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gpu: nvgpu: update super surface for igpu

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Add supper surface gpu_va details to super surface header member
as needed by PMU ucode to process.
This is required for iGPU PMU ucode on nvgpu-next to process command
line args and ACK back with INIT message, without this PMU ucode ends
up in hang due to DMA wait.
Update super-surface details to cmd line args for PMU ucode to
know the starting address of super-surface in SYSMEM.

JIRA NVGPU-5186

Change-Id: I56d7d3e28527e46707663c97bc8e2a58000c7f5a
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2376364
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
mkumbar
2020-07-16 13:21:39 +05:30
committed by Alex Waterman
parent e6a3540ec1
commit 3f75e62c26
2 changed files with 19 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c
View File

@@ -107,6 +107,10 @@ int nvgpu_pmu_ns_fw_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu)
pmu->fw->ops.set_cmd_line_args_cpu_freq(pmu,
g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
if (pmu->fw->ops.config_cmd_line_args_super_surface != NULL) {
pmu->fw->ops.config_cmd_line_args_super_surface(pmu);
}
nvgpu_pmu_fw_get_cmd_line_args_offset(g, &args_offset);
err = nvgpu_falcon_copy_to_dmem(pmu->flcn, args_offset,

15
drivers/gpu/nvgpu/common/pmu/super_surface/super_surface.c
View File

@@ -32,6 +32,7 @@ int nvgpu_pmu_super_surface_buf_alloc(struct gk20a *g, struct nvgpu_pmu *pmu,
{
struct vm_gk20a *vm = g->mm.pmu.vm;
int err = 0;
u32 tmp = 0;
nvgpu_log_fn(g, " ");
@@ -43,8 +44,22 @@ int nvgpu_pmu_super_surface_buf_alloc(struct gk20a *g, struct nvgpu_pmu *pmu,
&ss->super_surface_buf);
if (err != 0) {
nvgpu_err(g, "failed to allocate pmu suffer surface\n");
return err;
}
/* store the gpu_va in super-surface header for PMU ucode to access */
tmp = u64_lo32(ss->super_surface_buf.gpu_va);
nvgpu_mem_wr_n(g, nvgpu_pmu_super_surface_mem(g,
pmu, pmu->super_surface),
(u64)offsetof(struct super_surface, hdr.data.address.lo),
&tmp, sizeof(u32));
tmp = u64_hi32(ss->super_surface_buf.gpu_va);
nvgpu_mem_wr_n(g, nvgpu_pmu_super_surface_mem(g,
pmu, pmu->super_surface),
(u64)offsetof(struct super_surface, hdr.data.address.hi),
&tmp, sizeof(u32));
return err;
}