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gpu: nvgpu: gmmu: fix MISRA 16.x violations in gmmu.h

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MISRA rules 16.x enforce specific switch statement formats including
always having a break. Fix MISRA 16.x violations in gmmu.h.

JIRA NVGPU-3340

Change-Id: Ic03878265e84a571c128c59ba5eee6c83a725a67
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110596
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-05-02 14:29:29 -04:00
committed by mobile promotions
parent 93cfec16a9
commit 4222052a53
1 changed files with 11 additions and 4 deletions
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15
drivers/gpu/nvgpu/include/nvgpu/gmmu.h
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@@ -114,16 +114,23 @@ struct gk20a_mmu_level {
static inline const char *nvgpu_gmmu_perm_str(enum gk20a_mem_rw_flag p)
{
const char *str;
switch (p) {
case gk20a_mem_flag_none:
return "RW";
str = "RW";
break;
case gk20a_mem_flag_write_only:
return "WO";
str = "WO";
break;
case gk20a_mem_flag_read_only:
return "RO";
str = "RO";
break;
default:
return "??";
str = "??";
break;
}
return str;
}
int nvgpu_gmmu_init_page_table(struct vm_gk20a *vm);