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gpu: nvgpu: fix MISRA violations common.gr.ctx

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Rule 10.6 forbids assignment of an 32-bit expression to a 64-bit target.
This patch fixes MISRA 10.6 errors in common/gr/ctx.c

Jira NVGPU-3808

Change-Id: I02bc42040e494b230d51aa5c3ae035dd5e3ad9aa
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152643
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-07-12 15:35:47 -07:00
committed by mobile promotions
parent 39eef61416
commit 42440a161a
1 changed files with 4 additions and 2 deletions
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6
drivers/gpu/nvgpu/common/gr/ctx.c
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@@ -467,8 +467,10 @@ void nvgpu_gr_ctx_patch_write(struct gk20a *g,
return;
}
nvgpu_mem_wr32(g, &gr_ctx->patch_ctx.mem, patch_slot, addr);
nvgpu_mem_wr32(g, &gr_ctx->patch_ctx.mem, patch_slot + 1U, data);
nvgpu_mem_wr32(g, &gr_ctx->patch_ctx.mem,
(u64)patch_slot, addr);
nvgpu_mem_wr32(g, &gr_ctx->patch_ctx.mem,
(u64)patch_slot + 1ULL, data);
gr_ctx->patch_ctx.data_count = nvgpu_safe_add_u32(
gr_ctx->patch_ctx.data_count, 1U);
nvgpu_log(g, gpu_dbg_info,