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gpu: nvgpu: move mailbox0 write to engine bl_bootstrap

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Semantics of the engine bootloader bootstrap are to set falcon mailbox0
register to non-zero value and verify that it is cleared to ascertain
successful completion of bootstrap.
Read was done in the engine bl_bootstrap related functions. Hence move
the write as well to those functions.

JIRA NVGPU-1993

Change-Id: I6d04148fbf1d517f0af8b4cfc2ee144d38704647
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034511
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-03-06 23:10:14 +05:30
committed by mobile promotions
parent 9f68fecb64
commit 45ee7baab1
5 changed files with 8 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -656,8 +656,6 @@ int nvgpu_falcon_bl_bootstrap(struct nvgpu_falcon *flcn,
goto exit;
}
nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_0, 0xDEADA5A5U);
virt_addr = bl_info->bl_start_tag << 8;
err = nvgpu_falcon_bootstrap(flcn, virt_addr);

2
drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c
View File

@@ -374,6 +374,8 @@ static int gm20b_bl_bootstrap(struct gk20a *g,
pwr_pmu_new_instblk_target_sys_coh_f() :
pwr_pmu_new_instblk_target_sys_ncoh_f())) ;
nvgpu_falcon_mailbox_write(g->pmu.flcn, FALCON_MAILBOX_0, 0xDEADA5A5U);
return nvgpu_falcon_bl_bootstrap(g->pmu.flcn, bl_info);
}

2
drivers/gpu/nvgpu/gp106/sec2_gp106.c
View File

@@ -77,6 +77,8 @@ static int sec2_flcn_bl_bootstrap(struct gk20a *g,
data |= BIT32(3);
gk20a_writel(g, psec_falcon_engctl_r(), data);
nvgpu_falcon_mailbox_write(g->sec2.flcn, FALCON_MAILBOX_0, 0xDEADA5A5U);
err = nvgpu_falcon_bl_bootstrap(g->sec2.flcn, bl_info);
return err;

2
drivers/gpu/nvgpu/gv100/gsp_gv100.c
View File

@@ -68,6 +68,8 @@ static int gsp_flcn_bl_bootstrap(struct gk20a *g,
data |= pgsp_falcon_engctl_switch_context_true_f();
gk20a_writel(g, pgsp_falcon_engctl_r(), data);
nvgpu_falcon_mailbox_write(g->gsp_flcn, FALCON_MAILBOX_0, 0xDEADA5A5U);
status = nvgpu_falcon_bl_bootstrap(g->gsp_flcn, bl_info);
return status;

2
drivers/gpu/nvgpu/tu104/sec2_tu104.c
View File

@@ -202,6 +202,8 @@ static int tu104_sec2_flcn_bl_bootstrap(struct gk20a *g,
data |= (1U << 3U);
gk20a_writel(g, psec_falcon_engctl_r(), data);
nvgpu_falcon_mailbox_write(g->sec2.flcn, FALCON_MAILBOX_0, 0xDEADA5A5U);
return nvgpu_falcon_bl_bootstrap(g->sec2.flcn, bl_info);
}