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gpu: nvgpu: fix MISRA 5.7 in hal class

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Avoid issue with type_declaration: Declaring a type with
identifier "class" by renaming class hal as gpu_class hal.

JIRA NVGPU-3421

Change-Id: I0b285be7c86dc13f9a608d1470a610ddb33f241b
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114175
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-05-07 15:21:04 -07:00
committed by mobile promotions
parent 557c67fa30
commit 47f652e0f9
11 changed files with 27 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/gr/gr_setup.c
View File

@@ -102,7 +102,7 @@ int nvgpu_gr_setup_alloc_obj_ctx(struct nvgpu_channel *c, u32 class_num,
return -EINVAL;
}
if (!g->ops.class.is_valid(class_num)) {
if (!g->ops.gpu_class.is_valid(class_num)) {
nvgpu_err(g,
"invalid obj class 0x%x", class_num);
err = -EINVAL;

10
drivers/gpu/nvgpu/common/gr/obj_ctx.c
View File

@@ -74,7 +74,7 @@ static int nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode(struct gk20a *g,
nvgpu_log_fn(g, " ");
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP)) {
if (g->ops.class.is_valid_compute(class_num)) {
if (g->ops.gpu_class.is_valid_compute(class_num)) {
nvgpu_gr_ctx_init_compute_preemption_mode(gr_ctx,
NVGPU_PREEMPTION_MODE_COMPUTE_CTA);
}
@@ -115,12 +115,12 @@ int nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(struct gk20a *g,
return 0;
}
if (g->ops.class.is_valid_gfx(class_num) &&
if (g->ops.gpu_class.is_valid_gfx(class_num) &&
nvgpu_gr_ctx_desc_force_preemption_gfxp(gr_ctx_desc)) {
graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
}
if (g->ops.class.is_valid_compute(class_num) &&
if (g->ops.gpu_class.is_valid_compute(class_num) &&
nvgpu_gr_ctx_desc_force_preemption_cilp(gr_ctx_desc)) {
compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
}
@@ -185,8 +185,8 @@ int nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(struct gk20a *g,
break;
}
if (g->ops.class.is_valid_compute(class_num) ||
g->ops.class.is_valid_gfx(class_num)) {
if (g->ops.gpu_class.is_valid_compute(class_num) ||
g->ops.gpu_class.is_valid_gfx(class_num)) {
switch (compute_preempt_mode) {
case NVGPU_PREEMPTION_MODE_COMPUTE_WFI:
case NVGPU_PREEMPTION_MODE_COMPUTE_CTA:

4
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -364,7 +364,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.flush_channel_tlb = nvgpu_gr_intr_flush_channel_tlb,
},
},
.class = {
.gpu_class = {
.is_valid = gp10b_class_is_valid,
.is_valid_gfx = gp10b_class_is_valid_gfx,
.is_valid_compute = gp10b_class_is_valid_compute,
@@ -769,7 +769,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
gops->cbc = vgpu_gp10b_ops.cbc;
gops->ce = vgpu_gp10b_ops.ce;
gops->gr = vgpu_gp10b_ops.gr;
gops->class = vgpu_gp10b_ops.class;
gops->gpu_class = vgpu_gp10b_ops.gpu_class;
gops->gr.ctxsw_prog = vgpu_gp10b_ops.gr.ctxsw_prog;
gops->gr.config = vgpu_gp10b_ops.gr.config;
gops->fb = vgpu_gp10b_ops.fb;

12
drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c
View File

@@ -230,7 +230,7 @@ int vgpu_gr_alloc_obj_ctx(struct nvgpu_channel *c, u32 class_num, u32 flags)
return -EINVAL;
}
if (!g->ops.class.is_valid(class_num)) {
if (!g->ops.gpu_class.is_valid(class_num)) {
nvgpu_err(g, "invalid obj class 0x%x", class_num);
err = -EINVAL;
goto out;
@@ -1245,10 +1245,10 @@ static int vgpu_gr_init_ctxsw_preemption_mode(struct gk20a *g,
if (priv->constants.force_preempt_mode && !graphics_preempt_mode &&
!compute_preempt_mode) {
graphics_preempt_mode = g->ops.class.is_valid_gfx(class) ?
graphics_preempt_mode = g->ops.gpu_class.is_valid_gfx(class) ?
NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP : 0;
compute_preempt_mode =
g->ops.class.is_valid_compute(class) ?
g->ops.gpu_class.is_valid_compute(class) ?
NVGPU_PREEMPTION_MODE_COMPUTE_CTA : 0;
}
@@ -1277,12 +1277,12 @@ static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g,
&msg.params.gr_bind_ctxsw_buffers;
int err = 0;
if (g->ops.class.is_valid_gfx(class) &&
if (g->ops.gpu_class.is_valid_gfx(class) &&
g->gr->gr_ctx_desc->force_preemption_gfxp) {
graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
}
if (g->ops.class.is_valid_compute(class) &&
if (g->ops.gpu_class.is_valid_compute(class) &&
g->gr->gr_ctx_desc->force_preemption_cilp) {
compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
}
@@ -1363,7 +1363,7 @@ static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g,
break;
}
if (g->ops.class.is_valid_compute(class)) {
if (g->ops.gpu_class.is_valid_compute(class)) {
switch (compute_preempt_mode) {
case NVGPU_PREEMPTION_MODE_COMPUTE_WFI:
nvgpu_gr_ctx_init_compute_preemption_mode(gr_ctx,

4
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -425,7 +425,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.flush_channel_tlb = nvgpu_gr_intr_flush_channel_tlb,
},
},
.class = {
.gpu_class = {
.is_valid = gv11b_class_is_valid,
.is_valid_gfx = gv11b_class_is_valid_gfx,
.is_valid_compute = gv11b_class_is_valid_compute,
@@ -859,7 +859,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
gops->cbc = vgpu_gv11b_ops.cbc;
gops->ce = vgpu_gv11b_ops.ce;
gops->gr = vgpu_gv11b_ops.gr;
gops->class = vgpu_gv11b_ops.class;
gops->gpu_class = vgpu_gv11b_ops.gpu_class;
gops->gr.ctxsw_prog = vgpu_gv11b_ops.gr.ctxsw_prog;
gops->gr.config = vgpu_gv11b_ops.gr.config;
gops->fb = vgpu_gv11b_ops.fb;

4
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -482,7 +482,7 @@ static const struct gpu_ops gm20b_ops = {
gm20b_gr_falcon_read_fecs_ctxsw_status1,
},
},
.class = {
.gpu_class = {
.is_valid = gm20b_class_is_valid,
.is_valid_gfx = gm20b_class_is_valid_gfx,
.is_valid_compute = gm20b_class_is_valid_compute,
@@ -980,7 +980,7 @@ int gm20b_init_hal(struct gk20a *g)
gops->cbc = gm20b_ops.cbc;
gops->ce = gm20b_ops.ce;
gops->gr = gm20b_ops.gr;
gops->class = gm20b_ops.class;
gops->gpu_class = gm20b_ops.gpu_class;
gops->gr.ctxsw_prog = gm20b_ops.gr.ctxsw_prog;
gops->gr.config = gm20b_ops.gr.config;
gops->fb = gm20b_ops.fb;

4
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -544,7 +544,7 @@ static const struct gpu_ops gp10b_ops = {
gm20b_gr_falcon_read_fecs_ctxsw_status1,
},
},
.class = {
.gpu_class = {
.is_valid = gp10b_class_is_valid,
.is_valid_gfx = gp10b_class_is_valid_gfx,
.is_valid_compute = gp10b_class_is_valid_compute,
@@ -1064,7 +1064,7 @@ int gp10b_init_hal(struct gk20a *g)
gops->cbc = gp10b_ops.cbc;
gops->ce = gp10b_ops.ce;
gops->gr = gp10b_ops.gr;
gops->class = gp10b_ops.class;
gops->gpu_class = gp10b_ops.gpu_class;
gops->gr.ctxsw_prog = gp10b_ops.gr.ctxsw_prog;
gops->gr.config = gp10b_ops.gr.config;
gops->fb = gp10b_ops.fb;

4
drivers/gpu/nvgpu/hal/init/hal_gv100.c
View File

@@ -658,7 +658,7 @@ static const struct gpu_ops gv100_ops = {
gm20b_gr_falcon_read_fecs_ctxsw_status1,
},
},
.class = {
.gpu_class = {
.is_valid = gv11b_class_is_valid,
.is_valid_gfx = gv11b_class_is_valid_gfx,
.is_valid_compute = gv11b_class_is_valid_compute,
@@ -1330,7 +1330,7 @@ int gv100_init_hal(struct gk20a *g)
gops->cbc = gv100_ops.cbc;
gops->ce = gv100_ops.ce;
gops->gr = gv100_ops.gr;
gops->class = gv100_ops.class;
gops->gpu_class = gv100_ops.gpu_class;
gops->gr.ctxsw_prog = gv100_ops.gr.ctxsw_prog;
gops->gr.config = gv100_ops.gr.config;
gops->fb = gv100_ops.fb;

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -632,7 +632,7 @@ static const struct gpu_ops gv11b_ops = {
gm20b_gr_falcon_read_fecs_ctxsw_status1,
},
},
.class = {
.gpu_class = {
.is_valid = gv11b_class_is_valid,
.is_valid_gfx = gv11b_class_is_valid_gfx,
.is_valid_compute = gv11b_class_is_valid_compute,
@@ -1220,7 +1220,7 @@ int gv11b_init_hal(struct gk20a *g)
gops->cbc = gv11b_ops.cbc;
gops->ce = gv11b_ops.ce;
gops->gr = gv11b_ops.gr;
gops->class = gv11b_ops.class;
gops->gpu_class = gv11b_ops.gpu_class;
gops->gr.ctxsw_prog = gv11b_ops.gr.ctxsw_prog;
gops->gr.config = gv11b_ops.gr.config;
gops->fb = gv11b_ops.fb;

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -693,7 +693,7 @@ static const struct gpu_ops tu104_ops = {
gm20b_gr_falcon_read_fecs_ctxsw_status1,
},
},
.class = {
.gpu_class = {
.is_valid = tu104_class_is_valid,
.is_valid_gfx = tu104_class_is_valid_gfx,
.is_valid_compute = tu104_class_is_valid_compute,
@@ -1377,7 +1377,7 @@ int tu104_init_hal(struct gk20a *g)
gops->cbc = tu104_ops.cbc;
gops->ce = tu104_ops.ce;
gops->gr = tu104_ops.gr;
gops->class = tu104_ops.class;
gops->gpu_class = tu104_ops.gpu_class;
gops->gr.ctxsw_prog = tu104_ops.gr.ctxsw_prog;
gops->gr.config = tu104_ops.gr.config;
gops->fb = tu104_ops.fb;

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -866,7 +866,7 @@ struct gpu_ops {
bool (*is_valid)(u32 class_num);
bool (*is_valid_gfx)(u32 class_num);
bool (*is_valid_compute)(u32 class_num);
} class;
} gpu_class;
struct {
void (*init_hw)(struct gk20a *g);