gpu: nvgpu: fix MISRA 16.x errors in hal class

Fixed issues related to switch case formatting.

JIRA NVGPU-3421

Change-Id: I5271b0ede0c400444e60d70bf05943461766bc59
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114174
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-05-07 13:50:36 -07:00
committed by mobile promotions
parent df7ffe8722
commit 557c67fa30
4 changed files with 36 additions and 40 deletions

View File

@@ -26,7 +26,7 @@
bool gm20b_class_is_valid(u32 class_num)
{
bool valid = false;
bool valid;
switch (class_num) {
case MAXWELL_COMPUTE_B:
@@ -38,6 +38,7 @@ bool gm20b_class_is_valid(u32 class_num)
break;
default:
valid = false;
break;
}

View File

@@ -23,11 +23,12 @@
#include <nvgpu/class.h>
#include <nvgpu/barrier.h>
#include "class_gm20b.h"
#include "class_gp10b.h"
bool gp10b_class_is_valid(u32 class_num)
{
bool valid = false;
bool valid;
nvgpu_speculation_barrier();
switch (class_num) {
@@ -36,16 +37,8 @@ bool gp10b_class_is_valid(u32 class_num)
case PASCAL_DMA_COPY_A:
valid = true;
break;
case MAXWELL_COMPUTE_B:
case MAXWELL_B:
case FERMI_TWOD_A:
case KEPLER_DMA_COPY_A:
case MAXWELL_DMA_COPY_A:
valid = true;
break;
default:
valid = gm20b_class_is_valid(class_num);
break;
}
return valid;

View File

@@ -23,32 +23,23 @@
#include <nvgpu/class.h>
#include <nvgpu/barrier.h>
#include "class_gp10b.h"
#include "class_gv11b.h"
bool gv11b_class_is_valid(u32 class_num)
{
bool valid = false;
bool valid;
nvgpu_speculation_barrier();
switch (class_num) {
case VOLTA_COMPUTE_A:
case VOLTA_A:
case VOLTA_DMA_COPY_A:
valid = true;
break;
case MAXWELL_COMPUTE_B:
case MAXWELL_B:
case FERMI_TWOD_A:
case KEPLER_DMA_COPY_A:
case MAXWELL_DMA_COPY_A:
case PASCAL_COMPUTE_A:
case PASCAL_A:
case PASCAL_DMA_COPY_A:
valid = true;
break;
default:
valid = gp10b_class_is_valid(class_num);
break;
}
return valid;
@@ -56,17 +47,16 @@ bool gv11b_class_is_valid(u32 class_num)
bool gv11b_class_is_valid_gfx(u32 class_num)
{
bool valid = false;
bool valid;
nvgpu_speculation_barrier();
switch (class_num) {
case VOLTA_A:
case PASCAL_A:
case MAXWELL_B:
valid = true;
break;
default:
valid = gp10b_class_is_valid_gfx(class_num);
break;
}
return valid;
@@ -74,17 +64,17 @@ bool gv11b_class_is_valid_gfx(u32 class_num)
bool gv11b_class_is_valid_compute(u32 class_num)
{
bool valid = false;
bool valid;
nvgpu_speculation_barrier();
switch (class_num) {
case VOLTA_COMPUTE_A:
case PASCAL_COMPUTE_A:
case MAXWELL_COMPUTE_B:
valid = true;
break;
default:
valid = gp10b_class_is_valid_compute(class_num);
break;
}
return valid;

View File

@@ -28,42 +28,54 @@
bool tu104_class_is_valid(u32 class_num)
{
bool valid;
nvgpu_speculation_barrier();
switch (class_num) {
case TURING_CHANNEL_GPFIFO_A:
case TURING_A:
case TURING_COMPUTE_A:
case TURING_DMA_COPY_A:
return true;
valid = true;
break;
default:
valid = gv11b_class_is_valid(class_num);
break;
}
return gv11b_class_is_valid(class_num);
return valid;
};
bool tu104_class_is_valid_gfx(u32 class_num)
{
bool valid;
nvgpu_speculation_barrier();
switch (class_num) {
case TURING_A:
return true;
valid = true;
break;
default:
valid = gv11b_class_is_valid_gfx(class_num);
break;
}
return gv11b_class_is_valid_gfx(class_num);
return valid;
}
bool tu104_class_is_valid_compute(u32 class_num)
{
bool valid;
nvgpu_speculation_barrier();
switch (class_num) {
case TURING_COMPUTE_A:
return true;
valid = true;
break;
default:
valid = gv11b_class_is_valid_compute(class_num);
break;
}
return gv11b_class_is_valid_compute(class_num);
return valid;
}