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gpu: nvgpu: Use gr_instance specific api to query the num of sm

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Replaced get_no_of_sm() with gr_instance specific api
nvgpu_gr_config_get_no_of_sm()

JIRA NVGPU-5656

Change-Id: I01b786402dde857e7cc30d5370429d02ebe3f428
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2543245
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Lakshmanan M
2021-06-11 15:59:34 +05:30
committed by mobile promotions
parent c4dee40c49
commit 4a3a9d46e3
5 changed files with 10 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
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@@ -1902,10 +1902,10 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
int err; int err;
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch); struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch);
u32 flags = NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE; u32 flags = NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g); struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
if (tsg == NULL) { if (tsg == NULL) {
return -EINVAL; return -EINVAL;
@@ -2124,15 +2124,14 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state)
u32 no_of_sm; u32 no_of_sm;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g); struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
if((g->ops.gr.init.get_no_of_sm == NULL) || if ((g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask == NULL) ||
(g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask == NULL) ||
(g->ops.gr.lock_down_sm == NULL) || (g->ops.gr.lock_down_sm == NULL) ||
(g->ops.gr.bpt_reg_info == NULL) || (g->ops.gr.bpt_reg_info == NULL) ||
(g->ops.gr.sm_debugger_attached == NULL)) { (g->ops.gr.sm_debugger_attached == NULL)) {
return -EINVAL; return -EINVAL;
} }
no_of_sm = g->ops.gr.init.get_no_of_sm(g); no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
if (!g->ops.gr.sm_debugger_attached(g)) { if (!g->ops.gr.sm_debugger_attached(g)) {
nvgpu_err(g, nvgpu_err(g,

2
drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c
View File

@@ -432,7 +432,7 @@ void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0; u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0;
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g); u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
/* for maxwell & kepler */ /* for maxwell & kepler */
u32 numSmPerTpc = 1; u32 numSmPerTpc = 1;

4
drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
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@@ -800,7 +800,7 @@ void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
u32 gpc, tpc, sm, sm_id; u32 gpc, tpc, sm, sm_id;
u32 offset; u32 offset;
u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0; u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0;
u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g); u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
for (sm_id = 0; sm_id < no_of_sm; sm_id++) { for (sm_id = 0; sm_id < no_of_sm; sm_id++) {
struct nvgpu_sm_info *sm_info = struct nvgpu_sm_info *sm_info =
@@ -867,11 +867,11 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
{ {
struct nvgpu_dbg_reg_op *ops; struct nvgpu_dbg_reg_op *ops;
unsigned int i = 0, sm_id; unsigned int i = 0, sm_id;
u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
int err; int err;
struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch); struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch);
u32 flags = NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE; u32 flags = NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g); struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 no_of_sm = nvgpu_gr_config_get_no_of_sm(gr->config);
if (tsg == NULL) { if (tsg == NULL) {
nvgpu_err(g, "gv11b_gr_set_sm_debug_mode failed=>tsg NULL"); nvgpu_err(g, "gv11b_gr_set_sm_debug_mode failed=>tsg NULL");

2
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
View File

@@ -759,7 +759,7 @@ int gv11b_gr_init_commit_sm_id_programming(struct gk20a *g,
u32 *tpc_sm_id; u32 *tpc_sm_id;
u32 sm_id_size = g->ops.gr.init.get_sm_id_size(); u32 sm_id_size = g->ops.gr.init.get_sm_id_size();
for (sm_id = 0; sm_id < g->ops.gr.init.get_no_of_sm(g); for (sm_id = 0; sm_id < nvgpu_gr_config_get_no_of_sm(config);
sm_id++) { sm_id++) {
struct nvgpu_sm_info *sm_info = struct nvgpu_sm_info *sm_info =
((gr_ctx == NULL) || ((gr_ctx == NULL) ||

4
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -855,8 +855,10 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
struct warpstate *ioctl_w_state; struct warpstate *ioctl_w_state;
struct nvgpu_warpstate *w_state = NULL; struct nvgpu_warpstate *w_state = NULL;
u32 ioctl_size, size, sm_id, no_of_sm; u32 ioctl_size, size, sm_id, no_of_sm;
struct nvgpu_gr_config *gr_config =
nvgpu_gr_get_gr_instance_config_ptr(g, gr_instance_id);
no_of_sm = g->ops.gr.init.get_no_of_sm(g); no_of_sm = nvgpu_gr_config_get_no_of_sm(gr_config);
ioctl_size = no_of_sm * sizeof(struct warpstate); ioctl_size = no_of_sm * sizeof(struct warpstate);
ioctl_w_state = nvgpu_kzalloc(g, ioctl_size); ioctl_w_state = nvgpu_kzalloc(g, ioctl_size);