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gpu: nvgpu: fix MISRA violations in common.gr

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1. misra_c_2012_rule_8_6_violation: "gm20b_gr_init_fe_go_idle_timeout"
   is declared but never defined.

Fix by adding config CONFIG_NVGPU_HAL_NON_FUSA for header declaration
of "gm20b_gr_init_fe_go_idle_timeout"

2. misra_c_2012_rule_5_7_violation: Identifier "ops" is already used
   to represent a type.

Fix by renaming local variable ops to nonstall_ops in
gm20b_gr_intr_nonstall_isr()

3. missing_default: No default case found for the switch statement
   "switch (offset << 2)"

Fix by adding break and default statements to switch case in
gv11b_gr_intr_handle_sw_method()

Jira NVGPU-6779

Change-Id: I8df097ec66479edcd2e81bf46bab5b5db52ac8c8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2541246
(cherry picked from commit c4d9fe0449f8c6ee209051abfe58c6f3a745808d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2543012
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2021-06-08 16:20:24 +05:30
committed by mobile promotions
parent a9e1c19f44
commit c4dee40c49
3 changed files with 41 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,7 +53,9 @@ int gm20b_gr_init_wait_idle(struct gk20a *g);
int gm20b_gr_init_wait_fe_idle(struct gk20a *g);
int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on);
void gm20b_gr_init_override_context_reset(struct gk20a *g);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gm20b_gr_init_fe_go_idle_timeout(struct gk20a *g, bool enable);
#endif
void gm20b_gr_init_pipe_mode_override(struct gk20a *g, bool enable);
void gm20b_gr_init_load_method_init(struct gk20a *g,
struct netlist_av_list *sw_method_init);

6
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c
View File

@@ -373,7 +373,7 @@ void gm20b_gr_intr_enable_interrupts(struct gk20a *g, bool enable)
u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g)
{
u32 ops = 0;
u32 nonstall_ops = 0;
u32 gr_intr = nvgpu_readl(g, gr_intr_nonstall_r());
nvgpu_log(g, gpu_dbg_intr, "pgraph nonstall intr %08x", gr_intr);
@@ -382,10 +382,10 @@ u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g)
/* Clear the interrupt */
nvgpu_writel(g, gr_intr_nonstall_r(),
gr_intr_nonstall_trap_pending_f());
ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
nonstall_ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_CIC_NONSTALL_OPS_POST_EVENTS);
}
return ops;
return nonstall_ops;
}
#ifdef CONFIG_NVGPU_DEBUGGER

50
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
View File

@@ -179,6 +179,8 @@ void gv11b_gr_intr_set_shader_cut_collector(struct gk20a *g, u32 data)
int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data)
{
int err = -EFAULT;
nvgpu_log_fn(g, " ");
if (class_num == VOLTA_COMPUTE_A) {
@@ -186,56 +188,74 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
case NVC0C0_SET_SHADER_EXCEPTIONS:
g->ops.gr.intr.set_shader_exceptions(g, data);
return 0;
err = 0;
break;
#endif
case NVC3C0_SET_SKEDCHECK:
gv11b_gr_intr_set_skedcheck(g, data);
return 0;
err = 0;
break;
case NVC3C0_SET_SHADER_CUT_COLLECTOR:
gv11b_gr_intr_set_shader_cut_collector(g, data);
return 0;
err = 0;
break;
default:
err = -EINVAL;
break;
}
}
#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)
if (class_num == VOLTA_A) {
switch (offset << 2) {
case NVC397_SET_SHADER_EXCEPTIONS:
g->ops.gr.intr.set_shader_exceptions(g, data);
return 0;
err = 0;
break;
case NVC397_SET_CIRCULAR_BUFFER_SIZE:
g->ops.gr.set_circular_buffer_size(g, data);
return 0;
err = 0;
break;
case NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
g->ops.gr.set_alpha_circular_buffer_size(g, data);
return 0;
err = 0;
break;
case NVC397_SET_GO_IDLE_TIMEOUT:
gp10b_gr_intr_set_go_idle_timeout(g, data);
return 0;
err = 0;
break;
case NVC097_SET_COALESCE_BUFFER_SIZE:
gv11b_gr_intr_set_coalesce_buffer_size(g, data);
return 0;
err = 0;
break;
case NVC397_SET_TEX_IN_DBG:
gv11b_gr_intr_set_tex_in_dbg(g, data);
return 0;
err = 0;
break;
case NVC397_SET_SKEDCHECK:
gv11b_gr_intr_set_skedcheck(g, data);
return 0;
err = 0;
break;
case NVC397_SET_BES_CROP_DEBUG3:
g->ops.gr.set_bes_crop_debug3(g, data);
return 0;
err = 0;
break;
case NVC397_SET_BES_CROP_DEBUG4:
g->ops.gr.set_bes_crop_debug4(g, data);
return 0;
err = 0;
break;
case NVC397_SET_SHADER_CUT_COLLECTOR:
gv11b_gr_intr_set_shader_cut_collector(g, data);
return 0;
err = 0;
break;
default:
err = -EINVAL;
break;
}
}
#endif
return -EINVAL;
return err;
}
void gv11b_gr_intr_handle_gcc_exception(struct gk20a *g, u32 gpc,