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gpu: nvgpu: Enable the reporting of PRI access violation

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- Enable the reporting of PRI access violation.
- While enabling PRI access violation, it has been found that PRI timeout
  reporting was added part of ptimer. Since both PRI timeout and access
  violation are logically co-related, we have decided to add them as part
  of PRIV_RING.

Jira NVGPU-3087

Change-Id: I5543f1b5d0ab01354ffff16c172a635b2df1fd26
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087824
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2019-04-02 19:56:07 +05:30
committed by mobile promotions
parent 0e82e8d6c3
commit 4ad98e87ad
4 changed files with 26 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/ptimer/ptimer_gk20a.c
View File

@@ -69,8 +69,8 @@ void gk20a_ptimer_isr(struct gk20a *g)
error_addr = 0U;
}
if (g->ops.ptimer.err_ops.report_timeout_err != NULL) {
ret = g->ops.ptimer.err_ops.report_timeout_err(g,
if (g->ops.priv_ring.err_ops.report_timeout_err != NULL) {
ret = g->ops.priv_ring.err_ops.report_timeout_err(g,
NVGPU_ERR_MODULE_PRI,
inst,
GPU_PRI_TIMEOUT_ERROR,

14
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b.c
View File

@@ -68,6 +68,20 @@ void gp10b_priv_ring_decode_error_code(struct gk20a *g,
u32 error_code)
{
u32 error_type_index;
int ret = 0;
if (g->ops.priv_ring.err_ops.report_access_violation != NULL) {
ret = g->ops.priv_ring.err_ops.report_access_violation (g,
NVGPU_ERR_MODULE_PRI,
0U,
GPU_PRI_ACCESS_VIOLATION,
0U,
error_code);
if (ret != 0) {
nvgpu_err(g, "Failed to report PRI access violation: "
"err_code=%u", error_code);
}
}
error_type_index = (error_code & 0x00000f00U) >> 8U;
error_code = error_code & 0xBADFf000U;

13
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1602,11 +1602,6 @@ struct gpu_ops {
int (*get_timestamps_zipper)(struct gk20a *g,
u32 source_id, u32 count,
struct nvgpu_cpu_time_correlation_sample *samples);
struct {
int (*report_timeout_err)(struct gk20a *g,
u32 hw_id, u32 inst, u32 err_id,
u32 err_addr, u32 error_code);
} err_ops;
} ptimer;
struct {
@@ -1692,6 +1687,14 @@ struct gpu_ops {
u32 (*enum_ltc)(struct gk20a *g);
u32 (*get_gpc_count)(struct gk20a *g);
u32 (*get_fbp_count)(struct gk20a *g);
struct {
int (*report_access_violation)(struct gk20a *g,
u32 hw_id, u32 inst, u32 err_id,
u32 err_addr, u32 error_code);
int (*report_timeout_err)(struct gk20a *g,
u32 hw_id, u32 inst, u32 err_id,
u32 err_addr, u32 error_code);
} err_ops;
} priv_ring;
struct {
int (*check_priv_security)(struct gk20a *g);

3
drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h
View File

@@ -161,7 +161,8 @@ struct gr_exception_info {
#define GPU_HUBMMU_PDE0_DATA_ECC_CORRECTED 6U
#define GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED 7U
#define GPU_PRI_TIMEOUT_ERROR 0U
#define GPU_PRI_TIMEOUT_ERROR 0U
#define GPU_PRI_ACCESS_VIOLATION 1U
#define GPU_CE_LAUNCH_ERROR 0U
#define GPU_CE_BLOCK_PIPE 1U