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gpu: nvgpu: add helper function for fecs dmem data

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Added helper function gm20b_gr_falcon_update_fecs_dmem_data
programming fecs dmem data. With using this helper function,
avoid repeating same code twice.

JIRA NVGPU-3226

Change-Id: I490cc6b5ed6a1df5bcd0590833c8f9b83661d538
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111750
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-05-03 17:30:51 -07:00
committed by mobile promotions
parent 4c4f45e7eb
commit 4e9534c243
1 changed files with 23 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

57
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c
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@@ -317,6 +317,25 @@ void gm20b_gr_falcon_bind_instblk(struct gk20a *g,
}
static void gm20b_gr_falcon_program_fecs_dmem_data(struct gk20a *g,
u32 reg_offset, u32 addr_code32, u32 addr_data32,
u32 code_size, u32 data_size)
{
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 4);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), addr_code32);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), code_size);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), addr_data32);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), data_size);
}
void gm20b_gr_falcon_load_ctxsw_ucode_header(struct gk20a *g,
u32 reg_offset, u32 boot_signature, u32 addr_code32,
u32 addr_data32, u32 code_size, u32 data_size)
@@ -347,46 +366,16 @@ void gm20b_gr_falcon_load_ctxsw_ucode_header(struct gk20a *g,
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 4);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
addr_code32);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
code_size);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
addr_data32);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
data_size);
gm20b_gr_falcon_program_fecs_dmem_data(g, reg_offset,
addr_code32, addr_data32, code_size, data_size);
break;
case FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED:
case FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED:
case FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED:
case FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED2:
case FALCON_UCODE_SIG_T21X_GPCCS_WITHOUT_RESERVED:
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 4);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
addr_code32);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
code_size);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
addr_data32);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
data_size);
gm20b_gr_falcon_program_fecs_dmem_data(g, reg_offset,
addr_code32, addr_data32, code_size, data_size);
break;
case FALCON_UCODE_SIG_T12X_FECS_OLDER:
case FALCON_UCODE_SIG_T12X_GPCCS_OLDER: