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gpu: nvgpu: fix MISRA 17.7 in hal ltc driver
Add error check for return value from function nvgpu_timeout_init. JIRA NVGPU-3422 Change-Id: Ie89f689539086c5990f0856022aa4e5c4099e190 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2119970 GVS: Gerrit_Virtual_Submit Reviewed-by: Philip Elcan <pelcan@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -77,6 +77,7 @@ void gm20b_flush_ltc(struct gk20a *g)
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u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
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bool is_clean_pending_set = false;
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bool is_invalidate_pending_set = false;
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int err;
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/* Clean... */
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nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_cmgmt1_r(),
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@@ -108,7 +109,11 @@ void gm20b_flush_ltc(struct gk20a *g)
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*
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* So 5ms timeout here should be more than sufficient.
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*/
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nvgpu_timeout_init(g, &timeout, 5, NVGPU_TIMER_CPU_TIMER);
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err = nvgpu_timeout_init(g, &timeout, 5, NVGPU_TIMER_CPU_TIMER);
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if (err != 0) {
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nvgpu_err(g, "nvgpu_timeout_init failed err=%d", err);
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return;
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}
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do {
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int cmgmt1 = ltc_ltc0_ltss_tstg_cmgmt1_r() +
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@@ -134,7 +139,11 @@ void gm20b_flush_ltc(struct gk20a *g)
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u32 op_pending;
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/* Again, 5ms. */
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nvgpu_timeout_init(g, &timeout, 5, NVGPU_TIMER_CPU_TIMER);
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err = nvgpu_timeout_init(g, &timeout, 5, NVGPU_TIMER_CPU_TIMER);
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if (err != 0) {
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nvgpu_err(g, "nvgpu_timeout_init failed err=%d", err);
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return;
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}
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do {
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int cmgmt0 = ltc_ltc0_ltss_tstg_cmgmt0_r() +
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