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gpu: nvgpu: Generalize BIOS code

Browse Source 
Most of BIOS parsing code is not specific to any particular GPU. Move
most of the code to generic files, and leave only chip specific parts
dealing with microcontroller boot into chip specific files.

As most of the parsing is generic, they do not need to be called via
HALs so remove the HALs and change the calls into direct function
calls.

All definitions meant to be used outside BIOS code itself are now in
<nvgpu/bios.h>

Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302222
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Terje Bergstrom
2017-02-09 08:17:47 -08:00
committed by mobile promotions
parent 29a79e6b80
commit 53465def64
34 changed files with 911 additions and 1019 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/Makefile.nvgpu
View File

@@ -33,6 +33,7 @@ nvgpu-y := \
common/mm/lockless_allocator.o \
common/nvgpu_common.o \
common/semaphore.o \
common/vbios/bios.o \
gk20a/gk20a.o \
gk20a/sched_gk20a.o \
gk20a/as_gk20a.o \
@@ -160,7 +161,6 @@ nvgpu-y += \
gp106/fifo_gp106.o \
gp106/ltc_gp106.o \
gp106/fb_gp106.o \
gp106/bios_gp106.o \
gp106/regops_gp106.o \
clk/clk_mclk.o \
pstate/pstate.o \

9
drivers/gpu/nvgpu/clk/clk_domain.c
View File

@@ -11,14 +11,14 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "clk.h"
#include "clk_fll.h"
#include "clk_domain.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
@@ -261,10 +261,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs)
return -EINVAL;
clocks_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
clocks_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.clock_token, CLOCKS_TABLE);
if (clocks_table_ptr == NULL) {
status = -EINVAL;

9
drivers/gpu/nvgpu/clk/clk_fll.c
View File

@@ -11,13 +11,13 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "clk.h"
#include "clk_fll.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
@@ -234,10 +234,7 @@ static u32 devinit_get_fll_device_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs)
return -EINVAL;
fll_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
fll_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.clock_token, FLL_TABLE);
if (fll_table_ptr == NULL) {
status = -1;

19
drivers/gpu/nvgpu/clk/clk_freq_controller.c
View File

@@ -11,15 +11,15 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "clk.h"
#include "clk_fll.h"
#include "clk_domain.h"
#include "clk_freq_controller.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
@@ -185,16 +185,11 @@ static u32 clk_get_freq_controller_table(struct gk20a *g,
};
} freq_controller_data;
if (g->ops.bios.get_perf_table_ptrs) {
pfreq_controller_table_ptr =
(u8 *)g->ops.bios.get_perf_table_ptrs(g,
g->bios.clock_token,
FREQUENCY_CONTROLLER_TABLE);
if (pfreq_controller_table_ptr == NULL) {
status = -EINVAL;
goto done;
}
} else {
pfreq_controller_table_ptr =
(u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.clock_token,
FREQUENCY_CONTROLLER_TABLE);
if (pfreq_controller_table_ptr == NULL) {
status = -EINVAL;
goto done;
}

21
drivers/gpu/nvgpu/clk/clk_mclk.c
View File

@@ -13,12 +13,10 @@
#include <linux/delay.h>
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "gm206/bios_gm206.h"
#include "include/bios.h"
#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
#include <nvgpu/hw/gp106/hw_fb_gp106.h>
@@ -2022,12 +2020,7 @@ static int mclk_get_memclk_table(struct gk20a *g)
gk20a_dbg_info("");
if (!(g->ops.bios.get_perf_table_ptrs &&
g->ops.bios.execute_script)) {
goto done;
}
mem_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
mem_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token,
MEMORY_CLOCK_TABLE);
if (mem_table_ptr == NULL) {
@@ -2067,7 +2060,7 @@ static int mclk_get_memclk_table(struct gk20a *g)
script_index = BIOS_GET_FIELD(memclock_base_entry.flags1,
VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX);
script_ptr = gm206_bios_read_u32(g,
script_ptr = nvgpu_bios_read_u32(g,
memclock_table_header.script_list_ptr +
script_index * sizeof(u32));
@@ -2107,7 +2100,7 @@ static int mclk_get_memclk_table(struct gk20a *g)
fb_fbpa_fbio_delay_priv_m(),
fb_fbpa_fbio_delay_priv_f(shadow_idx)));
status = g->ops.bios.execute_script(g, script_ptr);
status = nvgpu_bios_execute_script(g, script_ptr);
if (status < 0) {
gk20a_writel(g, fb_fbpa_fbio_delay_r(),
old_fbio_delay);
@@ -2121,7 +2114,7 @@ static int mclk_get_memclk_table(struct gk20a *g)
cmd_script_index = BIOS_GET_FIELD(memclock_base_entry.flags2,
VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX);
cmd_script_ptr = gm206_bios_read_u32(g,
cmd_script_ptr = nvgpu_bios_read_u32(g,
memclock_table_header.cmd_script_list_ptr +
cmd_script_index * sizeof(u32));
@@ -2159,7 +2152,7 @@ static int mclk_get_memclk_table(struct gk20a *g)
fb_fbpa_fbio_cmd_delay_cmd_priv_f(
cmd_idx)));
status = g->ops.bios.execute_script(g, cmd_script_ptr);
status = nvgpu_bios_execute_script(g, cmd_script_ptr);
if (status < 0) {
gk20a_writel(g, fb_fbpa_fbio_cmd_delay_r(),
old_fbio_cmd_delay);

10
drivers/gpu/nvgpu/clk/clk_prog.c
View File

@@ -11,11 +11,12 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "clk.h"
#include "clk_prog.h"
#include "clk_vf_point.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
@@ -180,12 +181,7 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs) {
status = -EINVAL;
goto done;
}
clkprogs_tbl_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
clkprogs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.clock_token, CLOCK_PROGRAMMING_TABLE);
if (clkprogs_tbl_ptr == NULL) {
status = -EINVAL;

2
drivers/gpu/nvgpu/clk/clk_vf_point.c
View File

@@ -14,10 +14,8 @@
#include "gk20a/gk20a.h"
#include "clk.h"
#include "clk_vf_point.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"

10
drivers/gpu/nvgpu/clk/clk_vin.c
View File

@@ -11,9 +11,9 @@
* more details.
*/
#include "gk20a/gk20a.h"
#include <nvgpu/bios.h>
#include "include/bios.h"
#include "gk20a/gk20a.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
@@ -28,7 +28,6 @@
#include "clk.h"
#include "clk_vin.h"
#include <nvgpu/hw/gp106/hw_fuse_gp106.h>
static u32 devinit_get_vin_device_table(struct gk20a *g,
@@ -349,10 +348,7 @@ static u32 devinit_get_vin_device_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs)
return -EINVAL;
vin_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
vin_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.clock_token, VIN_TABLE);
if (vin_table_ptr == NULL) {
status = -1;

748
drivers/gpu/nvgpu/common/vbios/bios.c Normal file
View File

@@ -0,0 +1,748 @@
/*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <nvgpu/bios.h>
#include <nvgpu/hw/gp106/hw_gc6_gp106.h>
#include "gk20a/gk20a.h"
#define BIT_HEADER_ID 0xb8ff
#define BIT_HEADER_SIGNATURE 0x00544942
#define PCI_EXP_ROM_SIG 0xaa55
#define PCI_EXP_ROM_SIG_NV 0x4e56
#define INIT_DONE 0x71
#define INIT_RESUME 0x72
#define INIT_CONDITION 0x75
#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f
struct condition_entry {
u32 cond_addr;
u32 cond_mask;
u32 cond_compare;
} __packed;
static u16 nvgpu_bios_rdu16(struct gk20a *g, int offset)
{
u16 val = (g->bios.data[offset+1] << 8) + g->bios.data[offset];
return val;
}
static u32 nvgpu_bios_rdu32(struct gk20a *g, int offset)
{
u32 val = (g->bios.data[offset+3] << 24) +
(g->bios.data[offset+2] << 16) +
(g->bios.data[offset+1] << 8) +
g->bios.data[offset];
return val;
}
struct bit {
u16 id;
u32 signature;
u16 bcd_version;
u8 header_size;
u8 token_size;
u8 token_entries;
u8 header_checksum;
} __packed;
#define TOKEN_ID_BIOSDATA 0x42
#define TOKEN_ID_NVINIT_PTRS 0x49
#define TOKEN_ID_FALCON_DATA 0x70
#define TOKEN_ID_PERF_PTRS 0x50
#define TOKEN_ID_CLOCK_PTRS 0x43
#define TOKEN_ID_VIRT_PTRS 0x56
#define TOKEN_ID_MEMORY_PTRS 0x4D
union memory_ptrs {
struct {
u8 rsvd0[2];
u8 mem_strap_data_count;
u16 mem_strap_xlat_tbl_ptr;
u8 rsvd1[8];
} v1 __packed;
struct {
u8 mem_strap_data_count;
u16 mem_strap_xlat_tbl_ptr;
u8 rsvd[14];
} v2 __packed;
};
struct biosdata {
u32 version;
u8 oem_version;
u8 checksum;
u16 int15callbackspost;
u16 int16callbackssystem;
u16 boardid;
u16 framecount;
u8 biosmoddate[8];
} __packed;
struct nvinit_ptrs {
u16 initscript_table_ptr;
u16 macro_index_table_ptr;
u16 macro_table_ptr;
u16 condition_table_ptr;
u16 io_condition_table_ptr;
u16 io_flag_condition_table_ptr;
u16 init_function_table_ptr;
u16 vbios_private_table_ptr;
u16 data_arrays_table_ptr;
u16 pcie_settings_script_ptr;
u16 devinit_tables_ptr;
u16 devinit_tables_size;
u16 bootscripts_ptr;
u16 bootscripts_size;
u16 nvlink_config_data_ptr;
} __packed;
struct falcon_data_v2 {
u32 falcon_ucode_table_ptr;
} __packed;
struct falcon_ucode_table_hdr_v1 {
u8 version;
u8 header_size;
u8 entry_size;
u8 entry_count;
u8 desc_version;
u8 desc_size;
} __packed;
struct falcon_ucode_table_entry_v1 {
u8 application_id;
u8 target_id;
u32 desc_ptr;
} __packed;
#define TARGET_ID_PMU 0x01
#define APPLICATION_ID_DEVINIT 0x04
#define APPLICATION_ID_PRE_OS 0x01
struct falcon_ucode_desc_v1 {
union {
u32 v_desc;
u32 stored_size;
} hdr_size;
u32 uncompressed_size;
u32 virtual_entry;
u32 interface_offset;
u32 imem_phys_base;
u32 imem_load_size;
u32 imem_virt_base;
u32 imem_sec_base;
u32 imem_sec_size;
u32 dmem_offset;
u32 dmem_phys_base;
u32 dmem_load_size;
} __packed;
struct application_interface_table_hdr_v1 {
u8 version;
u8 header_size;
u8 entry_size;
u8 entry_count;
} __packed;
struct application_interface_entry_v1 {
u32 id;
u32 dmem_offset;
} __packed;
#define APPINFO_ID_DEVINIT 0x01
struct devinit_engine_interface {
u32 field0;
u32 field1;
u32 tables_phys_base;
u32 tables_virt_base;
u32 script_phys_base;
u32 script_virt_base;
u32 script_virt_entry;
u16 script_size;
u8 memory_strap_count;
u8 reserved;
u32 memory_information_table_virt_base;
u32 empty_script_virt_base;
u32 cond_table_virt_base;
u32 io_cond_table_virt_base;
u32 data_arrays_table_virt_base;
u32 gpio_assignment_table_virt_base;
} __packed;
struct pci_exp_rom {
u16 sig;
u8 reserved[0x16];
u16 pci_data_struct_ptr;
u32 size_of_block;
} __packed;
struct pci_data_struct {
u32 sig;
u16 vendor_id;
u16 device_id;
u16 device_list_ptr;
u16 pci_data_struct_len;
u8 pci_data_struct_rev;
u8 class_code[3];
u16 image_len;
u16 vendor_rom_rev;
u8 code_type;
u8 last_image;
u16 max_runtime_image_len;
} __packed;
struct pci_ext_data_struct {
u32 sig;
u16 nv_pci_data_ext_rev;
u16 nv_pci_data_ext_len;
u16 sub_image_len;
u8 priv_last_image;
u8 flags;
} __packed;
static void nvgpu_bios_parse_bit(struct gk20a *g, int offset);
int nvgpu_bios_parse_rom(struct gk20a *g)
{
int offset = 0;
int last = 0;
bool found = false;
unsigned int i;
while (!last) {
struct pci_exp_rom *pci_rom;
struct pci_data_struct *pci_data;
struct pci_ext_data_struct *pci_ext_data;
pci_rom = (struct pci_exp_rom *)&g->bios.data[offset];
gk20a_dbg_fn("pci rom sig %04x ptr %04x block %x",
pci_rom->sig, pci_rom->pci_data_struct_ptr,
pci_rom->size_of_block);
if (pci_rom->sig != PCI_EXP_ROM_SIG &&
pci_rom->sig != PCI_EXP_ROM_SIG_NV) {
gk20a_err(g->dev, "invalid VBIOS signature");
return -EINVAL;
}
pci_data =
(struct pci_data_struct *)
&g->bios.data[offset + pci_rom->pci_data_struct_ptr];
gk20a_dbg_fn("pci data sig %08x len %d image len %x type %x last %d max %08x",
pci_data->sig, pci_data->pci_data_struct_len,
pci_data->image_len, pci_data->code_type,
pci_data->last_image,
pci_data->max_runtime_image_len);
if (pci_data->code_type == 0x3) {
pci_ext_data = (struct pci_ext_data_struct *)
&g->bios.data[(offset +
pci_rom->pci_data_struct_ptr +
pci_data->pci_data_struct_len +
0xf)
& ~0xf];
gk20a_dbg_fn("pci ext data sig %08x rev %x len %x sub_image_len %x priv_last %d flags %x",
pci_ext_data->sig,
pci_ext_data->nv_pci_data_ext_rev,
pci_ext_data->nv_pci_data_ext_len,
pci_ext_data->sub_image_len,
pci_ext_data->priv_last_image,
pci_ext_data->flags);
gk20a_dbg_fn("expansion rom offset %x",
pci_data->image_len * 512);
g->bios.expansion_rom_offset =
pci_data->image_len * 512;
offset += pci_ext_data->sub_image_len * 512;
last = pci_ext_data->priv_last_image;
} else {
offset += pci_data->image_len * 512;
last = pci_data->last_image;
}
}
gk20a_dbg_info("read bios");
for (i = 0; i < g->bios.size - 6; i++) {
if (nvgpu_bios_rdu16(g, i) == BIT_HEADER_ID &&
nvgpu_bios_rdu32(g, i+2) == BIT_HEADER_SIGNATURE) {
nvgpu_bios_parse_bit(g, i);
found = true;
}
}
if (!found)
return -EINVAL;
else
return 0;
}
static void nvgpu_bios_parse_biosdata(struct gk20a *g, int offset)
{
struct biosdata biosdata;
memcpy(&biosdata, &g->bios.data[offset], sizeof(biosdata));
gk20a_dbg_fn("bios version %x, oem version %x",
biosdata.version,
biosdata.oem_version);
g->gpu_characteristics.vbios_version = biosdata.version;
g->gpu_characteristics.vbios_oem_version = biosdata.oem_version;
}
static void nvgpu_bios_parse_nvinit_ptrs(struct gk20a *g, int offset)
{
struct nvinit_ptrs nvinit_ptrs;
memcpy(&nvinit_ptrs, &g->bios.data[offset], sizeof(nvinit_ptrs));
gk20a_dbg_fn("devinit ptr %x size %d", nvinit_ptrs.devinit_tables_ptr,
nvinit_ptrs.devinit_tables_size);
gk20a_dbg_fn("bootscripts ptr %x size %d", nvinit_ptrs.bootscripts_ptr,
nvinit_ptrs.bootscripts_size);
g->bios.devinit_tables = &g->bios.data[nvinit_ptrs.devinit_tables_ptr];
g->bios.devinit_tables_size = nvinit_ptrs.devinit_tables_size;
g->bios.bootscripts = &g->bios.data[nvinit_ptrs.bootscripts_ptr];
g->bios.bootscripts_size = nvinit_ptrs.bootscripts_size;
g->bios.condition_table_ptr = nvinit_ptrs.condition_table_ptr;
}
static void nvgpu_bios_parse_memory_ptrs(struct gk20a *g, int offset, u8 version)
{
union memory_ptrs memory_ptrs;
if ((version < 1) || (version > 2))
return;
memcpy(&memory_ptrs, &g->bios.data[offset], sizeof(memory_ptrs));
g->bios.mem_strap_data_count = (version > 1) ? memory_ptrs.v2.mem_strap_data_count :
memory_ptrs.v1.mem_strap_data_count;
g->bios.mem_strap_xlat_tbl_ptr = (version > 1) ? memory_ptrs.v2.mem_strap_xlat_tbl_ptr :
memory_ptrs.v1.mem_strap_xlat_tbl_ptr;
}
static void nvgpu_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset)
{
struct devinit_engine_interface interface;
memcpy(&interface, &g->bios.devinit.dmem[dmem_offset], sizeof(interface));
gk20a_dbg_fn("devinit tables phys %x script phys %x size %d",
interface.tables_phys_base,
interface.script_phys_base,
interface.script_size);
g->bios.devinit_tables_phys_base = interface.tables_phys_base;
g->bios.devinit_script_phys_base = interface.script_phys_base;
}
static int nvgpu_bios_parse_appinfo_table(struct gk20a *g, int offset)
{
struct application_interface_table_hdr_v1 hdr;
int i;
memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
gk20a_dbg_fn("appInfoHdr ver %d size %d entrySize %d entryCount %d",
hdr.version, hdr.header_size,
hdr.entry_size, hdr.entry_count);
if (hdr.version != 1)
return 0;
offset += sizeof(hdr);
for (i = 0; i < hdr.entry_count; i++) {
struct application_interface_entry_v1 entry;
memcpy(&entry, &g->bios.data[offset], sizeof(entry));
gk20a_dbg_fn("appInfo id %d dmem_offset %d",
entry.id, entry.dmem_offset);
if (entry.id == APPINFO_ID_DEVINIT)
nvgpu_bios_parse_devinit_appinfo(g, entry.dmem_offset);
offset += hdr.entry_size;
}
return 0;
}
static int nvgpu_bios_parse_falcon_ucode_desc(struct gk20a *g,
struct nvgpu_bios_ucode *ucode, int offset)
{
struct falcon_ucode_desc_v1 desc;
memcpy(&desc, &g->bios.data[offset], sizeof(desc));
gk20a_dbg_info("falcon ucode desc stored size %d uncompressed size %d",
desc.hdr_size.stored_size, desc.uncompressed_size);
gk20a_dbg_info("falcon ucode desc virtualEntry %x, interfaceOffset %x",
desc.virtual_entry, desc.interface_offset);
gk20a_dbg_info("falcon ucode IMEM phys base %x, load size %x virt base %x sec base %x sec size %x",
desc.imem_phys_base, desc.imem_load_size,
desc.imem_virt_base, desc.imem_sec_base,
desc.imem_sec_size);
gk20a_dbg_info("falcon ucode DMEM offset %d phys base %x, load size %d",
desc.dmem_offset, desc.dmem_phys_base,
desc.dmem_load_size);
if (desc.hdr_size.stored_size != desc.uncompressed_size) {
gk20a_dbg_info("does not match");
return -EINVAL;
}
ucode->code_entry_point = desc.virtual_entry;
ucode->bootloader = &g->bios.data[offset] + sizeof(desc);
ucode->bootloader_phys_base = desc.imem_phys_base;
ucode->bootloader_size = desc.imem_load_size - desc.imem_sec_size;
ucode->ucode = ucode->bootloader + ucode->bootloader_size;
ucode->phys_base = ucode->bootloader_phys_base + ucode->bootloader_size;
ucode->size = desc.imem_sec_size;
ucode->dmem = ucode->bootloader + desc.dmem_offset;
ucode->dmem_phys_base = desc.dmem_phys_base;
ucode->dmem_size = desc.dmem_load_size;
return nvgpu_bios_parse_appinfo_table(g,
offset + sizeof(desc) +
desc.dmem_offset + desc.interface_offset);
}
static int nvgpu_bios_parse_falcon_ucode_table(struct gk20a *g, int offset)
{
struct falcon_ucode_table_hdr_v1 hdr;
int i;
memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
gk20a_dbg_fn("falcon ucode table ver %d size %d entrySize %d entryCount %d descVer %d descSize %d",
hdr.version, hdr.header_size,
hdr.entry_size, hdr.entry_count,
hdr.desc_version, hdr.desc_size);
if (hdr.version != 1)
return -EINVAL;
offset += hdr.header_size;
for (i = 0; i < hdr.entry_count; i++) {
struct falcon_ucode_table_entry_v1 entry;
memcpy(&entry, &g->bios.data[offset], sizeof(entry));
gk20a_dbg_fn("falcon ucode table entry appid %x targetId %x descPtr %x",
entry.application_id, entry.target_id,
entry.desc_ptr);
if (entry.target_id == TARGET_ID_PMU &&
entry.application_id == APPLICATION_ID_DEVINIT) {
int err;
err = nvgpu_bios_parse_falcon_ucode_desc(g,
&g->bios.devinit, entry.desc_ptr);
if (err)
err = nvgpu_bios_parse_falcon_ucode_desc(g,
&g->bios.devinit,
entry.desc_ptr +
g->bios.expansion_rom_offset);
if (err)
gk20a_err(dev_from_gk20a(g),
"could not parse devinit ucode desc");
} else if (entry.target_id == TARGET_ID_PMU &&
entry.application_id == APPLICATION_ID_PRE_OS) {
int err;
err = nvgpu_bios_parse_falcon_ucode_desc(g,
&g->bios.preos, entry.desc_ptr);
if (err)
err = nvgpu_bios_parse_falcon_ucode_desc(g,
&g->bios.preos,
entry.desc_ptr +
g->bios.expansion_rom_offset);
if (err)
gk20a_err(dev_from_gk20a(g),
"could not parse preos ucode desc");
}
offset += hdr.entry_size;
}
return 0;
}
static void nvgpu_bios_parse_falcon_data_v2(struct gk20a *g, int offset)
{
struct falcon_data_v2 falcon_data;
int err;
memcpy(&falcon_data, &g->bios.data[offset], sizeof(falcon_data));
gk20a_dbg_fn("falcon ucode table ptr %x",
falcon_data.falcon_ucode_table_ptr);
err = nvgpu_bios_parse_falcon_ucode_table(g,
falcon_data.falcon_ucode_table_ptr);
if (err)
err = nvgpu_bios_parse_falcon_ucode_table(g,
falcon_data.falcon_ucode_table_ptr +
g->bios.expansion_rom_offset);
if (err)
gk20a_err(dev_from_gk20a(g),
"could not parse falcon ucode table");
}
void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
struct bit_token *ptoken, u8 table_id)
{
u32 perf_table_id_offset = 0;
u8 *perf_table_ptr = NULL;
u8 data_size = 4;
if (ptoken != NULL) {
if (ptoken->token_id == TOKEN_ID_VIRT_PTRS) {
perf_table_id_offset = *((u16 *)&g->bios.data[
ptoken->data_ptr +
(table_id * PERF_PTRS_WIDTH_16)]);
data_size = PERF_PTRS_WIDTH_16;
} else {
perf_table_id_offset = *((u32 *)&g->bios.data[
ptoken->data_ptr +
(table_id * PERF_PTRS_WIDTH)]);
data_size = PERF_PTRS_WIDTH;
}
} else
return (void *)perf_table_ptr;
if (table_id < (ptoken->data_size/data_size)) {
gk20a_dbg_info("Perf_Tbl_ID-offset 0x%x Tbl_ID_Ptr-offset- 0x%x",
(ptoken->data_ptr +
(table_id * data_size)),
perf_table_id_offset);
if (perf_table_id_offset != 0) {
/* check is perf_table_id_offset is > 64k */
if (perf_table_id_offset & ~0xFFFF)
perf_table_ptr =
&g->bios.data[g->bios.expansion_rom_offset +
perf_table_id_offset];
else
perf_table_ptr =
&g->bios.data[perf_table_id_offset];
} else
gk20a_warn(g->dev, "PERF TABLE ID %d is NULL",
table_id);
} else
gk20a_warn(g->dev, "INVALID PERF TABLE ID - %d ", table_id);
return (void *)perf_table_ptr;
}
static void nvgpu_bios_parse_bit(struct gk20a *g, int offset)
{
struct bit bit;
struct bit_token bit_token;
int i;
gk20a_dbg_fn("");
memcpy(&bit, &g->bios.data[offset], sizeof(bit));
gk20a_dbg_info("BIT header: %04x %08x", bit.id, bit.signature);
gk20a_dbg_info("tokens: %d entries * %d bytes",
bit.token_entries, bit.token_size);
offset += bit.header_size;
for (i = 0; i < bit.token_entries; i++) {
memcpy(&bit_token, &g->bios.data[offset], sizeof(bit_token));
gk20a_dbg_info("BIT token id %d ptr %d size %d ver %d",
bit_token.token_id, bit_token.data_ptr,
bit_token.data_size, bit_token.data_version);
switch (bit_token.token_id) {
case TOKEN_ID_BIOSDATA:
nvgpu_bios_parse_biosdata(g, bit_token.data_ptr);
break;
case TOKEN_ID_NVINIT_PTRS:
nvgpu_bios_parse_nvinit_ptrs(g, bit_token.data_ptr);
break;
case TOKEN_ID_FALCON_DATA:
if (bit_token.data_version == 2)
nvgpu_bios_parse_falcon_data_v2(g,
bit_token.data_ptr);
break;
case TOKEN_ID_PERF_PTRS:
g->bios.perf_token =
(struct bit_token *)&g->bios.data[offset];
break;
case TOKEN_ID_CLOCK_PTRS:
g->bios.clock_token =
(struct bit_token *)&g->bios.data[offset];
break;
case TOKEN_ID_VIRT_PTRS:
g->bios.virt_token =
(struct bit_token *)&g->bios.data[offset];
break;
case TOKEN_ID_MEMORY_PTRS:
nvgpu_bios_parse_memory_ptrs(g, bit_token.data_ptr,
bit_token.data_version);
default:
break;
}
offset += bit.token_size;
}
gk20a_dbg_fn("done");
}
static u32 __nvgpu_bios_readbyte(struct gk20a *g, u32 offset)
{
return (u32) g->bios.data[offset];
}
u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset)
{
return (u8) __nvgpu_bios_readbyte(g, offset);
}
s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset)
{
u32 val;
val = __nvgpu_bios_readbyte(g, offset);
val = val & 0x80 ? (val | ~0xff) : val;
return (s8) val;
}
u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset)
{
u16 val;
val = __nvgpu_bios_readbyte(g, offset) |
(__nvgpu_bios_readbyte(g, offset+1) << 8);
return val;
}
u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset)
{
u32 val;
val = __nvgpu_bios_readbyte(g, offset) |
(__nvgpu_bios_readbyte(g, offset+1) << 8) |
(__nvgpu_bios_readbyte(g, offset+2) << 16) |
(__nvgpu_bios_readbyte(g, offset+3) << 24);
return val;
}
static void nvgpu_bios_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condition,
u32 reg, u32 stride, u32 count, u32 data_table_offset)
{
u8 i;
u32 data, strap, index;
if (*condition) {
strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf;
index = g->bios.mem_strap_xlat_tbl_ptr ?
nvgpu_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr +
strap) : strap;
for (i = 0; i < count; i++) {
data = nvgpu_bios_read_u32(g, data_table_offset + ((i *
g->bios.mem_strap_data_count + index) *
sizeof(u32)));
gk20a_writel(g, reg, data);
reg += stride;
}
}
}
static void gp106_init_condition(struct gk20a *g, bool *condition,
u32 condition_id)
{
struct condition_entry entry;
entry.cond_addr = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
sizeof(entry)*condition_id);
entry.cond_mask = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
sizeof(entry)*condition_id + 4);
entry.cond_compare = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
sizeof(entry)*condition_id + 8);
if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask)
!= entry.cond_compare) {
*condition = false;
}
}
int nvgpu_bios_execute_script(struct gk20a *g, u32 offset)
{
u8 opcode;
u32 ip;
u32 operand[8];
bool condition, end;
int status = 0;
ip = offset;
condition = true;
end = false;
while (!end) {
opcode = nvgpu_bios_read_u8(g, ip++);
switch (opcode) {
case INIT_XMEMSEL_ZM_NV_REG_ARRAY:
operand[0] = nvgpu_bios_read_u32(g, ip);
operand[1] = nvgpu_bios_read_u8(g, ip+4);
operand[2] = nvgpu_bios_read_u8(g, ip+5);
ip += 6;
nvgpu_bios_init_xmemsel_zm_nv_reg_array(g, &condition,
operand[0], operand[1], operand[2], ip);
ip += operand[2] * sizeof(u32) *
g->bios.mem_strap_data_count;
break;
case INIT_CONDITION:
operand[0] = nvgpu_bios_read_u8(g, ip);
ip++;
gp106_init_condition(g, &condition, operand[0]);
break;
case INIT_RESUME:
condition = true;
break;
case INIT_DONE:
end = true;
break;
default:
gk20a_err(dev_from_gk20a(g), "opcode: 0x%02x", opcode);
end = true;
status = -EINVAL;
break;
}
}
return status;
}

4
drivers/gpu/nvgpu/gk20a/gk20a.c
View File

@@ -918,8 +918,8 @@ int gk20a_pm_finalize_poweron(struct device *dev)
g->gpu_reset_done = true;
}
if (g->ops.bios.init)
err = g->ops.bios.init(g);
if (g->ops.bios_init)
err = g->ops.bios_init(g);
if (err)
goto done;

10
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -54,7 +54,6 @@ struct acr_desc;
#include "cde_gk20a.h"
#include "debug_gk20a.h"
#include "sched_gk20a.h"
#include "gm206/bios_gm206.h"
#ifdef CONFIG_ARCH_TEGRA_18x_SOC
#include "clk/clk.h"
#include "clk/clk_arb.h"
@@ -62,7 +61,6 @@ struct acr_desc;
#include "pmgr/pmgr.h"
#include "therm/thrm.h"
#endif
#include "gm206/bios_gm206.h"
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)
#define WRITE_ONCE(x, val) \
@@ -751,12 +749,8 @@ struct gpu_ops {
int (*chip_init_gpu_characteristics)(struct gk20a *g);
int (*read_ptimer)(struct gk20a *g, u64 *value);
struct {
int (*init)(struct gk20a *g);
void *(*get_perf_table_ptrs)(struct gk20a *g,
struct bit_token *ptoken, u8 table_id);
int (*execute_script)(struct gk20a *g, u32 offset);
} bios;
int (*bios_init)(struct gk20a *g);
#if defined(CONFIG_GK20A_CYCLE_STATS)
struct {
int (*enable_snapshot)(struct channel_gk20a *ch,

635
drivers/gpu/nvgpu/gm206/bios_gm206.c
View File

@@ -16,6 +16,8 @@
#include <linux/firmware.h>
#include <linux/pci.h>
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "gm20b/fifo_gm20b.h"
#include "fifo_gm206.h"
@@ -27,617 +29,12 @@
#include <nvgpu/hw/gm206/hw_mc_gm206.h>
#include <nvgpu/hw/gm206/hw_top_gm206.h>
#define BIT_HEADER_ID 0xb8ff
#define BIT_HEADER_SIGNATURE 0x00544942
#define BIOS_SIZE 0x40000
#define PCI_EXP_ROM_SIG 0xaa55
#define PCI_EXP_ROM_SIG_NV 0x4e56
#define ROM_FILE_PAYLOAD_OFFSET 0xa00
#define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */
#define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */
#define BIOS_OVERLAY_NAME "bios-%04x.rom"
#define BIOS_OVERLAY_NAME_FORMATTED "bios-xxxx.rom"
static u16 gm206_bios_rdu16(struct gk20a *g, int offset)
{
u16 val = (g->bios.data[offset+1] << 8) + g->bios.data[offset];
return val;
}
static u32 gm206_bios_rdu32(struct gk20a *g, int offset)
{
u32 val = (g->bios.data[offset+3] << 24) +
(g->bios.data[offset+2] << 16) +
(g->bios.data[offset+1] << 8) +
g->bios.data[offset];
return val;
}
struct bit {
u16 id;
u32 signature;
u16 bcd_version;
u8 header_size;
u8 token_size;
u8 token_entries;
u8 header_checksum;
} __packed;
#define TOKEN_ID_BIOSDATA 0x42
#define TOKEN_ID_NVINIT_PTRS 0x49
#define TOKEN_ID_FALCON_DATA 0x70
#define TOKEN_ID_PERF_PTRS 0x50
#define TOKEN_ID_CLOCK_PTRS 0x43
#define TOKEN_ID_VIRT_PTRS 0x56
#define TOKEN_ID_MEMORY_PTRS 0x4D
union memory_ptrs {
struct {
u8 rsvd0[2];
u8 mem_strap_data_count;
u16 mem_strap_xlat_tbl_ptr;
u8 rsvd1[8];
} v1 __packed;
struct {
u8 mem_strap_data_count;
u16 mem_strap_xlat_tbl_ptr;
u8 rsvd[14];
} v2 __packed;
};
struct biosdata {
u32 version;
u8 oem_version;
u8 checksum;
u16 int15callbackspost;
u16 int16callbackssystem;
u16 boardid;
u16 framecount;
u8 biosmoddate[8];
} __packed;
struct nvinit_ptrs {
u16 initscript_table_ptr;
u16 macro_index_table_ptr;
u16 macro_table_ptr;
u16 condition_table_ptr;
u16 io_condition_table_ptr;
u16 io_flag_condition_table_ptr;
u16 init_function_table_ptr;
u16 vbios_private_table_ptr;
u16 data_arrays_table_ptr;
u16 pcie_settings_script_ptr;
u16 devinit_tables_ptr;
u16 devinit_tables_size;
u16 bootscripts_ptr;
u16 bootscripts_size;
u16 nvlink_config_data_ptr;
} __packed;
struct falcon_data_v2 {
u32 falcon_ucode_table_ptr;
} __packed;
struct falcon_ucode_table_hdr_v1 {
u8 version;
u8 header_size;
u8 entry_size;
u8 entry_count;
u8 desc_version;
u8 desc_size;
} __packed;
struct falcon_ucode_table_entry_v1 {
u8 application_id;
u8 target_id;
u32 desc_ptr;
} __packed;
#define TARGET_ID_PMU 0x01
#define APPLICATION_ID_DEVINIT 0x04
#define APPLICATION_ID_PRE_OS 0x01
struct falcon_ucode_desc_v1 {
union {
u32 v_desc;
u32 stored_size;
} hdr_size;
u32 uncompressed_size;
u32 virtual_entry;
u32 interface_offset;
u32 imem_phys_base;
u32 imem_load_size;
u32 imem_virt_base;
u32 imem_sec_base;
u32 imem_sec_size;
u32 dmem_offset;
u32 dmem_phys_base;
u32 dmem_load_size;
} __packed;
struct application_interface_table_hdr_v1 {
u8 version;
u8 header_size;
u8 entry_size;
u8 entry_count;
} __packed;
struct application_interface_entry_v1 {
u32 id;
u32 dmem_offset;
} __packed;
#define APPINFO_ID_DEVINIT 0x01
struct devinit_engine_interface {
u32 field0;
u32 field1;
u32 tables_phys_base;
u32 tables_virt_base;
u32 script_phys_base;
u32 script_virt_base;
u32 script_virt_entry;
u16 script_size;
u8 memory_strap_count;
u8 reserved;
u32 memory_information_table_virt_base;
u32 empty_script_virt_base;
u32 cond_table_virt_base;
u32 io_cond_table_virt_base;
u32 data_arrays_table_virt_base;
u32 gpio_assignment_table_virt_base;
} __packed;
struct pci_exp_rom {
u16 sig;
u8 reserved[0x16];
u16 pci_data_struct_ptr;
u32 size_of_block;
} __packed;
struct pci_data_struct {
u32 sig;
u16 vendor_id;
u16 device_id;
u16 device_list_ptr;
u16 pci_data_struct_len;
u8 pci_data_struct_rev;
u8 class_code[3];
u16 image_len;
u16 vendor_rom_rev;
u8 code_type;
u8 last_image;
u16 max_runtime_image_len;
} __packed;
struct pci_ext_data_struct {
u32 sig;
u16 nv_pci_data_ext_rev;
u16 nv_pci_data_ext_len;
u16 sub_image_len;
u8 priv_last_image;
u8 flags;
} __packed;
static int gm206_bios_parse_rom(struct gk20a *g)
{
int offset = 0;
int last = 0;
while (!last) {
struct pci_exp_rom *pci_rom;
struct pci_data_struct *pci_data;
struct pci_ext_data_struct *pci_ext_data;
pci_rom = (struct pci_exp_rom *)&g->bios.data[offset];
gk20a_dbg_fn("pci rom sig %04x ptr %04x block %x",
pci_rom->sig, pci_rom->pci_data_struct_ptr,
pci_rom->size_of_block);
if (pci_rom->sig != PCI_EXP_ROM_SIG &&
pci_rom->sig != PCI_EXP_ROM_SIG_NV) {
gk20a_err(g->dev, "invalid VBIOS signature");
return -EINVAL;
}
pci_data =
(struct pci_data_struct *)
&g->bios.data[offset + pci_rom->pci_data_struct_ptr];
gk20a_dbg_fn("pci data sig %08x len %d image len %x type %x last %d max %08x",
pci_data->sig, pci_data->pci_data_struct_len,
pci_data->image_len, pci_data->code_type,
pci_data->last_image,
pci_data->max_runtime_image_len);
if (pci_data->code_type == 0x3) {
pci_ext_data = (struct pci_ext_data_struct *)
&g->bios.data[(offset +
pci_rom->pci_data_struct_ptr +
pci_data->pci_data_struct_len +
0xf)
& ~0xf];
gk20a_dbg_fn("pci ext data sig %08x rev %x len %x sub_image_len %x priv_last %d flags %x",
pci_ext_data->sig,
pci_ext_data->nv_pci_data_ext_rev,
pci_ext_data->nv_pci_data_ext_len,
pci_ext_data->sub_image_len,
pci_ext_data->priv_last_image,
pci_ext_data->flags);
gk20a_dbg_fn("expansion rom offset %x",
pci_data->image_len * 512);
g->bios.expansion_rom_offset =
pci_data->image_len * 512;
offset += pci_ext_data->sub_image_len * 512;
last = pci_ext_data->priv_last_image;
} else {
offset += pci_data->image_len * 512;
last = pci_data->last_image;
}
}
return 0;
}
static void gm206_bios_parse_biosdata(struct gk20a *g, int offset)
{
struct biosdata biosdata;
memcpy(&biosdata, &g->bios.data[offset], sizeof(biosdata));
gk20a_dbg_fn("bios version %x, oem version %x",
biosdata.version,
biosdata.oem_version);
g->gpu_characteristics.vbios_version = biosdata.version;
g->gpu_characteristics.vbios_oem_version = biosdata.oem_version;
}
static void gm206_bios_parse_nvinit_ptrs(struct gk20a *g, int offset)
{
struct nvinit_ptrs nvinit_ptrs;
memcpy(&nvinit_ptrs, &g->bios.data[offset], sizeof(nvinit_ptrs));
gk20a_dbg_fn("devinit ptr %x size %d", nvinit_ptrs.devinit_tables_ptr,
nvinit_ptrs.devinit_tables_size);
gk20a_dbg_fn("bootscripts ptr %x size %d", nvinit_ptrs.bootscripts_ptr,
nvinit_ptrs.bootscripts_size);
g->bios.devinit_tables = &g->bios.data[nvinit_ptrs.devinit_tables_ptr];
g->bios.devinit_tables_size = nvinit_ptrs.devinit_tables_size;
g->bios.bootscripts = &g->bios.data[nvinit_ptrs.bootscripts_ptr];
g->bios.bootscripts_size = nvinit_ptrs.bootscripts_size;
g->bios.condition_table_ptr = nvinit_ptrs.condition_table_ptr;
}
static void gm206_bios_parse_memory_ptrs(struct gk20a *g, int offset, u8 version)
{
union memory_ptrs memory_ptrs;
if ((version < 1) || (version > 2))
return;
memcpy(&memory_ptrs, &g->bios.data[offset], sizeof(memory_ptrs));
g->bios.mem_strap_data_count = (version > 1) ? memory_ptrs.v2.mem_strap_data_count :
memory_ptrs.v1.mem_strap_data_count;
g->bios.mem_strap_xlat_tbl_ptr = (version > 1) ? memory_ptrs.v2.mem_strap_xlat_tbl_ptr :
memory_ptrs.v1.mem_strap_xlat_tbl_ptr;
}
static void gm206_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset)
{
struct devinit_engine_interface interface;
memcpy(&interface, &g->bios.devinit.dmem[dmem_offset], sizeof(interface));
gk20a_dbg_fn("devinit tables phys %x script phys %x size %d",
interface.tables_phys_base,
interface.script_phys_base,
interface.script_size);
g->bios.devinit_tables_phys_base = interface.tables_phys_base;
g->bios.devinit_script_phys_base = interface.script_phys_base;
}
static int gm206_bios_parse_appinfo_table(struct gk20a *g, int offset)
{
struct application_interface_table_hdr_v1 hdr;
int i;
memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
gk20a_dbg_fn("appInfoHdr ver %d size %d entrySize %d entryCount %d",
hdr.version, hdr.header_size,
hdr.entry_size, hdr.entry_count);
if (hdr.version != 1)
return 0;
offset += sizeof(hdr);
for (i = 0; i < hdr.entry_count; i++) {
struct application_interface_entry_v1 entry;
memcpy(&entry, &g->bios.data[offset], sizeof(entry));
gk20a_dbg_fn("appInfo id %d dmem_offset %d",
entry.id, entry.dmem_offset);
if (entry.id == APPINFO_ID_DEVINIT)
gm206_bios_parse_devinit_appinfo(g, entry.dmem_offset);
offset += hdr.entry_size;
}
return 0;
}
static int gm206_bios_parse_falcon_ucode_desc(struct gk20a *g,
struct nvgpu_bios_ucode *ucode, int offset)
{
struct falcon_ucode_desc_v1 desc;
memcpy(&desc, &g->bios.data[offset], sizeof(desc));
gk20a_dbg_info("falcon ucode desc stored size %d uncompressed size %d",
desc.hdr_size.stored_size, desc.uncompressed_size);
gk20a_dbg_info("falcon ucode desc virtualEntry %x, interfaceOffset %x",
desc.virtual_entry, desc.interface_offset);
gk20a_dbg_info("falcon ucode IMEM phys base %x, load size %x virt base %x sec base %x sec size %x",
desc.imem_phys_base, desc.imem_load_size,
desc.imem_virt_base, desc.imem_sec_base,
desc.imem_sec_size);
gk20a_dbg_info("falcon ucode DMEM offset %d phys base %x, load size %d",
desc.dmem_offset, desc.dmem_phys_base,
desc.dmem_load_size);
if (desc.hdr_size.stored_size != desc.uncompressed_size) {
gk20a_dbg_info("does not match");
return -EINVAL;
}
ucode->code_entry_point = desc.virtual_entry;
ucode->bootloader = &g->bios.data[offset] + sizeof(desc);
ucode->bootloader_phys_base = desc.imem_phys_base;
ucode->bootloader_size = desc.imem_load_size - desc.imem_sec_size;
ucode->ucode = ucode->bootloader + ucode->bootloader_size;
ucode->phys_base = ucode->bootloader_phys_base + ucode->bootloader_size;
ucode->size = desc.imem_sec_size;
ucode->dmem = ucode->bootloader + desc.dmem_offset;
ucode->dmem_phys_base = desc.dmem_phys_base;
ucode->dmem_size = desc.dmem_load_size;
return gm206_bios_parse_appinfo_table(g,
offset + sizeof(desc) +
desc.dmem_offset + desc.interface_offset);
}
static int gm206_bios_parse_falcon_ucode_table(struct gk20a *g, int offset)
{
struct falcon_ucode_table_hdr_v1 hdr;
int i;
memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
gk20a_dbg_fn("falcon ucode table ver %d size %d entrySize %d entryCount %d descVer %d descSize %d",
hdr.version, hdr.header_size,
hdr.entry_size, hdr.entry_count,
hdr.desc_version, hdr.desc_size);
if (hdr.version != 1)
return -EINVAL;
offset += hdr.header_size;
for (i = 0; i < hdr.entry_count; i++) {
struct falcon_ucode_table_entry_v1 entry;
memcpy(&entry, &g->bios.data[offset], sizeof(entry));
gk20a_dbg_fn("falcon ucode table entry appid %x targetId %x descPtr %x",
entry.application_id, entry.target_id,
entry.desc_ptr);
if (entry.target_id == TARGET_ID_PMU &&
entry.application_id == APPLICATION_ID_DEVINIT) {
int err;
err = gm206_bios_parse_falcon_ucode_desc(g,
&g->bios.devinit, entry.desc_ptr);
if (err)
err = gm206_bios_parse_falcon_ucode_desc(g,
&g->bios.devinit,
entry.desc_ptr +
g->bios.expansion_rom_offset);
if (err)
gk20a_err(dev_from_gk20a(g),
"could not parse devinit ucode desc");
} else if (entry.target_id == TARGET_ID_PMU &&
entry.application_id == APPLICATION_ID_PRE_OS) {
int err;
err = gm206_bios_parse_falcon_ucode_desc(g,
&g->bios.preos, entry.desc_ptr);
if (err)
err = gm206_bios_parse_falcon_ucode_desc(g,
&g->bios.preos,
entry.desc_ptr +
g->bios.expansion_rom_offset);
if (err)
gk20a_err(dev_from_gk20a(g),
"could not parse preos ucode desc");
}
offset += hdr.entry_size;
}
return 0;
}
static void gm206_bios_parse_falcon_data_v2(struct gk20a *g, int offset)
{
struct falcon_data_v2 falcon_data;
int err;
memcpy(&falcon_data, &g->bios.data[offset], sizeof(falcon_data));
gk20a_dbg_fn("falcon ucode table ptr %x",
falcon_data.falcon_ucode_table_ptr);
err = gm206_bios_parse_falcon_ucode_table(g,
falcon_data.falcon_ucode_table_ptr);
if (err)
err = gm206_bios_parse_falcon_ucode_table(g,
falcon_data.falcon_ucode_table_ptr +
g->bios.expansion_rom_offset);
if (err)
gk20a_err(dev_from_gk20a(g),
"could not parse falcon ucode table");
}
static void *gm206_bios_get_perf_table_ptrs(struct gk20a *g,
struct bit_token *ptoken, u8 table_id)
{
u32 perf_table_id_offset = 0;
u8 *perf_table_ptr = NULL;
u8 data_size = 4;
if (ptoken != NULL) {
if (ptoken->token_id == TOKEN_ID_VIRT_PTRS) {
perf_table_id_offset = *((u16 *)&g->bios.data[
ptoken->data_ptr +
(table_id * PERF_PTRS_WIDTH_16)]);
data_size = PERF_PTRS_WIDTH_16;
} else {
perf_table_id_offset = *((u32 *)&g->bios.data[
ptoken->data_ptr +
(table_id * PERF_PTRS_WIDTH)]);
data_size = PERF_PTRS_WIDTH;
}
} else
return (void *)perf_table_ptr;
if (table_id < (ptoken->data_size/data_size)) {
gk20a_dbg_info("Perf_Tbl_ID-offset 0x%x Tbl_ID_Ptr-offset- 0x%x",
(ptoken->data_ptr +
(table_id * data_size)),
perf_table_id_offset);
if (perf_table_id_offset != 0) {
/* check is perf_table_id_offset is > 64k */
if (perf_table_id_offset & ~0xFFFF)
perf_table_ptr =
&g->bios.data[g->bios.expansion_rom_offset +
perf_table_id_offset];
else
perf_table_ptr =
&g->bios.data[perf_table_id_offset];
} else
gk20a_warn(g->dev, "PERF TABLE ID %d is NULL",
table_id);
} else
gk20a_warn(g->dev, "INVALID PERF TABLE ID - %d ", table_id);
return (void *)perf_table_ptr;
}
static void gm206_bios_parse_bit(struct gk20a *g, int offset)
{
struct bit bit;
struct bit_token bit_token;
int i;
gk20a_dbg_fn("");
memcpy(&bit, &g->bios.data[offset], sizeof(bit));
gk20a_dbg_info("BIT header: %04x %08x", bit.id, bit.signature);
gk20a_dbg_info("tokens: %d entries * %d bytes",
bit.token_entries, bit.token_size);
offset += bit.header_size;
for (i = 0; i < bit.token_entries; i++) {
memcpy(&bit_token, &g->bios.data[offset], sizeof(bit_token));
gk20a_dbg_info("BIT token id %d ptr %d size %d ver %d",
bit_token.token_id, bit_token.data_ptr,
bit_token.data_size, bit_token.data_version);
switch (bit_token.token_id) {
case TOKEN_ID_BIOSDATA:
gm206_bios_parse_biosdata(g, bit_token.data_ptr);
break;
case TOKEN_ID_NVINIT_PTRS:
gm206_bios_parse_nvinit_ptrs(g, bit_token.data_ptr);
break;
case TOKEN_ID_FALCON_DATA:
if (bit_token.data_version == 2)
gm206_bios_parse_falcon_data_v2(g,
bit_token.data_ptr);
break;
case TOKEN_ID_PERF_PTRS:
g->bios.perf_token =
(struct bit_token *)&g->bios.data[offset];
break;
case TOKEN_ID_CLOCK_PTRS:
g->bios.clock_token =
(struct bit_token *)&g->bios.data[offset];
break;
case TOKEN_ID_VIRT_PTRS:
g->bios.virt_token =
(struct bit_token *)&g->bios.data[offset];
break;
case TOKEN_ID_MEMORY_PTRS:
gm206_bios_parse_memory_ptrs(g, bit_token.data_ptr,
bit_token.data_version);
default:
break;
}
offset += bit.token_size;
}
gk20a_dbg_fn("done");
}
static u32 __gm206_bios_readbyte(struct gk20a *g, u32 offset)
{
return (u32) g->bios.data[offset];
}
u8 gm206_bios_read_u8(struct gk20a *g, u32 offset)
{
return (u8) __gm206_bios_readbyte(g, offset);
}
s8 gm206_bios_read_s8(struct gk20a *g, u32 offset)
{
u32 val;
val = __gm206_bios_readbyte(g, offset);
val = val & 0x80 ? (val | ~0xff) : val;
return (s8) val;
}
u16 gm206_bios_read_u16(struct gk20a *g, u32 offset)
{
u16 val;
val = __gm206_bios_readbyte(g, offset) |
(__gm206_bios_readbyte(g, offset+1) << 8);
return val;
}
u32 gm206_bios_read_u32(struct gk20a *g, u32 offset)
{
u32 val;
val = __gm206_bios_readbyte(g, offset) |
(__gm206_bios_readbyte(g, offset+1) << 8) |
(__gm206_bios_readbyte(g, offset+2) << 16) |
(__gm206_bios_readbyte(g, offset+3) << 24);
return val;
}
#define ROM_FILE_PAYLOAD_OFFSET 0xa00
#define BIOS_SIZE 0x40000
static void upload_code(struct gk20a *g, u32 dst,
u8 *src, u32 size, u8 port, bool sec)
@@ -831,14 +228,13 @@ static int gm206_bios_preos(struct gk20a *g)
return err;
}
static int gm206_bios_init(struct gk20a *g)
int gm206_bios_init(struct gk20a *g)
{
unsigned int i;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
struct dentry *d;
const struct firmware *bios_fw;
int err;
bool found = 0;
struct pci_dev *pdev = to_pci_dev(g->dev);
char rom_name[sizeof(BIOS_OVERLAY_NAME_FORMATTED)];
@@ -880,24 +276,10 @@ static int gm206_bios_init(struct gk20a *g)
g->ops.xve.enable_shadow_rom(g);
}
err = gm206_bios_parse_rom(g);
err = nvgpu_bios_parse_rom(g);
if (err)
return err;
gk20a_dbg_info("read bios");
for (i = 0; i < g->bios.size - 6; i++) {
if (gm206_bios_rdu16(g, i) == BIT_HEADER_ID &&
gm206_bios_rdu32(g, i+2) == BIT_HEADER_SIGNATURE) {
gm206_bios_parse_bit(g, i);
found = true;
}
}
if (!found) {
gk20a_err(g->dev, "no valid VBIOS found");
return -EINVAL;
}
if (g->gpu_characteristics.vbios_version <
platform->vbios_min_version) {
gk20a_err(g->dev, "unsupported VBIOS version %08x",
@@ -936,8 +318,7 @@ free_firmware:
return err;
}
void gm206_init_bios(struct gpu_ops *gops)
void gm206_init_bios_ops(struct gpu_ops *gops)
{
gops->bios.init = gm206_bios_init;
gops->bios.get_perf_table_ptrs = gm206_bios_get_perf_table_ptrs;
gops->bios_init = gm206_bios_init;
}

56
drivers/gpu/nvgpu/gm206/bios_gm206.h
View File

@@ -14,60 +14,10 @@
#ifndef NVGPU_BIOS_GM206_H
#define NVGPU_BIOS_GM206_H
#define PERF_PTRS_WIDTH 0x4
#define PERF_PTRS_WIDTH_16 0x2
#define NV_PCFG 0x88000
enum {
CLOCKS_TABLE = 2,
CLOCK_PROGRAMMING_TABLE,
FLL_TABLE,
VIN_TABLE,
FREQUENCY_CONTROLLER_TABLE
};
enum {
PERFORMANCE_TABLE = 0,
MEMORY_CLOCK_TABLE,
MEMORY_TWEAK_TABLE,
POWER_CONTROL_TABLE,
THERMAL_CONTROL_TABLE,
THERMAL_DEVICE_TABLE,
THERMAL_COOLERS_TABLE,
PERFORMANCE_SETTINGS_SCRIPT,
CONTINUOUS_VIRTUAL_BINNING_TABLE,
POWER_SENSORS_TABLE = 0xA,
POWER_CAPPING_TABLE = 0xB,
POWER_TOPOLOGY_TABLE = 0xF,
THERMAL_CHANNEL_TABLE = 0x12,
VOLTAGE_RAIL_TABLE = 26,
VOLTAGE_DEVICE_TABLE,
VOLTAGE_POLICY_TABLE,
LOWPOWER_TABLE,
LOWPOWER_GR_TABLE = 32,
LOWPOWER_MS_TABLE = 33,
};
enum {
VP_FIELD_TABLE = 0,
VP_FIELD_REGISTER,
VP_TRANSLATION_TABLE,
};
struct bit_token {
u8 token_id;
u8 data_version;
u16 data_size;
u16 data_ptr;
} __packed;
struct gk20a;
struct gpu_ops;
void gm206_init_bios(struct gpu_ops *gops);
u8 gm206_bios_read_u8(struct gk20a *g, u32 offset);
s8 gm206_bios_read_s8(struct gk20a *g, u32 offset);
u16 gm206_bios_read_u16(struct gk20a *g, u32 offset);
u32 gm206_bios_read_u32(struct gk20a *g, u32 offset);
int gm206_bios_init(struct gk20a *g);
void gm206_init_bios_ops(struct gpu_ops *gops);
#endif

2
drivers/gpu/nvgpu/gm206/hal_gm206.c
View File

@@ -198,7 +198,7 @@ int gm206_init_hal(struct gk20a *g)
#if defined(CONFIG_GK20A_CYCLE_STATS)
gk20a_init_css_ops(gops);
#endif
gm206_init_bios(gops);
gm206_init_bios_ops(gops);
switch(ver){
case GK20A_GPUID_GM206:
gops->name = "gm206";

123
drivers/gpu/nvgpu/gp106/bios_gp106.c
View File

@@ -1,123 +0,0 @@
/*
* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "gk20a/gk20a.h"
#include "gm206/bios_gm206.h"
#include "bios_gp106.h"
#include <nvgpu/hw/gp106/hw_gc6_gp106.h>
static void gp106_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condition,
u32 reg, u32 stride, u32 count, u32 data_table_offset)
{
u8 i;
u32 data, strap, index;
if (*condition) {
strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf;
index = g->bios.mem_strap_xlat_tbl_ptr ?
gm206_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr +
strap) : strap;
for (i = 0; i < count; i++) {
data = gm206_bios_read_u32(g, data_table_offset + ((i *
g->bios.mem_strap_data_count + index) *
sizeof(u32)));
gk20a_writel(g, reg, data);
reg += stride;
}
}
}
static void gp106_init_condition(struct gk20a *g, bool *condition,
u32 condition_id)
{
struct condition_entry entry;
entry.cond_addr = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
sizeof(entry)*condition_id);
entry.cond_mask = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
sizeof(entry)*condition_id + 4);
entry.cond_compare = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
sizeof(entry)*condition_id + 8);
if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask)
!= entry.cond_compare) {
*condition = false;
}
}
static int gp106_execute_script(struct gk20a *g, u32 offset)
{
u8 opcode;
u32 ip;
u32 operand[8];
bool condition, end;
int status = 0;
ip = offset;
condition = true;
end = false;
while (!end) {
opcode = gm206_bios_read_u8(g, ip++);
switch (opcode) {
case INIT_XMEMSEL_ZM_NV_REG_ARRAY:
operand[0] = gm206_bios_read_u32(g, ip);
operand[1] = gm206_bios_read_u8(g, ip+4);
operand[2] = gm206_bios_read_u8(g, ip+5);
ip += 6;
gp106_init_xmemsel_zm_nv_reg_array(g, &condition,
operand[0], operand[1], operand[2], ip);
ip += operand[2] * sizeof(u32) *
g->bios.mem_strap_data_count;
break;
case INIT_CONDITION:
operand[0] = gm206_bios_read_u8(g, ip);
ip++;
gp106_init_condition(g, &condition, operand[0]);
break;
case INIT_RESUME:
condition = true;
break;
case INIT_DONE:
end = true;
break;
default:
gk20a_err(dev_from_gk20a(g), "opcode: 0x%02x", opcode);
end = true;
status = -EINVAL;
break;
}
}
return status;
}
void gp106_init_bios(struct gpu_ops *gops)
{
gm206_init_bios(gops);
gops->bios.execute_script = gp106_execute_script;
}

31
drivers/gpu/nvgpu/gp106/bios_gp106.h
View File

@@ -1,31 +0,0 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef NVGPU_BIOS_GP106_H
#define NVGPU_BIOS_GP106_H
struct gpu_ops;
#define INIT_DONE 0x71
#define INIT_RESUME 0x72
#define INIT_CONDITION 0x75
#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f
struct condition_entry {
u32 cond_addr;
u32 cond_mask;
u32 cond_compare;
} __packed;
void gp106_init_bios(struct gpu_ops *gops);
#endif

4
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -39,7 +39,7 @@
#include "gp106/clk_gp106.h"
#include "gp106/clk_arb_gp106.h"
#include "gp106/bios_gp106.h"
#include "gm206/bios_gm206.h"
#include "gp106/therm_gp106.h"
#include "gp106/xve_gp106.h"
#include "gp106/fifo_gp106.h"
@@ -245,7 +245,7 @@ int gp106_init_hal(struct gk20a *g)
#if defined(CONFIG_GK20A_CYCLE_STATS)
gk20a_init_css_ops(gops);
#endif
gp106_init_bios(gops);
gm206_init_bios_ops(gops);
gp106_init_therm_ops(gops);
gp106_init_xve_ops(gops);

66
drivers/gpu/nvgpu/include/bios.h → drivers/gpu/nvgpu/include/nvgpu/bios.h
View File

@@ -1,7 +1,5 @@
/*
* vbios tables support
*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -13,10 +11,58 @@
* more details.
*/
#ifndef NVGPU_INCLUDE_BIOS_H
#define NVGPU_INCLUDE_BIOS_H
#ifndef NVGPU_BIOS_H
#define NVGPU_BIOS_H
#include "gk20a/gk20a.h"
#include <linux/types.h>
struct gk20a;
#define PERF_PTRS_WIDTH 0x4
#define PERF_PTRS_WIDTH_16 0x2
enum {
CLOCKS_TABLE = 2,
CLOCK_PROGRAMMING_TABLE,
FLL_TABLE,
VIN_TABLE,
FREQUENCY_CONTROLLER_TABLE
};
enum {
PERFORMANCE_TABLE = 0,
MEMORY_CLOCK_TABLE,
MEMORY_TWEAK_TABLE,
POWER_CONTROL_TABLE,
THERMAL_CONTROL_TABLE,
THERMAL_DEVICE_TABLE,
THERMAL_COOLERS_TABLE,
PERFORMANCE_SETTINGS_SCRIPT,
CONTINUOUS_VIRTUAL_BINNING_TABLE,
POWER_SENSORS_TABLE = 0xA,
POWER_CAPPING_TABLE = 0xB,
POWER_TOPOLOGY_TABLE = 0xF,
THERMAL_CHANNEL_TABLE = 0x12,
VOLTAGE_RAIL_TABLE = 26,
VOLTAGE_DEVICE_TABLE,
VOLTAGE_POLICY_TABLE,
LOWPOWER_TABLE,
LOWPOWER_GR_TABLE = 32,
LOWPOWER_MS_TABLE = 33,
};
enum {
VP_FIELD_TABLE = 0,
VP_FIELD_REGISTER,
VP_TRANSLATION_TABLE,
};
struct bit_token {
u8 token_id;
u8 data_version;
u16 data_size;
u16 data_ptr;
} __packed;
#define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT)
@@ -988,5 +1034,13 @@ struct nvgpu_bios_lpwr_gr_table_1x_entry {
#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4)
#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4
int nvgpu_bios_parse_rom(struct gk20a *g);
u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset);
s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset);
u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset);
u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset);
void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
struct bit_token *ptoken, u8 table_id);
int nvgpu_bios_execute_script(struct gk20a *g, u32 offset);
#endif

36
drivers/gpu/nvgpu/lpwr/lpwr.c
View File

@@ -11,12 +11,13 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#include "gp106/pmu_gp106.h"
#include "gm206/bios_gm206.h"
#include "pstate/pstate.h"
#include "include/bios.h"
#include "perf/perf.h"
#include "lpwr.h"
@@ -30,13 +31,10 @@ static int get_lpwr_idx_table(struct gk20a *g)
struct nvgpu_bios_lpwr_idx_table_1x_header header = { 0 };
struct nvgpu_bios_lpwr_idx_table_1x_entry entry = { 0 };
if (g->ops.bios.get_perf_table_ptrs) {
lpwr_idx_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g,
g->bios.perf_token, LOWPOWER_TABLE);
if (lpwr_idx_table_ptr == NULL)
return -EINVAL;
} else
return -EINVAL;
lpwr_idx_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, LOWPOWER_TABLE);
if (lpwr_idx_table_ptr == NULL)
return -EINVAL;
memcpy(&header, lpwr_idx_table_ptr,
sizeof(struct nvgpu_bios_lpwr_idx_table_1x_header));
@@ -75,13 +73,10 @@ static int get_lpwr_gr_table(struct gk20a *g)
struct nvgpu_bios_lpwr_gr_table_1x_header header = { 0 };
struct nvgpu_bios_lpwr_gr_table_1x_entry entry = { 0 };
if (g->ops.bios.get_perf_table_ptrs) {
lpwr_gr_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g,
g->bios.perf_token, LOWPOWER_GR_TABLE);
if (lpwr_gr_table_ptr == NULL)
return -EINVAL;
} else
return -EINVAL;
lpwr_gr_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, LOWPOWER_GR_TABLE);
if (lpwr_gr_table_ptr == NULL)
return -EINVAL;
memcpy(&header, lpwr_gr_table_ptr,
sizeof(struct nvgpu_bios_lpwr_gr_table_1x_header));
@@ -122,13 +117,10 @@ static int get_lpwr_ms_table(struct gk20a *g)
struct nvgpu_bios_lpwr_ms_table_1x_header header = { 0 };
struct nvgpu_bios_lpwr_ms_table_1x_entry entry = { 0 };
if (g->ops.bios.get_perf_table_ptrs) {
lpwr_ms_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g,
g->bios.perf_token, LOWPOWER_MS_TABLE);
if (lpwr_ms_table_ptr == NULL)
return -EINVAL;
} else
return -EINVAL;
lpwr_ms_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, LOWPOWER_MS_TABLE);
if (lpwr_ms_table_ptr == NULL)
return -EINVAL;
memcpy(&header, lpwr_ms_table_ptr,
sizeof(struct nvgpu_bios_lpwr_ms_table_1x_header));

2
drivers/gpu/nvgpu/lpwr/rppg.c
View File

@@ -16,8 +16,6 @@
#include "gp106/pmu_gp106.h"
#include "gm206/bios_gm206.h"
#include "pstate/pstate.h"
#include "include/bios.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
void *param, u32 handle, u32 status)

9
drivers/gpu/nvgpu/perf/vfe_equ.c
View File

@@ -11,13 +11,13 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "perf.h"
#include "vfe_equ.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e255.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
@@ -147,10 +147,7 @@ static u32 devinit_get_vfe_equ_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs)
return -EINVAL;
vfeequs_tbl_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
vfeequs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token,
CONTINUOUS_VIRTUAL_BINNING_TABLE);

18
drivers/gpu/nvgpu/perf/vfe_var.c
View File

@@ -11,13 +11,13 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "perf.h"
#include "vfe_var.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
@@ -179,17 +179,14 @@ u32 dev_init_get_vfield_info(struct gk20a *g,
u8 *psegmentcount = NULL;
u32 status = 0;
if (!g->ops.bios.get_perf_table_ptrs)
return -EINVAL;
vfieldregtableptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
vfieldregtableptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.virt_token, VP_FIELD_REGISTER);
if (vfieldregtableptr == NULL) {
status = -EINVAL;
goto done;
}
vfieldtableptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
vfieldtableptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.virt_token, VP_FIELD_TABLE);
if (vfieldtableptr == NULL) {
status = -EINVAL;
@@ -864,12 +861,7 @@ static u32 devinit_get_vfe_var_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs) {
status = -EINVAL;
goto done;
}
vfevars_tbl_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
vfevars_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token,
CONTINUOUS_VIRTUAL_BINNING_TABLE);
if (vfevars_tbl_ptr == NULL) {

1
drivers/gpu/nvgpu/pmgr/pmgrpmu.c
View File

@@ -13,7 +13,6 @@
#include "gk20a/gk20a.h"
#include "pwrdev.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>

8
drivers/gpu/nvgpu/pmgr/pwrdev.c
View File

@@ -11,9 +11,10 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "pwrdev.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
@@ -138,10 +139,7 @@ static u32 devinit_get_pwr_device_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs)
return -EINVAL;
pwr_device_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
pwr_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, POWER_SENSORS_TABLE);
if (pwr_device_table_ptr == NULL) {
status = -EINVAL;

8
drivers/gpu/nvgpu/pmgr/pwrmonitor.c
View File

@@ -11,9 +11,10 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "pwrdev.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
@@ -185,10 +186,7 @@ static u32 devinit_get_pwr_topology_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs)
return -EINVAL;
pwr_topology_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
pwr_topology_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, POWER_TOPOLOGY_TABLE);
if (pwr_topology_table_ptr == NULL) {
status = -EINVAL;

8
drivers/gpu/nvgpu/pmgr/pwrpolicy.c
View File

@@ -11,9 +11,10 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "pwrpolicy.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
@@ -521,10 +522,7 @@ static u32 devinit_get_pwr_policy_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs)
return -EINVAL;
ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, POWER_CAPPING_TABLE);
if (ptr == NULL) {
status = -EINVAL;

11
drivers/gpu/nvgpu/pstate/pstate.c
View File

@@ -13,11 +13,12 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "clk/clk.h"
#include "perf/perf.h"
#include "pmgr/pmgr.h"
#include "include/bios.h"
#include "pstate/pstate.h"
#include "therm/thrm.h"
@@ -342,11 +343,9 @@ static int pstate_sw_setup(struct gk20a *g)
goto done;
}
if (g->ops.bios.get_perf_table_ptrs) {
hdr = (struct vbios_pstate_header_5x *)
g->ops.bios.get_perf_table_ptrs(g,
g->bios.perf_token, PERFORMANCE_TABLE);
}
hdr = (struct vbios_pstate_header_5x *)
nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, PERFORMANCE_TABLE);
if (!hdr) {
gk20a_err(dev_from_gk20a(g),

8
drivers/gpu/nvgpu/therm/thrmchannel.c
View File

@@ -11,9 +11,10 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "thrmchannel.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
@@ -130,10 +131,7 @@ static u32 devinit_get_therm_channel_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs)
return -EINVAL;
therm_channel_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
therm_channel_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, THERMAL_CHANNEL_TABLE);
if (therm_channel_table_ptr == NULL) {
status = -EINVAL;

8
drivers/gpu/nvgpu/therm/thrmdev.c
View File

@@ -11,9 +11,10 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "thrmdev.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
@@ -80,10 +81,7 @@ static u32 devinit_get_therm_device_table(struct gk20a *g,
gk20a_dbg_info("");
if (!g->ops.bios.get_perf_table_ptrs)
return -EINVAL;
therm_device_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
therm_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, THERMAL_DEVICE_TABLE);
if (therm_device_table_ptr == NULL) {
status = -EINVAL;

1
drivers/gpu/nvgpu/therm/thrmpmu.c
View File

@@ -12,7 +12,6 @@
*/
#include "gk20a/gk20a.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "thrmpmu.h"

15
drivers/gpu/nvgpu/volt/volt_dev.c
View File

@@ -14,17 +14,17 @@
#include <linux/sort.h>
#include "gk20a/gk20a.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
#include "include/bios.h"
#include "volt.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include <nvgpu/bios.h>
#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0
#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1
@@ -363,14 +363,9 @@ static u32 volt_get_volt_devices_table(struct gk20a *g,
u8 entry_idx;
u8 *entry_offset;
if (g->ops.bios.get_perf_table_ptrs) {
volt_device_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
g->bios.perf_token, VOLTAGE_DEVICE_TABLE);
if (volt_device_table_ptr == NULL) {
status = -EINVAL;
goto done;
}
} else {
volt_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, VOLTAGE_DEVICE_TABLE);
if (volt_device_table_ptr == NULL) {
status = -EINVAL;
goto done;
}

2
drivers/gpu/nvgpu/volt/volt_pmu.c
View File

@@ -12,7 +12,6 @@
*/
#include "gk20a/gk20a.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
@@ -20,7 +19,6 @@
#include "ctrl/ctrlperf.h"
#include "gk20a/pmu_gk20a.h"
#include "include/bios.h"
#include "volt.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>

18
drivers/gpu/nvgpu/volt/volt_policy.c
View File

@@ -11,16 +11,15 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "include/bios.h"
#include "volt.h"
static u32 volt_policy_pmu_data_init_super(struct gk20a *g,
@@ -170,15 +169,10 @@ static u32 volt_get_volt_policy_table(struct gk20a *g,
struct voltage_policy_split_rail split_rail;
} policy_type_data;
if (g->ops.bios.get_perf_table_ptrs) {
voltage_policy_table_ptr =
(u8 *)g->ops.bios.get_perf_table_ptrs(g,
g->bios.perf_token, VOLTAGE_POLICY_TABLE);
if (voltage_policy_table_ptr == NULL) {
status = -EINVAL;
goto done;
}
} else {
voltage_policy_table_ptr =
(u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, VOLTAGE_POLICY_TABLE);
if (voltage_policy_table_ptr == NULL) {
status = -EINVAL;
goto done;
}

16
drivers/gpu/nvgpu/volt/volt_rail.c
View File

@@ -11,16 +11,15 @@
* more details.
*/
#include <nvgpu/bios.h>
#include "gk20a/gk20a.h"
#include "include/bios.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "include/bios.h"
#include "volt.h"
u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
@@ -241,14 +240,9 @@ static u32 volt_get_volt_rail_table(struct gk20a *g,
struct voltage_rail volt_rail;
} rail_type_data;
if (g->ops.bios.get_perf_table_ptrs) {
volt_rail_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
g->bios.perf_token, VOLTAGE_RAIL_TABLE);
if (volt_rail_table_ptr == NULL) {
status = -EINVAL;
goto done;
}
} else {
volt_rail_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token, VOLTAGE_RAIL_TABLE);
if (volt_rail_table_ptr == NULL) {
status = -EINVAL;
goto done;
}