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gpu: nvgpu: avoid including ram header in gr falcon

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Avoid including hw_ram_gm20b.h in gr_falcon_gm20b.c.
Instead use ops for getting ramin base shift.

JIRA NVGPU-3211

Change-Id: I679d78064600d42038d4f01a9d5c14a64998dcf0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103714
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-04-23 14:28:08 -07:00
committed by mobile promotions
parent 9a26daf109
commit 5a9d4932bc
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c
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@@ -32,7 +32,6 @@
#include "common/gr/gr_priv.h"
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
#define GR_FECS_POLL_INTERVAL 5U /* usec */
@@ -951,7 +950,8 @@ u32 gm20b_gr_falcon_get_fecs_current_ctx_data(struct gk20a *g,
struct nvgpu_mem *inst_block)
{
u64 ptr = nvgpu_inst_block_addr(g, inst_block) >>
ram_in_base_shift_v();
g->ops.ramin.base_shift();
u32 aperture = nvgpu_aperture_mask(g, inst_block,
gr_fecs_current_ctx_target_sys_mem_ncoh_f(),
gr_fecs_current_ctx_target_sys_mem_coh_f(),