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gpu: nvgpu: ACR code refactor

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-Created struct nvgpu_acr to hold acr module related member
 within single struct which are currently spread across multiple structs
 like nvgpu_pmu, pmu_ops & gk20a.
-Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members
-Created struct hs_acr to hold ACR ucode specific members like bootloader data
 using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run.
-Created acr ops under struct nvgpu_acr	to perform ACR specific operation,
 currently ACR ops were part PMU which caused to have always dependence
 on PMU even though ACR was not executing on PMU.
-Added acr_remove_support ops which will be called as part of
 gk20a_remove_support() method, earlier acr cleanup was part of
 pmu remove_support method.
-Created define for ACR types,
-Ops acr_sw_init() function helps to set ACR properties
 statically for chip currently in execution & assign ops to point to
 needed functions as per chip.
-Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr
 function to alloc blob space.
-Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde
 based on interfaces used to bootstrap ACR ucode.
-Created function gm20b_bootstrap_hs_acr() function which is now common
 HAL for all chips to bootstrap ACR, earlier had 3 different function for
 gm20b/gp10b, gv11b & for all dgpu based on interface needed.
-Removed duplicate code for falcon engine wherever common falcon code can be used.
-Removed ACR code dependent on PMU & made changes to use from nvgpu_acr.

JIRA NVGPU-1148

Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813231
GVS: Gerrit_Virtual_Submit
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2018-09-06 20:44:27 +05:30
committed by mobile promotions
parent 7465926ccd
commit 5d30a5cda3
22 changed files with 862 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/mm/mm.c
View File

@@ -442,9 +442,10 @@ static int nvgpu_init_mm_setup_sw(struct gk20a *g)
* this requires fixed allocations in vidmem which must be
* allocated before all other buffers
*/
if (g->ops.pmu.alloc_blob_space != NULL &&
if (g->acr.alloc_blob_space != NULL &&
!nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY)) {
err = g->ops.pmu.alloc_blob_space(g, 0, &g->acr.ucode_blob);
err = g->acr.alloc_blob_space(g, 0, &g->acr.ucode_blob);
if (err) {
return err;
}

14
drivers/gpu/nvgpu/gk20a/gk20a.c
View File

@@ -165,6 +165,11 @@ int gk20a_finalize_poweron(struct gk20a *g)
goto done;
}
if (g->ops.acr.acr_sw_init != NULL &&
nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
g->ops.acr.acr_sw_init(g, &g->acr);
}
if (g->ops.bios.init) {
err = g->ops.bios.init(g);
}
@@ -273,6 +278,15 @@ int gk20a_finalize_poweron(struct gk20a *g)
}
}
if (g->acr.bootstrap_hs_acr != NULL &&
nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
err = g->acr.bootstrap_hs_acr(g, &g->acr, &g->acr.acr);
if (err != 0) {
nvgpu_err(g, "ACR bootstrap failed");
goto done;
}
}
if (g->ops.pmu.is_pmu_supported(g)) {
err = nvgpu_init_pmu_support(g);
if (err) {

374
drivers/gpu/nvgpu/gm20b/acr_gm20b.c
View File

@@ -38,8 +38,10 @@
#include <nvgpu/gk20a.h>
#include "mm_gm20b.h"
#include "pmu_gm20b.h"
#include "acr_gm20b.h"
#include <nvgpu/hw/gm20b/hw_falcon_gm20b.h>
#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
typedef int (*get_ucode_details)(struct gk20a *g, struct flcn_ucode_img *udata);
@@ -358,7 +360,7 @@ int prepare_ucode_blob(struct gk20a *g)
g->ops.fb.vpr_info_fetch(g);
gr_gk20a_init_ctxsw_ucode(g);
g->ops.pmu.get_wpr(g, &wpr_inf);
g->acr.get_wpr_info(g, &wpr_inf);
nvgpu_pmu_dbg(g, "wpr carveout base:%llx\n", wpr_inf.wpr_base);
nvgpu_pmu_dbg(g, "wpr carveout size :%llx\n", wpr_inf.size);
@@ -377,7 +379,7 @@ int prepare_ucode_blob(struct gk20a *g)
}
/*Alloc memory to hold ucode blob contents*/
err = g->ops.pmu.alloc_blob_space(g, plsfm->wpr_size
err = g->acr.alloc_blob_space(g, plsfm->wpr_size
, &g->acr.ucode_blob);
if (err) {
goto free_sgt;
@@ -450,7 +452,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g,
/*0th index is always PMU which is already handled in earlier
if condition*/
for (i = 1; i < (MAX_SUPPORTED_LSFM); i++) {
for (i = 1; i < g->acr.max_supported_lsfm; i++) {
memset(&ucode_img, 0, sizeof(ucode_img));
if (pmu_acr_supp_ucode_list[i](g, &ucode_img) == 0) {
if (ucode_img.lsf_desc != NULL) {
@@ -520,7 +522,7 @@ int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
* physical addresses of each respective segment.
*/
addr_base = p_lsfm->lsb_header.ucode_off;
g->ops.pmu.get_wpr(g, &wpr_inf);
g->acr.get_wpr_info(g, &wpr_inf);
addr_base += wpr_inf.wpr_base;
nvgpu_pmu_dbg(g, "pmu loader cfg u32 addrbase %x\n", (u32)addr_base);
/*From linux*/
@@ -596,7 +598,7 @@ int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
* physical addresses of each respective segment.
*/
addr_base = p_lsfm->lsb_header.ucode_off;
g->ops.pmu.get_wpr(g, &wpr_inf);
g->acr.get_wpr_info(g, &wpr_inf);
addr_base += wpr_inf.wpr_base;
nvgpu_pmu_dbg(g, "gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base,
@@ -874,7 +876,7 @@ static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr *plsfm,
/* Fill in static WPR header info*/
pnode->wpr_header.falcon_id = falcon_id;
pnode->wpr_header.bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
pnode->wpr_header.bootstrap_owner = g->acr.bootstrap_owner;
pnode->wpr_header.status = LSF_IMAGE_STATUS_COPY;
pnode->wpr_header.lazy_bootstrap =
@@ -1112,3 +1114,363 @@ void gm20b_update_lspmu_cmdline_args(struct gk20a *g)
(u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
}
static int nvgpu_gm20b_acr_wait_for_completion(struct gk20a *g,
struct nvgpu_falcon *flcn, unsigned int timeout)
{
u32 base_addr = flcn->flcn_base;
int completion = 0;
u32 data = 0;
nvgpu_log_fn(g, " ");
completion = nvgpu_flcn_wait_for_halt(flcn, timeout);
if (completion != 0U) {
nvgpu_err(g, "flcn-%d: ACR boot timed out", flcn->flcn_id);
goto exit;
}
nvgpu_pmu_dbg(g, "flcn-%d: ACR capabilities %x\n", flcn->flcn_id,
nvgpu_flcn_mailbox_read(flcn, FALCON_MAILBOX_1));
data = nvgpu_flcn_mailbox_read(flcn, FALCON_MAILBOX_0);
if (data != 0U) {
nvgpu_err(g, "flcn-%d: ACR boot failed, err %x", flcn->flcn_id,
data);
completion = -EAGAIN;
goto exit;
}
nvgpu_pmu_dbg(g, "flcn-%d: sctl reg %x", flcn->flcn_id,
gk20a_readl(g, base_addr + falcon_falcon_sctl_r()));
nvgpu_pmu_dbg(g, "flcn-%d: cpuctl reg %x", flcn->flcn_id,
gk20a_readl(g, base_addr + falcon_falcon_cpuctl_r()));
exit:
return completion;
}
static int gm20b_acr_hs_bl_exec(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, bool b_wait_for_halt)
{
struct nvgpu_firmware *hs_bl_fw = acr_desc->acr_hs_bl.hs_bl_fw;
struct hsflcn_bl_desc *hs_bl_desc;
struct nvgpu_falcon_bl_info bl_info;
struct hs_flcn_bl *hs_bl = &acr_desc->acr_hs_bl;
struct mm_gk20a *mm = &g->mm;
struct vm_gk20a *vm = mm->pmu.vm;
u32 *hs_bl_code = NULL;
int err = 0;
u32 bl_sz;
nvgpu_pmu_dbg(g, "Executing ACR HS Bootloader %s on Falcon-ID - %d",
hs_bl->bl_fw_name, acr_desc->acr_flcn->flcn_id);
if (hs_bl_fw == NULL) {
hs_bl_fw = nvgpu_request_firmware(g, hs_bl->bl_fw_name, 0U);
if (hs_bl_fw == NULL) {
nvgpu_err(g, "ACR HS BL ucode load fail");
return -ENOENT;
}
hs_bl->hs_bl_fw = hs_bl_fw;
hs_bl->hs_bl_bin_hdr = (struct bin_hdr *)hs_bl_fw->data;
hs_bl->hs_bl_desc = (struct hsflcn_bl_desc *)(hs_bl_fw->data +
hs_bl->hs_bl_bin_hdr->header_offset);
hs_bl_desc = hs_bl->hs_bl_desc;
hs_bl_code = (u32 *)(hs_bl_fw->data +
hs_bl->hs_bl_bin_hdr->data_offset);
bl_sz = ALIGN(hs_bl_desc->bl_img_hdr.bl_code_size, 256U);
hs_bl->hs_bl_ucode.size = bl_sz;
err = nvgpu_dma_alloc_sys(g, bl_sz, &hs_bl->hs_bl_ucode);
if (err) {
nvgpu_err(g, "ACR HS BL failed to allocate memory");
goto err_done;
}
hs_bl->hs_bl_ucode.gpu_va = nvgpu_gmmu_map(vm,
&hs_bl->hs_bl_ucode,
bl_sz,
0U, /* flags */
gk20a_mem_flag_read_only, false,
hs_bl->hs_bl_ucode.aperture);
if (hs_bl->hs_bl_ucode.gpu_va == 0U) {
nvgpu_err(g, "ACR HS BL failed to map ucode memory!!");
goto err_free_ucode;
}
nvgpu_mem_wr_n(g, &hs_bl->hs_bl_ucode, 0U, hs_bl_code, bl_sz);
nvgpu_pmu_dbg(g, "Copied BL ucode to bl_cpuva");
}
/* Fill HS BL info */
bl_info.bl_src = hs_bl->hs_bl_ucode.cpu_va;
bl_info.bl_desc = acr_desc->ptr_bl_dmem_desc;
bl_info.bl_desc_size = acr_desc->bl_dmem_desc_size;
bl_info.bl_size = hs_bl->hs_bl_ucode.size;
bl_info.bl_start_tag = hs_bl->hs_bl_desc->bl_start_tag;
/*
* 1. Dose falcon reset
* 2. setup falcon apertures
* 3. bootstrap falcon
*/
acr_desc->acr_flcn_setup_hw_and_bl_bootstrap(g, acr_desc, &bl_info);
if (b_wait_for_halt) {
/* wait for ACR halt*/
err = nvgpu_gm20b_acr_wait_for_completion(g, acr_desc->acr_flcn,
ACR_COMPLETION_TIMEOUT_MS);
if (err != 0U) {
goto err_unmap_bl;
}
}
return 0U;
err_unmap_bl:
nvgpu_gmmu_unmap(vm, &hs_bl->hs_bl_ucode, hs_bl->hs_bl_ucode.gpu_va);
err_free_ucode:
nvgpu_dma_free(g, &hs_bl->hs_bl_ucode);
err_done:
nvgpu_release_firmware(g, hs_bl_fw);
return err;
}
int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery)
{
struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
struct acr_fw_header *acr_fw_hdr = NULL;
struct bin_hdr *acr_fw_bin_hdr = NULL;
struct flcn_acr_desc *acr_dmem_desc;
u32 *acr_ucode_header = NULL;
u32 *acr_ucode_data = NULL;
nvgpu_log_fn(g, " ");
if (is_recovery) {
acr_desc->acr_dmem_desc->nonwpr_ucode_blob_size = 0U;
} else {
acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
acr_fw_hdr = (struct acr_fw_header *)
(acr_fw->data + acr_fw_bin_hdr->header_offset);
acr_ucode_data = (u32 *)(acr_fw->data +
acr_fw_bin_hdr->data_offset);
acr_ucode_header = (u32 *)(acr_fw->data +
acr_fw_hdr->hdr_offset);
/* During recovery need to update blob size as 0x0*/
acr_desc->acr_dmem_desc = (struct flcn_acr_desc *)((u8 *)(
acr_desc->acr_ucode.cpu_va) + acr_ucode_header[2U]);
/* Patch WPR info to ucode */
acr_dmem_desc = (struct flcn_acr_desc *)
&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
acr_dmem_desc->nonwpr_ucode_blob_start =
nvgpu_mem_get_addr(g, &g->acr.ucode_blob);
acr_dmem_desc->nonwpr_ucode_blob_size =
g->acr.ucode_blob.size;
acr_dmem_desc->regions.no_regions = 1U;
acr_dmem_desc->wpr_offset = 0U;
}
return 0;
}
int gm20b_acr_fill_bl_dmem_desc(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header)
{
struct flcn_bl_dmem_desc *bl_dmem_desc = &acr_desc->bl_dmem_desc;
nvgpu_log_fn(g, " ");
memset(bl_dmem_desc, 0U, sizeof(struct flcn_bl_dmem_desc));
bl_dmem_desc->signature[0] = 0U;
bl_dmem_desc->signature[1] = 0U;
bl_dmem_desc->signature[2] = 0U;
bl_dmem_desc->signature[3] = 0U;
bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
bl_dmem_desc->code_dma_base =
(unsigned int)(((u64)acr_desc->acr_ucode.gpu_va >> 8U));
bl_dmem_desc->code_dma_base1 = 0x0U;
bl_dmem_desc->non_sec_code_off = acr_ucode_header[0U];
bl_dmem_desc->non_sec_code_size = acr_ucode_header[1U];
bl_dmem_desc->sec_code_off = acr_ucode_header[5U];
bl_dmem_desc->sec_code_size = acr_ucode_header[6U];
bl_dmem_desc->code_entry_point = 0U; /* Start at 0th offset */
bl_dmem_desc->data_dma_base =
bl_dmem_desc->code_dma_base +
((acr_ucode_header[2U]) >> 8U);
bl_dmem_desc->data_dma_base1 = 0x0U;
bl_dmem_desc->data_size = acr_ucode_header[3U];
return 0;
}
/*
* Loads ACR bin to SYSMEM/FB and bootstraps ACR with bootloader code
* start and end are addresses of ucode blob in non-WPR region
*/
int gm20b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc)
{
struct mm_gk20a *mm = &g->mm;
struct vm_gk20a *vm = mm->pmu.vm;
struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
struct bin_hdr *acr_fw_bin_hdr = NULL;
struct acr_fw_header *acr_fw_hdr = NULL;
struct nvgpu_mem *acr_ucode_mem = &acr_desc->acr_ucode;
u32 img_size_in_bytes = 0;
u32 *acr_ucode_data;
u32 *acr_ucode_header;
u32 status = 0U;
nvgpu_pmu_dbg(g, "ACR TYPE %x ", acr_desc->acr_type);
if (acr_fw != NULL) {
acr->patch_wpr_info_to_ucode(g, acr, acr_desc, true);
} else {
acr_fw = nvgpu_request_firmware(g, acr_desc->acr_fw_name,
NVGPU_REQUEST_FIRMWARE_NO_SOC);
if (acr_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr_desc->acr_fw_name, g->name);
return -ENOENT;
}
acr_desc->acr_fw = acr_fw;
acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
acr_fw_hdr = (struct acr_fw_header *)
(acr_fw->data + acr_fw_bin_hdr->header_offset);
acr_ucode_header = (u32 *)(acr_fw->data +
acr_fw_hdr->hdr_offset);
acr_ucode_data = (u32 *)(acr_fw->data +
acr_fw_bin_hdr->data_offset);
img_size_in_bytes = ALIGN((acr_fw_bin_hdr->data_size), 256U);
/* Lets patch the signatures first.. */
if (acr_ucode_patch_sig(g, acr_ucode_data,
(u32 *)(acr_fw->data + acr_fw_hdr->sig_prod_offset),
(u32 *)(acr_fw->data + acr_fw_hdr->sig_dbg_offset),
(u32 *)(acr_fw->data + acr_fw_hdr->patch_loc),
(u32 *)(acr_fw->data + acr_fw_hdr->patch_sig)) < 0) {
nvgpu_err(g, "patch signatures fail");
status = -1;
goto err_release_acr_fw;
}
status = nvgpu_dma_alloc_map_sys(vm, img_size_in_bytes,
acr_ucode_mem);
if (status != 0U) {
status = -ENOMEM;
goto err_release_acr_fw;
}
acr->patch_wpr_info_to_ucode(g, acr, acr_desc, false);
nvgpu_mem_wr_n(g, acr_ucode_mem, 0U, acr_ucode_data,
img_size_in_bytes);
/*
* In order to execute this binary, we will be using
* a bootloader which will load this image into
* FALCON IMEM/DMEM.
* Fill up the bootloader descriptor to use..
* TODO: Use standard descriptor which the generic bootloader is
* checked in.
*/
acr->acr_fill_bl_dmem_desc(g, acr, acr_desc, acr_ucode_header);
}
status = gm20b_acr_hs_bl_exec(g, acr, acr_desc, true);
if (status != 0U) {
goto err_free_ucode_map;
}
return 0;
err_free_ucode_map:
nvgpu_dma_unmap_free(vm, acr_ucode_mem);
err_release_acr_fw:
nvgpu_release_firmware(g, acr_fw);
acr_fw = NULL;
return status;
}
void gm20b_remove_acr_support(struct nvgpu_acr *acr)
{
struct gk20a *g = acr->g;
struct mm_gk20a *mm = &g->mm;
struct vm_gk20a *vm = mm->pmu.vm;
if (acr->acr.acr_fw != NULL) {
nvgpu_release_firmware(g, acr->acr.acr_fw);
}
if (acr->acr.acr_hs_bl.hs_bl_fw != NULL) {
nvgpu_release_firmware(g, acr->acr.acr_hs_bl.hs_bl_fw);
}
nvgpu_dma_unmap_free(vm, &acr->acr.acr_ucode);
nvgpu_dma_unmap_free(vm, &acr->acr.acr_hs_bl.hs_bl_ucode);
}
static void gm20b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
{
struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl;
nvgpu_log_fn(g, " ");
/* ACR HS bootloader ucode name */
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
/* ACR HS ucode type & f/w name*/
hs_acr->acr_type = ACR_DEFAULT;
hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE;
/* bootlader interface used by ACR HS bootloader*/
hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc;
hs_acr->bl_dmem_desc_size = sizeof(struct flcn_bl_dmem_desc);
/* set on which falcon ACR need to execute*/
hs_acr->acr_flcn = &g->pmu_flcn;
hs_acr->acr_flcn_setup_hw_and_bl_bootstrap =
gm20b_pmu_setup_hw_and_bl_bootstrap;
}
void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
{
nvgpu_log_fn(g, " ");
acr->g = g;
acr->bootstrap_owner = LSF_FALCON_ID_PMU;
acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
gm20b_acr_default_sw_init(g, &acr->acr);
acr->get_wpr_info = gm20b_wpr_info;
acr->alloc_blob_space = gm20b_alloc_blob_space;
acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr;
acr->patch_wpr_info_to_ucode =
gm20b_acr_patch_wpr_info_to_ucode;
acr->acr_fill_bl_dmem_desc =
gm20b_acr_fill_bl_dmem_desc;
acr->remove_support = gm20b_remove_acr_support;
}

17
drivers/gpu/nvgpu/gm20b/acr_gm20b.h
View File

@@ -37,21 +37,32 @@ bool gm20b_is_pmu_supported(struct gk20a *g);
int prepare_ucode_blob(struct gk20a *g);
bool gm20b_is_lazy_bootstrap(u32 falcon_id);
bool gm20b_is_priv_load(u32 falcon_id);
void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
int gm20b_alloc_blob_space(struct gk20a *g, size_t size, struct nvgpu_mem *mem);
int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
void *lsfm, u32 *p_bl_gen_desc_size);
int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
void gm20b_update_lspmu_cmdline_args(struct gk20a *g);
void gm20b_setup_apertures(struct gk20a *g);
int gm20b_pmu_setup_sw(struct gk20a *g);
int gm20b_init_nspmu_setup_hw1(struct gk20a *g);
int acr_ucode_patch_sig(struct gk20a *g,
unsigned int *p_img,
unsigned int *p_prod_sig,
unsigned int *p_dbg_sig,
unsigned int *p_patch_loc,
unsigned int *p_patch_ind);
int gm20b_alloc_blob_space(struct gk20a *g,
size_t size, struct nvgpu_mem *mem);
void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery);
int gm20b_acr_fill_bl_dmem_desc(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header);
int gm20b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc);
void gm20b_remove_acr_support(struct nvgpu_acr *acr);
void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
#endif /*NVGPU_GM20B_ACR_GM20B_H*/

6
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -656,6 +656,9 @@ static const struct gpu_ops gm20b_ops = {
.read_vin_cal_slope_intercept_fuse = NULL,
.read_vin_cal_gain_offset_fuse = NULL,
},
.acr = {
.acr_sw_init = nvgpu_gm20b_acr_sw_init,
},
.chip_init_gpu_characteristics = gk20a_init_gpu_characteristics,
.get_litter_value = gm20b_get_litter_value,
};
@@ -703,6 +706,8 @@ int gm20b_init_hal(struct gk20a *g)
gops->fuse = gm20b_ops.fuse;
gops->acr = gm20b_ops.acr;
/* Lone functions */
gops->chip_init_gpu_characteristics =
gm20b_ops.chip_init_gpu_characteristics;
@@ -750,7 +755,6 @@ int gm20b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
g->pmu_lsf_pmu_wpr_init_done = 0;
g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
g->name = "gm20b";

60
drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
View File

@@ -277,3 +277,63 @@ bool gm20b_pmu_is_debug_mode_en(struct gk20a *g)
u32 ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r());
return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U;
}
static int gm20b_bl_bootstrap(struct gk20a *g,
struct nvgpu_falcon_bl_info *bl_info)
{
struct mm_gk20a *mm = &g->mm;
nvgpu_log_fn(g, " ");
gk20a_writel(g, pwr_falcon_itfen_r(),
gk20a_readl(g, pwr_falcon_itfen_r()) |
pwr_falcon_itfen_ctxen_enable_f());
gk20a_writel(g, pwr_pmu_new_instblk_r(),
pwr_pmu_new_instblk_ptr_f(
nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) |
pwr_pmu_new_instblk_valid_f(1U) |
(nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) ?
pwr_pmu_new_instblk_target_sys_coh_f() :
pwr_pmu_new_instblk_target_sys_ncoh_f())) ;
nvgpu_flcn_bl_bootstrap(&g->pmu_flcn, bl_info);
return 0;
}
int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g,
struct hs_acr *acr_desc,
struct nvgpu_falcon_bl_info *bl_info)
{
struct nvgpu_pmu *pmu = &g->pmu;
int err;
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&pmu->isr_mutex);
/*
* disable irqs for hs falcon booting
* as we will poll for halt
*/
g->ops.pmu.pmu_enable_irq(pmu, false);
pmu->isr_enabled = false;
err = nvgpu_flcn_reset(acr_desc->acr_flcn);
if (err != 0) {
nvgpu_mutex_release(&pmu->isr_mutex);
goto exit;
}
nvgpu_mutex_release(&pmu->isr_mutex);
if (g->ops.pmu.setup_apertures) {
g->ops.pmu.setup_apertures(g);
}
/*Clearing mailbox register used to reflect capabilities*/
gk20a_writel(g, pwr_falcon_mailbox1_r(), 0);
err = gm20b_bl_bootstrap(g, bl_info);
exit:
return err;
}

4
drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
View File

@@ -34,5 +34,7 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags);
int gm20b_pmu_init_acr(struct gk20a *g);
void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr);
bool gm20b_pmu_is_debug_mode_en(struct gk20a *g);
int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g,
struct hs_acr *acr_desc,
struct nvgpu_falcon_bl_info *bl_info);
#endif /*NVGPU_GM20B_PMU_GM20B_H*/

133
drivers/gpu/nvgpu/gp106/acr_gp106.c
View File

@@ -93,7 +93,7 @@ int gp106_alloc_blob_space(struct gk20a *g,
return 0;
}
g->ops.pmu.get_wpr(g, &wpr_inf);
g->acr.get_wpr_info(g, &wpr_inf);
/*
* Even though this mem_desc wouldn't be used, the wpr region needs to
@@ -456,7 +456,7 @@ int gp106_prepare_ucode_blob(struct gk20a *g)
memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr_v1));
gr_gk20a_init_ctxsw_ucode(g);
g->ops.pmu.get_wpr(g, &wpr_inf);
g->acr.get_wpr_info(g, &wpr_inf);
gp106_dbg_pmu(g, "wpr carveout base:%llx\n", (wpr_inf.wpr_base));
gp106_dbg_pmu(g, "wpr carveout size :%x\n", (u32)wpr_inf.size);
@@ -479,7 +479,7 @@ int gp106_prepare_ucode_blob(struct gk20a *g)
}
/*Alloc memory to hold ucode blob contents*/
err = g->ops.pmu.alloc_blob_space(g, plsfm->wpr_size
err = g->acr.alloc_blob_space(g, plsfm->wpr_size
,&g->acr.ucode_blob);
if (err) {
goto exit_err;
@@ -557,7 +557,7 @@ int lsfm_discover_ucode_images(struct gk20a *g,
/*0th index is always PMU which is already handled in earlier
if condition*/
for (i = 1; i < (MAX_SUPPORTED_LSFM); i++) {
for (i = 1; i < g->acr.max_supported_lsfm; i++) {
memset(&ucode_img, 0, sizeof(ucode_img));
if (pmu_acr_supp_ucode_list[i](g, &ucode_img) == 0) {
if (ucode_img.lsf_desc != NULL) {
@@ -626,7 +626,7 @@ int gp106_pmu_populate_loader_cfg(struct gk20a *g,
* physical addresses of each respective segment.
*/
addr_base = p_lsfm->lsb_header.ucode_off;
g->ops.pmu.get_wpr(g, &wpr_inf);
g->acr.get_wpr_info(g, &wpr_inf);
addr_base += (wpr_inf.wpr_base);
gp106_dbg_pmu(g, "pmu loader cfg addrbase 0x%llx\n", addr_base);
@@ -701,7 +701,7 @@ int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g,
* physical addresses of each respective segment.
*/
addr_base = p_lsfm->lsb_header.ucode_off;
g->ops.pmu.get_wpr(g, &wpr_inf);
g->acr.get_wpr_info(g, &wpr_inf);
addr_base += wpr_inf.wpr_base;
gp106_dbg_pmu(g, "falcon ID %x", p_lsfm->wpr_header.falcon_id);
@@ -1017,7 +1017,7 @@ int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
/* Fill in static WPR header info*/
pnode->wpr_header.falcon_id = falcon_id;
pnode->wpr_header.bootstrap_owner = g->bootstrap_owner;
pnode->wpr_header.bootstrap_owner = g->acr.bootstrap_owner;
pnode->wpr_header.status = LSF_IMAGE_STATUS_COPY;
pnode->wpr_header.lazy_bootstrap =
@@ -1030,6 +1030,7 @@ int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
pnode->wpr_header.bin_version = pnode->lsb_header.signature.version;
pnode->next = plsfm->ucode_img_list;
plsfm->ucode_img_list = pnode;
return 0;
}
@@ -1191,3 +1192,121 @@ int lsf_gen_wpr_requirements(struct gk20a *g,
plsfm->wpr_size = wpr_offset;
return 0;
}
int gp106_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, bool is_recovery)
{
struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
struct acr_fw_header *acr_fw_hdr = NULL;
struct bin_hdr *acr_fw_bin_hdr = NULL;
struct flcn_acr_desc_v1 *acr_dmem_desc;
struct wpr_carveout_info wpr_inf;
u32 *acr_ucode_header = NULL;
u32 *acr_ucode_data = NULL;
nvgpu_log_fn(g, " ");
acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
acr_fw_hdr = (struct acr_fw_header *)
(acr_fw->data + acr_fw_bin_hdr->header_offset);
acr_ucode_data = (u32 *)(acr_fw->data + acr_fw_bin_hdr->data_offset);
acr_ucode_header = (u32 *)(acr_fw->data + acr_fw_hdr->hdr_offset);
acr->get_wpr_info(g, &wpr_inf);
acr_dmem_desc = (struct flcn_acr_desc_v1 *)
&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
acr_dmem_desc->nonwpr_ucode_blob_start = wpr_inf.nonwpr_base;
acr_dmem_desc->nonwpr_ucode_blob_size = wpr_inf.size;
acr_dmem_desc->regions.no_regions = 1U;
acr_dmem_desc->wpr_offset = 0U;
acr_dmem_desc->wpr_region_id = 1U;
acr_dmem_desc->regions.region_props[0U].region_id = 1U;
acr_dmem_desc->regions.region_props[0U].start_addr =
(wpr_inf.wpr_base) >> 8U;
acr_dmem_desc->regions.region_props[0U].end_addr =
((wpr_inf.wpr_base) + wpr_inf.size) >> 8U;
acr_dmem_desc->regions.region_props[0U].shadowmMem_startaddress =
wpr_inf.nonwpr_base >> 8U;
return 0;
}
int gp106_acr_fill_bl_dmem_desc(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header)
{
struct nvgpu_mem *acr_ucode_mem = &acr_desc->acr_ucode;
struct flcn_bl_dmem_desc_v1 *bl_dmem_desc =
&acr_desc->bl_dmem_desc_v1;
nvgpu_log_fn(g, " ");
memset(bl_dmem_desc, 0U, sizeof(struct flcn_bl_dmem_desc_v1));
bl_dmem_desc->signature[0] = 0U;
bl_dmem_desc->signature[1] = 0U;
bl_dmem_desc->signature[2] = 0U;
bl_dmem_desc->signature[3] = 0U;
bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
flcn64_set_dma(&bl_dmem_desc->code_dma_base,
acr_ucode_mem->gpu_va);
bl_dmem_desc->non_sec_code_off = acr_ucode_header[0U];
bl_dmem_desc->non_sec_code_size = acr_ucode_header[1U];
bl_dmem_desc->sec_code_off = acr_ucode_header[5U];
bl_dmem_desc->sec_code_size = acr_ucode_header[6U];
bl_dmem_desc->code_entry_point = 0U;
flcn64_set_dma(&bl_dmem_desc->data_dma_base,
acr_ucode_mem->gpu_va + acr_ucode_header[2U]);
bl_dmem_desc->data_size = acr_ucode_header[3U];
return 0;
}
static void nvgpu_gp106_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
{
struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl;
nvgpu_log_fn(g, " ");
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
hs_acr->acr_type = ACR_DEFAULT;
hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE;
hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1;
hs_acr->bl_dmem_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
hs_acr->acr_flcn = &g->sec2_flcn;
hs_acr->acr_flcn_setup_hw_and_bl_bootstrap =
gp106_sec2_setup_hw_and_bl_bootstrap;
}
void nvgpu_gp106_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
{
nvgpu_log_fn(g, " ");
acr->g = g;
acr->bootstrap_owner = LSF_FALCON_ID_SEC2;
acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
nvgpu_gp106_acr_default_sw_init(g, &acr->acr);
acr->get_wpr_info = gp106_wpr_info;
acr->alloc_blob_space = gp106_alloc_blob_space;
acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr;
acr->patch_wpr_info_to_ucode =
gp106_acr_patch_wpr_info_to_ucode;
acr->acr_fill_bl_dmem_desc =
gp106_acr_fill_bl_dmem_desc;
acr->remove_support = gm20b_remove_acr_support;
}

8
drivers/gpu/nvgpu/gp106/acr_gp106.h
View File

@@ -63,4 +63,12 @@ int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g,
void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
struct lsfm_managed_ucode_img_v2 *pnode);
int gp106_acr_fill_bl_dmem_desc(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header);
int gp106_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, bool is_recovery);
void nvgpu_gp106_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
#endif /* NVGPU_ACR_GP106_H */

5
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -800,6 +800,9 @@ static const struct gpu_ops gp106_ops = {
.read_vin_cal_gain_offset_fuse =
gp106_fuse_read_vin_cal_gain_offset_fuse,
},
.acr = {
.acr_sw_init = nvgpu_gp106_acr_sw_init,
},
.get_litter_value = gp106_get_litter_value,
.chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
};
@@ -855,6 +858,7 @@ int gp106_init_hal(struct gk20a *g)
gops->falcon = gp106_ops.falcon;
gops->priv_ring = gp106_ops.priv_ring;
gops->fuse = gp106_ops.fuse;
gops->acr = gp106_ops.acr;
/* Lone functions */
gops->get_litter_value = gp106_ops.get_litter_value;
@@ -875,7 +879,6 @@ int gp106_init_hal(struct gk20a *g)
}
g->pmu_lsf_pmu_wpr_init_done = 0;
g->bootstrap_owner = LSF_FALCON_ID_SEC2;
gops->clk.split_rail_support = true;
gops->clk.support_clk_freq_controller = true;
gops->clk.support_pmgr_domain = true;

193
drivers/gpu/nvgpu/gp106/sec2_gp106.c
View File

@@ -32,147 +32,6 @@
#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
#include <nvgpu/hw/gp106/hw_psec_gp106.h>
int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g,
unsigned int timeout)
{
int status = 0;
if (nvgpu_flcn_clear_halt_intr_status(&g->sec2_flcn, timeout)) {
status = -EBUSY;
}
return status;
}
int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
{
u32 data = 0;
int completion = 0;
completion = nvgpu_flcn_wait_for_halt(&g->sec2_flcn, timeout);
if (completion) {
nvgpu_err(g, "ACR boot timed out");
goto exit;
}
g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn,
FALCON_MAILBOX_1);
nvgpu_pmu_dbg(g, "ACR capabilities %x\n", g->acr.capabilities);
data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0);
if (data) {
nvgpu_err(g, "ACR boot failed, err %x", data);
completion = -EAGAIN;
goto exit;
}
init_pmu_setup_hw1(g);
exit:
if (completion) {
nvgpu_kill_task_pg_init(g);
nvgpu_pmu_state_change(g, PMU_STATE_OFF, false);
nvgpu_flcn_dump_stats(&g->sec2_flcn);
}
return completion;
}
int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
void *desc, u32 bl_sz)
{
struct gk20a *g = gk20a_from_pmu(pmu);
struct mm_gk20a *mm = &g->mm;
struct nvgpu_falcon_bl_info bl_info;
u32 data = 0;
nvgpu_log_fn(g, " ");
/* SEC2 Config */
gk20a_writel(g, psec_falcon_itfen_r(),
gk20a_readl(g, psec_falcon_itfen_r()) |
psec_falcon_itfen_ctxen_enable_f());
gk20a_writel(g, psec_falcon_nxtctx_r(),
pwr_pmu_new_instblk_ptr_f(
nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
pwr_pmu_new_instblk_valid_f(1) |
nvgpu_aperture_mask(g, &mm->pmu.inst_block,
pwr_pmu_new_instblk_target_sys_ncoh_f(),
pwr_pmu_new_instblk_target_sys_coh_f(),
pwr_pmu_new_instblk_target_fb_f()));
data = gk20a_readl(g, psec_falcon_debug1_r());
data |= psec_falcon_debug1_ctxsw_mode_m();
gk20a_writel(g, psec_falcon_debug1_r(), data);
data = gk20a_readl(g, psec_falcon_engctl_r());
data |= (1 << 3);
gk20a_writel(g, psec_falcon_engctl_r(), data);
bl_info.bl_src = g->acr.hsbl_ucode.cpu_va;
bl_info.bl_desc = desc;
bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
bl_info.bl_size = bl_sz;
bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag;
nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, &bl_info);
return 0;
}
void init_pmu_setup_hw1(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
struct nvgpu_pmu *pmu = &g->pmu;
/* PMU TRANSCFG */
/* setup apertures - virtual */
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
pwr_fbif_transcfg_mem_type_physical_f() |
pwr_fbif_transcfg_target_local_fb_f());
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
pwr_fbif_transcfg_mem_type_virtual_f());
/* setup apertures - physical */
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
pwr_fbif_transcfg_mem_type_physical_f() |
pwr_fbif_transcfg_target_local_fb_f());
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
pwr_fbif_transcfg_mem_type_physical_f() |
pwr_fbif_transcfg_target_coherent_sysmem_f());
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
pwr_fbif_transcfg_mem_type_physical_f() |
pwr_fbif_transcfg_target_noncoherent_sysmem_f());
/* PMU Config */
gk20a_writel(g, pwr_falcon_itfen_r(),
gk20a_readl(g, pwr_falcon_itfen_r()) |
pwr_falcon_itfen_ctxen_enable_f());
gk20a_writel(g, pwr_pmu_new_instblk_r(),
pwr_pmu_new_instblk_ptr_f(
nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
pwr_pmu_new_instblk_valid_f(1) |
nvgpu_aperture_mask(g, &mm->pmu.inst_block,
pwr_pmu_new_instblk_target_sys_ncoh_f(),
pwr_pmu_new_instblk_target_sys_coh_f(),
pwr_pmu_new_instblk_target_fb_f()));
/*Copying pmu cmdline args*/
g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, 0);
g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
pmu, GK20A_PMU_TRACE_BUFSIZE);
g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
pmu, GK20A_PMU_DMAIDX_VIRT);
if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) {
g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu);
}
nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args,
(u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
}
int gp106_sec2_reset(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
@@ -187,12 +46,47 @@ int gp106_sec2_reset(struct gk20a *g)
return 0;
}
int init_sec2_setup_hw1(struct gk20a *g,
void *desc, u32 bl_sz)
static int sec2_flcn_bl_bootstrap(struct gk20a *g,
struct nvgpu_falcon_bl_info *bl_info)
{
struct nvgpu_pmu *pmu = &g->pmu;
int err;
u32 data = 0;
struct mm_gk20a *mm = &g->mm;
u32 data = 0U;
int err = 0U;
nvgpu_log_fn(g, " ");
/* SEC2 Config */
gk20a_writel(g, psec_falcon_itfen_r(),
gk20a_readl(g, psec_falcon_itfen_r()) |
psec_falcon_itfen_ctxen_enable_f());
gk20a_writel(g, psec_falcon_nxtctx_r(),
pwr_pmu_new_instblk_ptr_f(
nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) |
pwr_pmu_new_instblk_valid_f(1U) |
nvgpu_aperture_mask(g, &mm->pmu.inst_block,
pwr_pmu_new_instblk_target_sys_ncoh_f(),
pwr_pmu_new_instblk_target_sys_coh_f(),
pwr_pmu_new_instblk_target_fb_f()));
data = gk20a_readl(g, psec_falcon_debug1_r());
data |= psec_falcon_debug1_ctxsw_mode_m();
gk20a_writel(g, psec_falcon_debug1_r(), data);
data = gk20a_readl(g, psec_falcon_engctl_r());
data |= (1U << 3U);
gk20a_writel(g, psec_falcon_engctl_r(), data);
err = nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, bl_info);
return err;
}
int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g,
struct hs_acr *acr_desc,
struct nvgpu_falcon_bl_info *bl_info)
{
u32 data = 0U;
nvgpu_log_fn(g, " ");
@@ -219,10 +113,5 @@ int init_sec2_setup_hw1(struct gk20a *g,
psec_fbif_transcfg_mem_type_physical_f() |
psec_fbif_transcfg_target_noncoherent_sysmem_f());
err = bl_bootstrap_sec2(pmu, desc, bl_sz);
if (err) {
return err;
}
return 0;
return sec2_flcn_bl_bootstrap(g, bl_info);
}

12
drivers/gpu/nvgpu/gp106/sec2_gp106.h
View File

@@ -23,14 +23,10 @@
#ifndef NVGPU_SEC2_GP106_H
#define NVGPU_SEC2_GP106_H
int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g,
unsigned int timeout);
int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
void *desc, u32 bl_sz);
void init_pmu_setup_hw1(struct gk20a *g);
int init_sec2_setup_hw1(struct gk20a *g,
void *desc, u32 bl_sz);
int gp106_sec2_reset(struct gk20a *g);
int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g,
struct hs_acr *acr_desc,
struct nvgpu_falcon_bl_info *bl_info);
#endif /* NVGPU_SEC2_GP106_H */

5
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -723,6 +723,9 @@ static const struct gpu_ops gp10b_ops = {
.read_vin_cal_slope_intercept_fuse = NULL,
.read_vin_cal_gain_offset_fuse = NULL,
},
.acr = {
.acr_sw_init = nvgpu_gm20b_acr_sw_init,
},
.chip_init_gpu_characteristics = gp10b_init_gpu_characteristics,
.get_litter_value = gp10b_get_litter_value,
};
@@ -761,6 +764,7 @@ int gp10b_init_hal(struct gk20a *g)
gops->priv_ring = gp10b_ops.priv_ring;
gops->fuse = gp10b_ops.fuse;
gops->acr = gp10b_ops.acr;
/* Lone Functions */
gops->chip_init_gpu_characteristics =
@@ -812,7 +816,6 @@ int gp10b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
g->pmu_lsf_pmu_wpr_init_done = 0;
g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
g->name = "gp10b";

5
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -930,6 +930,9 @@ static const struct gpu_ops gv100_ops = {
.set_nvhsclk_ctrl_swap_clk_nvl =
gv100_top_set_nvhsclk_ctrl_swap_clk_nvl,
},
.acr = {
.acr_sw_init = nvgpu_gp106_acr_sw_init,
},
.chip_init_gpu_characteristics = gv100_init_gpu_characteristics,
.get_litter_value = gv100_get_litter_value,
};
@@ -969,6 +972,7 @@ int gv100_init_hal(struct gk20a *g)
gops->fuse = gv100_ops.fuse;
gops->nvlink = gv100_ops.nvlink;
gops->top = gv100_ops.top;
gops->acr = gv100_ops.acr;
/* clocks */
gops->clk.init_clk_support = gv100_ops.clk.init_clk_support;
@@ -995,7 +999,6 @@ int gv100_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
g->pmu_lsf_pmu_wpr_init_done = 0;
g->bootstrap_owner = LSF_FALCON_ID_SEC2;
gops->clk.split_rail_support = false;
gops->clk.support_clk_freq_controller = false;
gops->clk.support_pmgr_domain = false;

87
drivers/gpu/nvgpu/gv11b/acr_gv11b.c
View File

@@ -38,6 +38,7 @@
#include "acr_gv11b.h"
#include "pmu_gv11b.h"
#include "gm20b/mm_gm20b.h"
#include "gm20b/pmu_gm20b.h"
#include "gm20b/acr_gm20b.h"
#include "gp106/acr_gp106.h"
@@ -68,6 +69,8 @@ void gv11b_setup_apertures(struct gk20a *g)
struct mm_gk20a *mm = &g->mm;
struct nvgpu_mem *inst_block = &mm->pmu.inst_block;
nvgpu_log_fn(g, " ");
/* setup apertures - virtual */
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
pwr_fbif_transcfg_mem_type_physical_f() |
@@ -91,3 +94,87 @@ void gv11b_setup_apertures(struct gk20a *g)
pwr_fbif_transcfg_mem_type_physical_f() |
pwr_fbif_transcfg_target_noncoherent_sysmem_f());
}
int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, bool is_recovery)
{
struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
struct acr_fw_header *acr_fw_hdr = NULL;
struct bin_hdr *acr_fw_bin_hdr = NULL;
struct flcn_acr_desc_v1 *acr_dmem_desc;
u32 *acr_ucode_header = NULL;
u32 *acr_ucode_data = NULL;
nvgpu_log_fn(g, " ");
if (is_recovery) {
acr_desc->acr_dmem_desc_v1->nonwpr_ucode_blob_size = 0U;
} else {
acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
acr_fw_hdr = (struct acr_fw_header *)
(acr_fw->data + acr_fw_bin_hdr->header_offset);
acr_ucode_data = (u32 *)(acr_fw->data +
acr_fw_bin_hdr->data_offset);
acr_ucode_header = (u32 *)(acr_fw->data +
acr_fw_hdr->hdr_offset);
/* During recovery need to update blob size as 0x0*/
acr_desc->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)
((u8 *)(acr_desc->acr_ucode.cpu_va) +
acr_ucode_header[2U]);
/* Patch WPR info to ucode */
acr_dmem_desc = (struct flcn_acr_desc_v1 *)
&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
acr_dmem_desc->nonwpr_ucode_blob_start =
nvgpu_mem_get_addr(g, &g->acr.ucode_blob);
acr_dmem_desc->nonwpr_ucode_blob_size =
g->acr.ucode_blob.size;
acr_dmem_desc->regions.no_regions = 1U;
acr_dmem_desc->wpr_offset = 0U;
}
return 0;
}
static void gv11b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
{
struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl;
nvgpu_log_fn(g, " ");
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
hs_acr->acr_type = ACR_DEFAULT;
hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE;
hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1;
hs_acr->bl_dmem_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
hs_acr->acr_flcn = &g->pmu_flcn;
hs_acr->acr_flcn_setup_hw_and_bl_bootstrap =
gm20b_pmu_setup_hw_and_bl_bootstrap;
}
void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
{
nvgpu_log_fn(g, " ");
acr->g = g;
acr->bootstrap_owner = LSF_FALCON_ID_PMU;
acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
gv11b_acr_default_sw_init(g, &acr->acr);
acr->get_wpr_info = gm20b_wpr_info;
acr->alloc_blob_space = gv11b_alloc_blob_space;
acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr;
acr->patch_wpr_info_to_ucode = gv11b_acr_patch_wpr_info_to_ucode;
acr->acr_fill_bl_dmem_desc =
gp106_acr_fill_bl_dmem_desc;
acr->remove_support = gm20b_remove_acr_support;
}

5
drivers/gpu/nvgpu/gv11b/acr_gv11b.h
View File

@@ -30,4 +30,9 @@ int gv11b_init_pmu_setup_hw1(struct gk20a *g,
void gv11b_setup_apertures(struct gk20a *g);
int gv11b_alloc_blob_space(struct gk20a *g, size_t size,
struct nvgpu_mem *mem);
void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, bool is_recovery);
#endif /* NVGPU_ACR_GV11B_H */

5
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -823,6 +823,9 @@ static const struct gpu_ops gv11b_ops = {
.read_vin_cal_slope_intercept_fuse = NULL,
.read_vin_cal_gain_offset_fuse = NULL,
},
.acr = {
.acr_sw_init = nvgpu_gv11b_acr_sw_init,
},
.chip_init_gpu_characteristics = gv11b_init_gpu_characteristics,
.get_litter_value = gv11b_get_litter_value,
};
@@ -858,6 +861,7 @@ int gv11b_init_hal(struct gk20a *g)
gops->priv_ring = gv11b_ops.priv_ring;
gops->fuse = gv11b_ops.fuse;
gops->clk_arb = gv11b_ops.clk_arb;
gops->acr = gv11b_ops.acr;
/* Lone functions */
gops->chip_init_gpu_characteristics =
@@ -903,7 +907,6 @@ int gv11b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
__nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
__nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);

110
drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,8 @@
#ifndef __NVGPU_ACR_H__
#define __NVGPU_ACR_H__
#include <nvgpu/falcon.h>
#include "gk20a/mm_gk20a.h"
#include "acr_lsfm.h"
@@ -31,6 +33,13 @@
#include "acr_objflcn.h"
struct nvgpu_firmware;
struct gk20a;
struct hs_acr_ops;
struct hs_acr;
struct nvgpu_acr;
#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
#define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
@@ -77,29 +86,94 @@ struct wpr_carveout_info {
u64 size;
};
struct acr_desc {
struct nvgpu_mem ucode_blob;
struct nvgpu_mem wpr_dummy;
struct bin_hdr *bl_bin_hdr;
struct hsflcn_bl_desc *pmu_hsbl_desc;
struct bin_hdr *hsbin_hdr;
struct acr_fw_header *fw_hdr;
u32 pmu_args;
/* ACR interfaces */
struct hs_flcn_bl {
char *bl_fw_name;
struct nvgpu_firmware *hs_bl_fw;
struct hsflcn_bl_desc *hs_bl_desc;
struct bin_hdr *hs_bl_bin_hdr;
struct nvgpu_mem hs_bl_ucode;
};
struct hs_acr {
u32 acr_type;
/* HS bootloader to validate & load ACR ucode */
struct hs_flcn_bl acr_hs_bl;
/* ACR ucode */
char *acr_fw_name;
struct nvgpu_firmware *acr_fw;
union{
struct flcn_acr_desc *acr_dmem_desc;
struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
};
struct nvgpu_mem acr_ucode;
struct nvgpu_firmware *hsbl_fw;
struct nvgpu_mem hsbl_ucode;
union {
struct flcn_bl_dmem_desc bl_dmem_desc;
struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
};
struct nvgpu_firmware *pmu_fw;
struct nvgpu_firmware *pmu_desc;
u32 capabilities;
void *ptr_bl_dmem_desc;
u32 bl_dmem_desc_size;
union{
struct flcn_acr_desc *acr_dmem_desc;
struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
};
/* Falcon used to execute ACR ucode */
struct nvgpu_falcon *acr_flcn;
int (*acr_flcn_setup_hw_and_bl_bootstrap)(struct gk20a *g,
struct hs_acr *acr_desc,
struct nvgpu_falcon_bl_info *bl_info);
};
#define ACR_DEFAULT 0U
#define ACR_AHESASC 1U
#define ACR_ASB 2U
struct nvgpu_acr {
struct gk20a *g;
u32 bootstrap_owner;
u32 max_supported_lsfm;
u32 capabilities;
/*
* non-wpr space to hold LSF ucodes,
* ACR does copy ucode from non-wpr to wpr
*/
struct nvgpu_mem ucode_blob;
/*
* Even though this mem_desc wouldn't be used,
* the wpr region needs to be reserved in the
* allocator in dGPU case.
*/
struct nvgpu_mem wpr_dummy;
/* ACR member for different types of ucode */
/* For older dgpu/tegra ACR cuode */
struct hs_acr acr;
/* ACR load split feature support */
struct hs_acr acr_ahesasc;
struct hs_acr acr_asb;
u32 pmu_args;
struct nvgpu_firmware *pmu_fw;
struct nvgpu_firmware *pmu_desc;
int (*prepare_ucode_blob)(struct gk20a *g, struct nvgpu_acr *acr);
void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf);
int (*alloc_blob_space)(struct gk20a *g, size_t size,
struct nvgpu_mem *mem);
int (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, bool is_recovery);
int (*acr_fill_bl_dmem_desc)(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header);
int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc);
void (*remove_support)(struct nvgpu_acr *acr);
};
#endif /*__NVGPU_ACR_H__*/

9
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1054,9 +1054,6 @@ struct gpu_ops {
bool (*is_engine_in_reset)(struct gk20a *g);
bool (*is_lazy_bootstrap)(u32 falcon_id);
bool (*is_priv_load)(u32 falcon_id);
void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf);
int (*alloc_blob_space)(struct gk20a *g,
size_t size, struct nvgpu_mem *mem);
int (*pmu_populate_loader_cfg)(struct gk20a *g,
void *lsfm, u32 *p_bl_gen_desc_size);
int (*flcn_populate_bl_dmem_desc)(struct gk20a *g,
@@ -1318,6 +1315,9 @@ struct gpu_ops {
u32 (*get_nvhsclk_ctrl_swap_clk_nvl)(struct gk20a *g);
void (*set_nvhsclk_ctrl_swap_clk_nvl)(struct gk20a *g, u32 val);
} top;
struct {
void (*acr_sw_init)(struct gk20a *g, struct nvgpu_acr *acr);
} acr;
void (*semaphore_wakeup)(struct gk20a *g, bool post_events);
};
@@ -1429,7 +1429,7 @@ struct gk20a {
struct sim_nvgpu *sim;
struct mm_gk20a mm;
struct nvgpu_pmu pmu;
struct acr_desc acr;
struct nvgpu_acr acr;
struct nvgpu_ecc ecc;
struct clk_pmupstate clk_pmu;
struct perf_pmupstate perf_pmu;
@@ -1477,7 +1477,6 @@ struct gk20a {
u32 disable_syncpoints;
bool support_pmu;
u32 bootstrap_owner;
bool is_virtual;

4
drivers/gpu/nvgpu/os/linux/module.c
View File

@@ -683,6 +683,10 @@ void gk20a_remove_support(struct gk20a *g)
if (g->pmu.remove_support)
g->pmu.remove_support(&g->pmu);
if (g->acr.remove_support != NULL) {
g->acr.remove_support(&g->acr);
}
if (g->gr.remove_support)
g->gr.remove_support(&g->gr);

5
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -548,6 +548,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.read_vin_cal_slope_intercept_fuse = NULL,
.read_vin_cal_gain_offset_fuse = NULL,
},
.acr = {
.acr_sw_init = nvgpu_gm20b_acr_sw_init,
},
.chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
.get_litter_value = gp10b_get_litter_value,
};
@@ -585,6 +588,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
gops->priv_ring = vgpu_gp10b_ops.priv_ring;
gops->fuse = vgpu_gp10b_ops.fuse;
gops->acr = vgpu_gp10b_ops.acr;
/* Lone Functions */
gops->chip_init_gpu_characteristics =
@@ -631,7 +635,6 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
g->pmu_lsf_pmu_wpr_init_done = 0;
g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
g->name = "gp10b";

4
drivers/gpu/nvgpu/vgpu/vgpu.c
View File

@@ -217,6 +217,10 @@ void vgpu_remove_support_common(struct gk20a *g)
if (g->pmu.remove_support)
g->pmu.remove_support(&g->pmu);
if (g->acr.remove_support != NULL) {
g->acr.remove_support(&g->acr);
}
if (g->gr.remove_support)
g->gr.remove_support(&g->gr);