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gpu: nvgpu: fix MISRA 17.7 rule in gr falcon
Added return value error check for following function calls: nvgpu_gr_falcon_copy_ctxsw_ucode_segments JIRA NVGPU-3226 Change-Id: I52b930cc33414a93407b6ab60189148e93d8fcea Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2107662 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -326,20 +326,28 @@ int nvgpu_gr_falcon_init_ctxsw_ucode(struct gk20a *g,
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goto clean_up;
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}
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nvgpu_gr_falcon_copy_ctxsw_ucode_segments(g, &ucode_info->surface_desc,
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err = nvgpu_gr_falcon_copy_ctxsw_ucode_segments(g,
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&ucode_info->surface_desc,
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&ucode_info->fecs,
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fecs_boot_image,
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nvgpu_netlist_get_fecs_inst_list(g),
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nvgpu_netlist_get_fecs_data_list(g));
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if (err != 0) {
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goto clean_up;
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}
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nvgpu_release_firmware(g, fecs_fw);
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fecs_fw = NULL;
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nvgpu_gr_falcon_copy_ctxsw_ucode_segments(g, &ucode_info->surface_desc,
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err = nvgpu_gr_falcon_copy_ctxsw_ucode_segments(g,
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&ucode_info->surface_desc,
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&ucode_info->gpccs,
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gpccs_boot_image,
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nvgpu_netlist_get_gpccs_inst_list(g),
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nvgpu_netlist_get_gpccs_data_list(g));
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if (err != 0) {
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goto clean_up;
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}
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nvgpu_release_firmware(g, gpccs_fw);
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gpccs_fw = NULL;
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