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gpu: nvgpu: make iommu bit getting hal NULL for turing

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For dgpu iommu bit is causing smmu fault when sysmem is accessed
via pcie. Since pcie is always having iommu enabled on linux that
creates issue for linux. So don't set the iommu bit for dgpu in any
case.

Bug 200640033

Change-Id: I38556779db94289b0656cdb53d417e4ff83ed426
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2384653
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
shashank singh
2020-07-23 21:39:50 +05:30
committed by Alex Waterman
parent e161c8d7fa
commit 650ce63466
2 changed files with 6 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1232,7 +1232,8 @@ static const struct gpu_ops tu104_ops = {
.get_big_page_sizes = gm20b_mm_get_big_page_sizes,
.get_default_big_page_size =
nvgpu_gmmu_default_big_page_size,
.get_iommu_bit = gp10b_mm_get_iommu_bit,
/* iommu bit is not applicable for dgpu */
.get_iommu_bit = NULL,
.gpu_phys_addr = gv11b_gpu_phys_addr,
}
},

7
drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gv11b_fusa.c
View File

@@ -27,13 +27,14 @@
/*
* On Volta the GPU determines whether to do L3 allocation for a mapping by
* checking bit 36 of the phsyical address. So if a mapping should allocte lines
* in the L3 this bit must be set.
* checking the l3 alloc bit (bit number depends on soc) of the physical address.
* So if a mapping should allocate lines in the L3 this bit must be set.
*/
u64 gv11b_gpu_phys_addr(struct gk20a *g,
struct nvgpu_gmmu_attrs *attrs, u64 phys)
{
if ((attrs != NULL) && attrs->l3_alloc) {
if ((attrs != NULL) && attrs->l3_alloc &&
(g->ops.mm.gmmu.get_iommu_bit != NULL)) {
return phys | BIT64(g->ops.mm.gmmu.get_iommu_bit(g));
}