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nvgpu: gpu: change log level for ctxsw wdt init

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Jira NVGPU-3250

Change-Id: I1dcb6290ab1fdac4cda7aa846bc2a0d3ab83a2be
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105798
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2019-04-26 15:23:27 +05:30
committed by mobile promotions
parent be0eabeb6c
commit 688242bcb3
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c
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@@ -643,7 +643,7 @@ int gm20b_gr_falcon_wait_ctxsw_ready(struct gk20a *g)
return -1;
}
nvgpu_info(g, "SYSCLK = %lu MHz", sysclk_freq_mhz);
nvgpu_log_info(g, "SYSCLK = %lu MHz", sysclk_freq_mhz);
if (g->ctxsw_wdt_period_us != 0U) {
wdt_val = (unsigned int)(sysclk_freq_mhz *
g->ctxsw_wdt_period_us);
@@ -651,7 +651,7 @@ int gm20b_gr_falcon_wait_ctxsw_ready(struct gk20a *g)
}
}
nvgpu_info(g, "configuring ctxsw_ucode wdt = 0x%x", wdt_val);
nvgpu_log_info(g, "configuring ctxsw_ucode wdt = 0x%x", wdt_val);
nvgpu_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), U32_MAX);
nvgpu_writel(g, gr_fecs_method_data_r(), wdt_val);
nvgpu_writel(g, gr_fecs_method_push_r(),