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gpu: nvgpu: remove hw_pri_ringmaster_gm20b.h include from gr/config

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Unit gr/config right now queries gpc_count from priv_ring by directly
reading the value from register

priv_ring unit now exposes below HAL to get gpc_count
g->ops.priv_ring.get_gpc_count()

Use this HAL in gr/config unit

Jira NVGPU-1879

Change-Id: Ibd3557b7f906690a7ad18f11d02a0a6990b98337
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016083
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-02-07 19:06:40 +05:30
committed by mobile promotions
parent 9345e5a74c
commit 6fb2abb153
9 changed files with 17 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/common/gr/config/gr_config.c
View File

@@ -24,8 +24,6 @@
#include <nvgpu/io.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h>
struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g)
{
struct nvgpu_gr_config *config;
@@ -34,7 +32,6 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g)
u32 pes_tpc_count;
u32 pes_heavy_index;
u32 gpc_new_skip_mask;
u32 tmp;
config = nvgpu_kzalloc(g, sizeof(*config));
if (config == NULL) {
@@ -48,8 +45,7 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g)
config->max_tpc_count = config->max_gpc_count *
config->max_tpc_per_gpc_count;
tmp = nvgpu_readl(g, pri_ringmaster_enum_gpc_r());
config->gpc_count = pri_ringmaster_enum_gpc_count_v(tmp);
config->gpc_count = g->ops.priv_ring.get_gpc_count(g);
if (config->gpc_count == 0U) {
nvgpu_err(g, "gpc_count==0!");
goto clean_up;

8
drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c
View File

@@ -123,3 +123,11 @@ u32 gm20b_priv_ring_enum_ltc(struct gk20a *g)
{
return gk20a_readl(g, pri_ringmaster_enum_ltc_r());
}
u32 gm20b_priv_ring_get_gpc_count(struct gk20a *g)
{
u32 tmp;
tmp = nvgpu_readl(g, pri_ringmaster_enum_gpc_r());
return pri_ringmaster_enum_gpc_count_v(tmp);
}

2
drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h
View File

@@ -29,4 +29,6 @@ void gm20b_priv_ring_enable(struct gk20a *g);
void gm20b_priv_set_timeout_settings(struct gk20a *g);
u32 gm20b_priv_ring_enum_ltc(struct gk20a *g);
u32 gm20b_priv_ring_get_gpc_count(struct gk20a *g);
#endif /* NVGPU_PRIV_RING_GM20B_H */

1
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -768,6 +768,7 @@ static const struct gpu_ops gm20b_ops = {
.set_ppriv_timeout_settings =
gm20b_priv_set_timeout_settings,
.enum_ltc = gm20b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
},
.fuse = {
.check_priv_security = gm20b_fuse_check_priv_security,

1
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -846,6 +846,7 @@ static const struct gpu_ops gp10b_ops = {
.set_ppriv_timeout_settings =
gm20b_priv_set_timeout_settings,
.enum_ltc = gm20b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
},
.fuse = {
.check_priv_security = gp10b_fuse_check_priv_security,

1
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -1054,6 +1054,7 @@ static const struct gpu_ops gv100_ops = {
.set_ppriv_timeout_settings =
gm20b_priv_set_timeout_settings,
.enum_ltc = gm20b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
},
.fuse = {
.is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,

1
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -982,6 +982,7 @@ static const struct gpu_ops gv11b_ops = {
.set_ppriv_timeout_settings =
gm20b_priv_set_timeout_settings,
.enum_ltc = gm20b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
},
.fuse = {
.check_priv_security = gp10b_fuse_check_priv_security,

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1466,6 +1466,7 @@ struct gpu_ops {
void (*decode_error_code)(struct gk20a *g, u32 error_code);
void (*set_ppriv_timeout_settings)(struct gk20a *g);
u32 (*enum_ltc)(struct gk20a *g);
u32 (*get_gpc_count)(struct gk20a *g);
} priv_ring;
struct {
int (*check_priv_security)(struct gk20a *g);

1
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -1093,6 +1093,7 @@ static const struct gpu_ops tu104_ops = {
.decode_error_code = gp10b_priv_ring_decode_error_code,
.set_ppriv_timeout_settings = NULL,
.enum_ltc = gm20b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
},
.fuse = {
.is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,