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gpu: nvgpu: debug: fix MISRA 5.7 violation

Browse Source 
MISRA 5.7 requires tag names be unique. Rename the struct
gk20a_debug_output to nvgpu_debug_context to avoid name collision with
the function of the same name.

JIRA NVGPU-3346

Change-Id: I9566b9dc6a7d090e87d9a09f6b8faf688589fbbd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116877
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-05-10 17:12:28 -04:00
committed by mobile promotions
parent 99bdda5846
commit 78c7e601f8
21 changed files with 50 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/fifo/channel.c
View File

@@ -2586,7 +2586,7 @@ void nvgpu_channel_free_inst(struct gk20a *g, struct nvgpu_channel *ch)
} }
void nvgpu_channel_debug_dump_all(struct gk20a *g, void nvgpu_channel_debug_dump_all(struct gk20a *g,
struct gk20a_debug_output *o) struct nvgpu_debug_context *o)
{ {
struct nvgpu_fifo *f = &g->fifo; struct nvgpu_fifo *f = &g->fifo;
u32 chid; u32 chid;

2
drivers/gpu/nvgpu/common/fifo/channel_gk20a.c
View File

@@ -107,7 +107,7 @@ void gk20a_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch,
} }
void gk20a_channel_debug_dump(struct gk20a *g, void gk20a_channel_debug_dump(struct gk20a *g,
struct gk20a_debug_output *o, struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info) struct nvgpu_channel_dump_info *info)
{ {
gk20a_debug_output(o, "Channel ID: %d, TSG ID: %u, pid %d, refs %d; " gk20a_debug_output(o, "Channel ID: %d, TSG ID: %u, pid %d, refs %d; "

4
drivers/gpu/nvgpu/common/fifo/channel_gk20a.h
View File

@@ -26,7 +26,7 @@
struct gk20a; struct gk20a;
struct nvgpu_channel; struct nvgpu_channel;
struct nvgpu_channel_hw_state; struct nvgpu_channel_hw_state;
struct gk20a_debug_output; struct nvgpu_debug_context;
struct nvgpu_channel_dump_info; struct nvgpu_channel_dump_info;
void gk20a_channel_enable(struct nvgpu_channel *ch); void gk20a_channel_enable(struct nvgpu_channel *ch);
@@ -36,6 +36,6 @@ void gk20a_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch,
struct nvgpu_channel_hw_state *state); struct nvgpu_channel_hw_state *state);
void gk20a_channel_debug_dump(struct gk20a *g, void gk20a_channel_debug_dump(struct gk20a *g,
struct gk20a_debug_output *o, struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info); struct nvgpu_channel_dump_info *info);
#endif /* FIFO_CHANNEL_GK20A_H */ #endif /* FIFO_CHANNEL_GK20A_H */

2
drivers/gpu/nvgpu/common/fifo/channel_gv11b.c
View File

@@ -82,7 +82,7 @@ void gv11b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
} }
void gv11b_channel_debug_dump(struct gk20a *g, void gv11b_channel_debug_dump(struct gk20a *g,
struct gk20a_debug_output *o, struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info) struct nvgpu_channel_dump_info *info)
{ {
gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d%s: ", gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d%s: ",

4
drivers/gpu/nvgpu/common/fifo/channel_gv11b.h
View File

@@ -28,7 +28,7 @@
struct gk20a; struct gk20a;
struct nvgpu_channel; struct nvgpu_channel;
struct nvgpu_channel_hw_state; struct nvgpu_channel_hw_state;
struct gk20a_debug_output; struct nvgpu_debug_context;
struct nvgpu_channel_dump_info; struct nvgpu_channel_dump_info;
void gv11b_channel_unbind(struct nvgpu_channel *ch); void gv11b_channel_unbind(struct nvgpu_channel *ch);
@@ -39,6 +39,6 @@ void gv11b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
bool eng, bool pbdma); bool eng, bool pbdma);
void gv11b_channel_debug_dump(struct gk20a *g, void gv11b_channel_debug_dump(struct gk20a *g,
struct gk20a_debug_output *o, struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info); struct nvgpu_channel_dump_info *info);
#endif /* FIFO_CHANNEL_GV11B_H */ #endif /* FIFO_CHANNEL_GV11B_H */

2
drivers/gpu/nvgpu/hal/fifo/engine_status_gm20b.c
View File

@@ -168,7 +168,7 @@ void gm20b_read_engine_status_info(struct gk20a *g, u32 engine_id,
} }
} }
void gm20b_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o) void gm20b_dump_engine_status(struct gk20a *g, struct nvgpu_debug_context *o)
{ {
u32 i, host_num_engines; u32 i, host_num_engines;
struct nvgpu_engine_status_info engine_status; struct nvgpu_engine_status_info engine_status;

4
drivers/gpu/nvgpu/hal/fifo/engine_status_gm20b.h
View File

@@ -27,12 +27,12 @@
struct gk20a; struct gk20a;
struct nvgpu_engine_status_info; struct nvgpu_engine_status_info;
struct gk20a_debug_output; struct nvgpu_debug_context;
void gm20b_read_engine_status_info(struct gk20a *g, u32 engine_id, void gm20b_read_engine_status_info(struct gk20a *g, u32 engine_id,
struct nvgpu_engine_status_info *status); struct nvgpu_engine_status_info *status);
void gm20b_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o); void gm20b_dump_engine_status(struct gk20a *g, struct nvgpu_debug_context *o);
#endif /* NVGPU_ENGINE_STATUS_GM20B_H */ #endif /* NVGPU_ENGINE_STATUS_GM20B_H */

2
drivers/gpu/nvgpu/hal/fifo/engine_status_gv100.c
View File

@@ -44,7 +44,7 @@ void gv100_read_engine_status_info(struct gk20a *g, u32 engine_id,
return; return;
} }
void gv100_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o) void gv100_dump_engine_status(struct gk20a *g, struct nvgpu_debug_context *o)
{ {
u32 i, host_num_engines; u32 i, host_num_engines;
struct nvgpu_engine_status_info engine_status; struct nvgpu_engine_status_info engine_status;

4
drivers/gpu/nvgpu/hal/fifo/engine_status_gv100.h
View File

@@ -27,12 +27,12 @@
struct gk20a; struct gk20a;
struct nvgpu_engine_status_info; struct nvgpu_engine_status_info;
struct gk20a_debug_output; struct nvgpu_debug_context;
void gv100_read_engine_status_info(struct gk20a *g, u32 engine_id, void gv100_read_engine_status_info(struct gk20a *g, u32 engine_id,
struct nvgpu_engine_status_info *status); struct nvgpu_engine_status_info *status);
void gv100_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o); void gv100_dump_engine_status(struct gk20a *g, struct nvgpu_debug_context *o);
#endif /* NVGPU_ENGINE_STATUS_GV100_H */ #endif /* NVGPU_ENGINE_STATUS_GV100_H */

4
drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.c
View File

@@ -314,7 +314,7 @@ u32 gm20b_pbdma_acquire_val(u64 timeout)
return val; return val;
} }
void gm20b_pbdma_dump_status(struct gk20a *g, struct gk20a_debug_output *o) void gm20b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o)
{ {
u32 i, host_num_pbdma; u32 i, host_num_pbdma;
struct nvgpu_pbdma_status_info pbdma_status; struct nvgpu_pbdma_status_info pbdma_status;
@@ -475,7 +475,7 @@ bool gm20b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id,
} }
void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g, void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
struct gk20a_debug_output *o, struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info) struct nvgpu_channel_dump_info *info)
{ {
#ifdef CONFIG_TEGRA_GK20A_NVHOST #ifdef CONFIG_TEGRA_GK20A_NVHOST

6
drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h
View File

@@ -26,7 +26,7 @@
#include <nvgpu/types.h> #include <nvgpu/types.h>
struct gk20a; struct gk20a;
struct gk20a_debug_output; struct nvgpu_debug_context;
struct nvgpu_channel_dump_info; struct nvgpu_channel_dump_info;
struct nvgpu_gpfifo_entry; struct nvgpu_gpfifo_entry;
@@ -44,7 +44,7 @@ void gm20b_pbdma_reset_header(struct gk20a *g, u32 pbdma_id);
void gm20b_pbdma_reset_method(struct gk20a *g, u32 pbdma_id, void gm20b_pbdma_reset_method(struct gk20a *g, u32 pbdma_id,
u32 pbdma_method_index); u32 pbdma_method_index);
u32 gm20b_pbdma_acquire_val(u64 timeout); u32 gm20b_pbdma_acquire_val(u64 timeout);
void gm20b_pbdma_dump_status(struct gk20a *g, struct gk20a_debug_output *o); void gm20b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o);
void gm20b_pbdma_format_gpfifo_entry(struct gk20a *g, void gm20b_pbdma_format_gpfifo_entry(struct gk20a *g,
struct nvgpu_gpfifo_entry *gpfifo_entry, struct nvgpu_gpfifo_entry *gpfifo_entry,
@@ -57,7 +57,7 @@ u32 gm20b_pbdma_restartable_0_intr_descs(void);
void gm20b_pbdma_clear_all_intr(struct gk20a *g, u32 pbdma_id); void gm20b_pbdma_clear_all_intr(struct gk20a *g, u32 pbdma_id);
void gm20b_pbdma_disable_and_clear_all_intr(struct gk20a *g); void gm20b_pbdma_disable_and_clear_all_intr(struct gk20a *g);
void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g, void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
struct gk20a_debug_output *o, struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info); struct nvgpu_channel_dump_info *info);
void gm20b_pbdma_setup_hw(struct gk20a *g); void gm20b_pbdma_setup_hw(struct gk20a *g);

2
drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c
View File

@@ -303,7 +303,7 @@ u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr)
} }
int gr_gm20b_dump_gr_status_regs(struct gk20a *g, int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
struct gk20a_debug_output *o) struct nvgpu_debug_context *o)
{ {
struct nvgpu_gr *gr = g->gr; struct nvgpu_gr *gr = g->gr;
u32 gr_engine_id; u32 gr_engine_id;

2
drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.h
View File

@@ -51,7 +51,7 @@ void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
bool gr_gm20b_is_tpc_addr(struct gk20a *g, u32 addr); bool gr_gm20b_is_tpc_addr(struct gk20a *g, u32 addr);
u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr); u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr);
int gr_gm20b_dump_gr_status_regs(struct gk20a *g, int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
struct gk20a_debug_output *o); struct nvgpu_debug_context *o);
int gr_gm20b_update_pc_sampling(struct nvgpu_channel *c, int gr_gm20b_update_pc_sampling(struct nvgpu_channel *c,
bool enable); bool enable);
void gr_gm20b_init_cyclestats(struct gk20a *g); void gr_gm20b_init_cyclestats(struct gk20a *g);

2
drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c
View File

@@ -231,7 +231,7 @@ void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
int gr_gp10b_dump_gr_status_regs(struct gk20a *g, int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
struct gk20a_debug_output *o) struct nvgpu_debug_context *o)
{ {
struct nvgpu_gr *gr = g->gr; struct nvgpu_gr *gr = g->gr;
u32 gr_engine_id; u32 gr_engine_id;

4
drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.h
View File

@@ -31,7 +31,7 @@ struct gk20a;
struct nvgpu_channel; struct nvgpu_channel;
struct nvgpu_gr_ctx; struct nvgpu_gr_ctx;
struct dbg_session_gk20a; struct dbg_session_gk20a;
struct gk20a_debug_output; struct nvgpu_debug_context;
#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF 0x0U #define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF 0x0U
#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1U #define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1U
@@ -43,7 +43,7 @@ void gr_gp10b_set_bes_crop_debug4(struct gk20a *g, u32 data);
void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data); void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data); void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data);
int gr_gp10b_dump_gr_status_regs(struct gk20a *g, int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
struct gk20a_debug_output *o); struct nvgpu_debug_context *o);
void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
int gr_gp10b_pre_process_sm_exception(struct gk20a *g, int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,

6
drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
View File

@@ -764,7 +764,7 @@ void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data)
} }
static void gr_gv11b_dump_gr_per_sm_regs(struct gk20a *g, static void gr_gv11b_dump_gr_per_sm_regs(struct gk20a *g,
struct gk20a_debug_output *o, struct nvgpu_debug_context *o,
u32 gpc, u32 tpc, u32 sm, u32 offset) u32 gpc, u32 tpc, u32 sm, u32 offset)
{ {
@@ -800,7 +800,7 @@ static void gr_gv11b_dump_gr_per_sm_regs(struct gk20a *g,
} }
static void gr_gv11b_dump_gr_sm_regs(struct gk20a *g, static void gr_gv11b_dump_gr_sm_regs(struct gk20a *g,
struct gk20a_debug_output *o) struct nvgpu_debug_context *o)
{ {
u32 gpc, tpc, sm, sm_per_tpc; u32 gpc, tpc, sm, sm_per_tpc;
u32 gpc_offset, tpc_offset, offset; u32 gpc_offset, tpc_offset, offset;
@@ -849,7 +849,7 @@ static void gr_gv11b_dump_gr_sm_regs(struct gk20a *g,
} }
int gr_gv11b_dump_gr_status_regs(struct gk20a *g, int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
struct gk20a_debug_output *o) struct nvgpu_debug_context *o)
{ {
struct nvgpu_gr *gr = g->gr; struct nvgpu_gr *gr = g->gr;
u32 gr_engine_id; u32 gr_engine_id;

4
drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h
View File

@@ -27,7 +27,7 @@
struct gk20a; struct gk20a;
struct nvgpu_warpstate; struct nvgpu_warpstate;
struct gk20a_debug_output; struct nvgpu_debug_context;
u32 gr_gv11b_ctxsw_checksum_mismatch_mailbox_val(void); u32 gr_gv11b_ctxsw_checksum_mismatch_mailbox_val(void);
void gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, void gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g,
@@ -37,7 +37,7 @@ void gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g,
void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data); void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data); void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data);
int gr_gv11b_dump_gr_status_regs(struct gk20a *g, int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
struct gk20a_debug_output *o); struct nvgpu_debug_context *o);
void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
int gr_gv11b_pre_process_sm_exception(struct gk20a *g, int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,

4
drivers/gpu/nvgpu/include/nvgpu/channel.h
View File

@@ -42,7 +42,7 @@ struct nvgpu_channel_sync;
struct nvgpu_gpfifo_userdata; struct nvgpu_gpfifo_userdata;
struct nvgpu_gr_subctx; struct nvgpu_gr_subctx;
struct nvgpu_gr_ctx; struct nvgpu_gr_ctx;
struct gk20a_debug_output; struct nvgpu_debug_context;
/* Flags to be passed to nvgpu_channel_setup_bind() */ /* Flags to be passed to nvgpu_channel_setup_bind() */
#define NVGPU_SETUP_BIND_FLAGS_SUPPORT_VPR BIT32(0) #define NVGPU_SETUP_BIND_FLAGS_SUPPORT_VPR BIT32(0)
@@ -546,7 +546,7 @@ int nvgpu_channel_set_syncpt(struct nvgpu_channel *ch);
struct nvgpu_channel *nvgpu_channel_refch_from_inst_ptr(struct gk20a *g, struct nvgpu_channel *nvgpu_channel_refch_from_inst_ptr(struct gk20a *g,
u64 inst_ptr); u64 inst_ptr);
void nvgpu_channel_debug_dump_all(struct gk20a *g, void nvgpu_channel_debug_dump_all(struct gk20a *g,
struct gk20a_debug_output *o); struct nvgpu_debug_context *o);
int nvgpu_channel_deferred_reset_engines(struct gk20a *g, int nvgpu_channel_deferred_reset_engines(struct gk20a *g,
struct nvgpu_channel *ch); struct nvgpu_channel *ch);

13
drivers/gpu/nvgpu/include/nvgpu/debug.h
View File

@@ -1,7 +1,7 @@
/* /*
* GK20A Debug functionality * GK20A Debug functionality
* *
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -30,7 +30,7 @@
struct gk20a; struct gk20a;
struct gpu_ops; struct gpu_ops;
struct gk20a_debug_output { struct nvgpu_debug_context {
void (*fn)(void *ctx, const char *str, size_t len); void (*fn)(void *ctx, const char *str, size_t len);
void *ctx; void *ctx;
char buf[256]; char buf[256];
@@ -40,11 +40,11 @@ struct gk20a_debug_output {
extern unsigned int gk20a_debug_trace_cmdbuf; extern unsigned int gk20a_debug_trace_cmdbuf;
__attribute__((format (printf, 2, 3))) __attribute__((format (printf, 2, 3)))
void gk20a_debug_output(struct gk20a_debug_output *o, void gk20a_debug_output(struct nvgpu_debug_context *o,
const char *fmt, ...); const char *fmt, ...);
void gk20a_debug_dump(struct gk20a *g); void gk20a_debug_dump(struct gk20a *g);
void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o); void gk20a_debug_show_dump(struct gk20a *g, struct nvgpu_debug_context *o);
void gk20a_gr_debug_dump(struct gk20a *g); void gk20a_gr_debug_dump(struct gk20a *g);
void gk20a_init_debug_ops(struct gpu_ops *gops); void gk20a_init_debug_ops(struct gpu_ops *gops);
@@ -52,11 +52,12 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink);
void gk20a_debug_deinit(struct gk20a *g); void gk20a_debug_deinit(struct gk20a *g);
#else #else
__attribute__((format (printf, 2, 3))) __attribute__((format (printf, 2, 3)))
static inline void gk20a_debug_output(struct gk20a_debug_output *o, static inline void gk20a_debug_output(struct nvgpu_debug_context *o,
const char *fmt, ...) {} const char *fmt, ...) {}
static inline void gk20a_debug_dump(struct gk20a *g) {} static inline void gk20a_debug_dump(struct gk20a *g) {}
static inline void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o) {} static inline void gk20a_debug_show_dump(struct gk20a *g,
struct nvgpu_debug_context *o) {}
static inline void gk20a_gr_debug_dump(struct gk20a *g) {} static inline void gk20a_gr_debug_dump(struct gk20a *g) {}
static inline void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink) {} static inline void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink) {}
static inline void gk20a_debug_deinit(struct gk20a *g) {} static inline void gk20a_debug_deinit(struct gk20a *g) {}

12
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -34,7 +34,7 @@ struct nvgpu_ce_app;
struct gk20a_ctxsw_trace; struct gk20a_ctxsw_trace;
struct nvgpu_mem_alloc_tracker; struct nvgpu_mem_alloc_tracker;
struct dbg_profiler_object_data; struct dbg_profiler_object_data;
struct gk20a_debug_output; struct nvgpu_debug_context;
struct nvgpu_clk_pll_debug_data; struct nvgpu_clk_pll_debug_data;
struct nvgpu_nvhost_dev; struct nvgpu_nvhost_dev;
struct nvgpu_netlist_vars; struct nvgpu_netlist_vars;
@@ -312,7 +312,7 @@ struct gpu_ops {
void (*set_pmm_register)(struct gk20a *g, u32 offset, u32 val, void (*set_pmm_register)(struct gk20a *g, u32 offset, u32 val,
u32 num_chiplets, u32 num_perfmons); u32 num_chiplets, u32 num_perfmons);
int (*dump_gr_regs)(struct gk20a *g, int (*dump_gr_regs)(struct gk20a *g,
struct gk20a_debug_output *o); struct nvgpu_debug_context *o);
int (*update_pc_sampling)(struct nvgpu_channel *ch, int (*update_pc_sampling)(struct nvgpu_channel *ch,
bool enable); bool enable);
void (*init_sm_dsm_reg_info)(void); void (*init_sm_dsm_reg_info)(void);
@@ -1107,7 +1107,7 @@ struct gpu_ops {
u32 *error_notifier); u32 *error_notifier);
u32 (*get_signature)(struct gk20a *g); u32 (*get_signature)(struct gk20a *g);
void (*dump_status)(struct gk20a *g, void (*dump_status)(struct gk20a *g,
struct gk20a_debug_output *o); struct nvgpu_debug_context *o);
u32 (*acquire_val)(u64 timeout); u32 (*acquire_val)(u64 timeout);
u32 (*read_data)(struct gk20a *g, u32 pbdma_id); u32 (*read_data)(struct gk20a *g, u32 pbdma_id);
void (*reset_header)(struct gk20a *g, u32 pbdma_id); void (*reset_header)(struct gk20a *g, u32 pbdma_id);
@@ -1189,7 +1189,7 @@ struct gpu_ops {
bool eng, bool pbdma); bool eng, bool pbdma);
int (*set_syncpt)(struct nvgpu_channel *ch); int (*set_syncpt)(struct nvgpu_channel *ch);
void (*debug_dump)(struct gk20a *g, void (*debug_dump)(struct gk20a *g,
struct gk20a_debug_output *o, struct nvgpu_debug_context *o,
struct nvgpu_channel_dump_info *info); struct nvgpu_channel_dump_info *info);
} channel; } channel;
struct { struct {
@@ -1236,7 +1236,7 @@ struct gpu_ops {
void (*read_engine_status_info) (struct gk20a *g, void (*read_engine_status_info) (struct gk20a *g,
u32 engine_id, struct nvgpu_engine_status_info *status); u32 engine_id, struct nvgpu_engine_status_info *status);
void (*dump_engine_status)(struct gk20a *g, void (*dump_engine_status)(struct gk20a *g,
struct gk20a_debug_output *o); struct nvgpu_debug_context *o);
} engine_status; } engine_status;
struct { struct {
void (*read_pbdma_status_info) (struct gk20a *g, void (*read_pbdma_status_info) (struct gk20a *g,
@@ -1526,7 +1526,7 @@ struct gpu_ops {
} mc; } mc;
struct { struct {
void (*show_dump)(struct gk20a *g, void (*show_dump)(struct gk20a *g,
struct gk20a_debug_output *o); struct nvgpu_debug_context *o);
} debug; } debug;
#ifdef NVGPU_DEBUGGER #ifdef NVGPU_DEBUGGER
struct { struct {

14
drivers/gpu/nvgpu/os/linux/debug.c
View File

@@ -52,7 +52,7 @@ static inline void gk20a_debug_write_to_seqfile(void *ctx, const char *str,
seq_write((struct seq_file *)ctx, str, len); seq_write((struct seq_file *)ctx, str, len);
} }
void gk20a_debug_output(struct gk20a_debug_output *o, const char *fmt, ...) void gk20a_debug_output(struct nvgpu_debug_context *o, const char *fmt, ...)
{ {
va_list args; va_list args;
int len; int len;
@@ -63,7 +63,7 @@ void gk20a_debug_output(struct gk20a_debug_output *o, const char *fmt, ...)
o->fn(o->ctx, o->buf, len); o->fn(o->ctx, o->buf, len);
} }
void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o) void gk20a_debug_show_dump(struct gk20a *g, struct nvgpu_debug_context *o)
{ {
nvgpu_channel_debug_dump_all(g, o); nvgpu_channel_debug_dump_all(g, o);
g->ops.pbdma.dump_status(g, o); g->ops.pbdma.dump_status(g, o);
@@ -71,7 +71,7 @@ void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
} }
static int gk20a_gr_dump_regs(struct gk20a *g, static int gk20a_gr_dump_regs(struct gk20a *g,
struct gk20a_debug_output *o) struct nvgpu_debug_context *o)
{ {
if (g->ops.gr.dump_gr_regs) if (g->ops.gr.dump_gr_regs)
nvgpu_pg_elpg_protected_call(g, g->ops.gr.dump_gr_regs(g, o)); nvgpu_pg_elpg_protected_call(g, g->ops.gr.dump_gr_regs(g, o));
@@ -81,7 +81,7 @@ static int gk20a_gr_dump_regs(struct gk20a *g,
void gk20a_gr_debug_dump(struct gk20a *g) void gk20a_gr_debug_dump(struct gk20a *g)
{ {
struct gk20a_debug_output o = { struct nvgpu_debug_context o = {
.fn = gk20a_debug_write_printk, .fn = gk20a_debug_write_printk,
.ctx = g, .ctx = g,
}; };
@@ -93,7 +93,7 @@ static int gk20a_gr_debug_show(struct seq_file *s, void *unused)
{ {
struct device *dev = s->private; struct device *dev = s->private;
struct gk20a *g = gk20a_get_platform(dev)->g; struct gk20a *g = gk20a_get_platform(dev)->g;
struct gk20a_debug_output o = { struct nvgpu_debug_context o = {
.fn = gk20a_debug_write_to_seqfile, .fn = gk20a_debug_write_to_seqfile,
.ctx = s, .ctx = s,
}; };
@@ -115,7 +115,7 @@ static int gk20a_gr_debug_show(struct seq_file *s, void *unused)
void gk20a_debug_dump(struct gk20a *g) void gk20a_debug_dump(struct gk20a *g)
{ {
struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g)); struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g));
struct gk20a_debug_output o = { struct nvgpu_debug_context o = {
.fn = gk20a_debug_write_printk, .fn = gk20a_debug_write_printk,
.ctx = g, .ctx = g,
}; };
@@ -131,7 +131,7 @@ void gk20a_debug_dump(struct gk20a *g)
static int gk20a_debug_show(struct seq_file *s, void *unused) static int gk20a_debug_show(struct seq_file *s, void *unused)
{ {
struct device *dev = s->private; struct device *dev = s->private;
struct gk20a_debug_output o = { struct nvgpu_debug_context o = {
.fn = gk20a_debug_write_to_seqfile, .fn = gk20a_debug_write_to_seqfile,
.ctx = s, .ctx = s,
}; };