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gpu: nvgpu: set FB/HSMMU debug mode

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Set NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL and NV_PFB_PRI_MMU_DEBUG_CTRL
in addition to NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL, in
NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE

Bug 2515097

Change-Id: I1763b43e79fac3edb68a35980683d58bfa89519f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115785
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-04-30 17:19:51 -07:00
committed by mobile promotions
parent adc2956568
commit 8057514a9f
13 changed files with 68 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
drivers/gpu/nvgpu/common/fifo/tsg.c
View File

@@ -893,13 +893,15 @@ int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_tsg *tsg,
struct gk20a *g;
int err = 0;
u32 tsg_refcnt;
u32 fb_refcnt;
if ((ch == NULL) || (tsg == NULL)) {
return -EINVAL;
}
g = ch->g;
if (g->ops.gr.set_mmu_debug_mode == NULL) {
if ((g->ops.fb.set_mmu_debug_mode == NULL) &&
(g->ops.gr.set_mmu_debug_mode == NULL)) {
return -ENOSYS;
}
@@ -909,26 +911,39 @@ int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_tsg *tsg,
return 0;
}
tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U;
fb_refcnt = g->mmu_debug_mode_refcnt + 1U;
} else {
if (!ch->mmu_debug_mode_enabled) {
/* already disabled for this channel */
return 0;
}
tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U;
fb_refcnt = g->mmu_debug_mode_refcnt - 1U;
}
/*
* enable GPC MMU debug mode if it was requested for at
* least one channel in the TSG
*/
err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U);
if (err != 0) {
nvgpu_err(g, "set mmu debug mode failed, err=%d", err);
return err;
if (g->ops.gr.set_mmu_debug_mode != NULL) {
/*
* enable GPC MMU debug mode if it was requested for at
* least one channel in the TSG
*/
err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U);
if (err != 0) {
nvgpu_err(g, "set mmu debug mode failed, err=%d", err);
return err;
}
}
if (g->ops.fb.set_mmu_debug_mode != NULL) {
/*
* enable FB/HS MMU debug mode if it was requested for
* at least one TSG
*/
g->ops.fb.set_mmu_debug_mode(g, fb_refcnt > 0U);
}
ch->mmu_debug_mode_enabled = enable;
tsg->mmu_debug_mode_refcnt = tsg_refcnt;
g->mmu_debug_mode_refcnt = fb_refcnt;
return err;
}

1
drivers/gpu/nvgpu/hal/fb/fb_gm20b.h
View File

@@ -51,6 +51,7 @@ int gm20b_fb_vpr_info_fetch(struct gk20a *g);
#ifdef CONFIG_NVGPU_DEBUGGER
bool gm20b_fb_debug_mode_enabled(struct gk20a *g);
void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable);
void gm20b_fb_set_mmu_debug_mode(struct gk20a *g, bool enable);
#endif
#endif

10
drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c
View File

@@ -50,7 +50,7 @@ bool gm20b_fb_debug_mode_enabled(struct gk20a *g)
fb_mmu_debug_ctrl_debug_enabled_v();
}
void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
void gm20b_fb_set_mmu_debug_mode(struct gk20a *g, bool enable)
{
u32 reg_val, fb_debug_ctrl;
@@ -62,11 +62,15 @@ void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
g->mmu_debug_ctrl = false;
}
reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
reg_val = nvgpu_readl(g, fb_mmu_debug_ctrl_r());
reg_val = set_field(reg_val,
fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
nvgpu_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
}
void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
{
gm20b_fb_set_mmu_debug_mode(g, enable);
g->ops.gr.set_debug_mode(g, enable);
}
#endif

24
drivers/gpu/nvgpu/hal/fb/fb_gv100.c
View File

@@ -182,3 +182,27 @@ size_t gv100_fb_get_vidmem_size(struct gk20a *g)
return bytes;
}
#endif
void gv100_fb_set_mmu_debug_mode(struct gk20a *g, bool enable)
{
u32 data, fb_ctrl, hsmmu_ctrl;
if (enable) {
fb_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
hsmmu_ctrl = fb_hsmmu_pri_mmu_debug_ctrl_debug_enabled_f();
g->mmu_debug_ctrl = true;
} else {
fb_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
hsmmu_ctrl = fb_hsmmu_pri_mmu_debug_ctrl_debug_disabled_f();
g->mmu_debug_ctrl = false;
}
data = nvgpu_readl(g, fb_mmu_debug_ctrl_r());
data = set_field(data, fb_mmu_debug_ctrl_debug_m(), fb_ctrl);
nvgpu_writel(g, fb_mmu_debug_ctrl_r(), data);
data = nvgpu_readl(g, fb_hsmmu_pri_mmu_debug_ctrl_r());
data = set_field(data,
fb_hsmmu_pri_mmu_debug_ctrl_debug_m(), hsmmu_ctrl);
nvgpu_writel(g, fb_hsmmu_pri_mmu_debug_ctrl_r(), data);
}

2
drivers/gpu/nvgpu/hal/fb/fb_gv100.h
View File

@@ -34,4 +34,6 @@ int gv100_fb_enable_nvlink(struct gk20a *g);
#ifdef CONFIG_NVGPU_DGPU
size_t gv100_fb_get_vidmem_size(struct gk20a *g);
#endif
void gv100_fb_set_mmu_debug_mode(struct gk20a *g, bool enable);
#endif /* NVGPU_FB_GV100_H */

1
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -582,6 +582,7 @@ static const struct gpu_ops gm20b_ops = {
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode,
.set_mmu_debug_mode = gm20b_fb_set_mmu_debug_mode,
#endif
.tlb_invalidate = gm20b_fb_tlb_invalidate,
.mem_unlock = NULL,

1
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -651,6 +651,7 @@ static const struct gpu_ops gp10b_ops = {
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode,
.set_mmu_debug_mode = gm20b_fb_set_mmu_debug_mode,
#endif
.tlb_invalidate = gm20b_fb_tlb_invalidate,
.mem_unlock = NULL,

1
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -783,6 +783,7 @@ static const struct gpu_ops gv11b_ops = {
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode,
.set_mmu_debug_mode = gm20b_fb_set_mmu_debug_mode,
#endif
.tlb_invalidate = gm20b_fb_tlb_invalidate,
.handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault,

1
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -800,6 +800,7 @@ static const struct gpu_ops tu104_ops = {
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode,
.set_mmu_debug_mode = gv100_fb_set_mmu_debug_mode,
#endif
.tlb_invalidate = fb_tu104_tlb_invalidate,
.handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault,

1
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
View File

@@ -435,6 +435,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = NULL,
.set_debug_mode = vgpu_mm_mmu_set_debug_mode,
.set_mmu_debug_mode = NULL,
#endif
.tlb_invalidate = vgpu_mm_tlb_invalidate,
},

1
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
View File

@@ -523,6 +523,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = NULL,
.set_debug_mode = vgpu_mm_mmu_set_debug_mode,
.set_mmu_debug_mode = NULL,
#endif
.tlb_invalidate = vgpu_mm_tlb_invalidate,
.write_mmu_fault_buffer_lo_hi =

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -993,6 +993,7 @@ struct gpu_ops {
#ifdef CONFIG_NVGPU_DEBUGGER
bool (*is_debug_mode_enabled)(struct gk20a *g);
void (*set_debug_mode)(struct gk20a *g, bool enable);
void (*set_mmu_debug_mode)(struct gk20a *g, bool enable);
#endif
int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb);
void (*handle_replayable_fault)(struct gk20a *g);
@@ -2125,6 +2126,7 @@ struct gk20a {
int profiler_reservation_count;
bool mmu_debug_ctrl;
u32 mmu_debug_mode_refcnt;
#endif /* CONFIG_NVGPU_DEBUGGER */
#ifdef CONFIG_NVGPU_FECS_TRACE

3
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
View File

@@ -1094,7 +1094,8 @@ static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode(
return -EINVAL;
}
if (g->ops.gr.set_mmu_debug_mode == NULL) {
if ((g->ops.fb.set_mmu_debug_mode == NULL) &&
(g->ops.gr.set_mmu_debug_mode == NULL)) {
return -ENOSYS;
}