gpu: nvgpu: vgpu: split vgpu.c into vgpu.c and vgpu_linux.c

vgpu.c will keep common code whil vgpu_linux.c is linux specific.

Jira EVLR-2364

Change-Id: Ice9782fa96c256f1b70320886d3720ab0db26244
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649943
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -178,7 +178,8 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
 	common/linux/vgpu/gm20b/vgpu_gr_gm20b.o \
 	common/linux/vgpu/sysfs_vgpu.o \
 	common/linux/vgpu/vgpu_ivc.o \
-	common/linux/vgpu/vgpu_ivm.o
+	common/linux/vgpu/vgpu_ivm.o \
+	common/linux/vgpu/vgpu_linux.o
 
 nvgpu-$(CONFIG_COMMON_CLK) += \
 	common/linux/clk.o

drivers/gpu/nvgpu/common/linux/module.c

@@ -42,7 +42,7 @@
 
 #include "platform_gk20a.h"
 #include "sysfs.h"
-#include "vgpu/vgpu.h"
+#include "vgpu/vgpu_linux.h"
 #include "scale.h"
 #include "pci.h"
 #include "module.h"

drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c

@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU CE2
  *
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -17,6 +17,7 @@
  */
 
 #include "vgpu.h"
+#include "gk20a/channel_gk20a.h"
 
 #include <nvgpu/bug.h>
 

drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c

@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU Clock Interface
  *
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,8 +16,11 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "gk20a/gk20a.h"
 #include "vgpu.h"
 #include "clk_vgpu.h"
+#include "ctrl/ctrlclk.h"
+#include "common/linux/platform_gk20a.h"
 
 static unsigned long
 vgpu_freq_table[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE];

drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c

@@ -25,6 +25,7 @@
 #include "common/linux/platform_gk20a.h"
 #include "common/linux/vgpu/vgpu.h"
 #include "common/linux/vgpu/css_vgpu.h"
+#include "common/linux/os_linux.h"
 
 static struct tegra_hv_ivm_cookie *css_cookie;
 

drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c

@@ -24,6 +24,7 @@
 #include <nvgpu/vgpu/tegra_vgpu.h>
 
 #include "gk20a/gk20a.h"
+#include "common/linux/os_linux.h"
 #include "vgpu.h"
 #include "fecs_trace_vgpu.h"
 

drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c

@@ -25,11 +25,14 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/barrier.h>
 #include <nvgpu/error_notifier.h>
+#include <nvgpu/vgpu/vgpu_ivc.h>
 
+#include "gk20a/gk20a.h"
 #include "vgpu.h"
 #include "fifo_vgpu.h"
 
 #include "common/linux/channel.h"
+#include "common/linux/os_linux.h"
 
 #include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>

drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c

@@ -24,6 +24,7 @@
 
 #include <nvgpu/bug.h>
 #include <nvgpu/dma.h>
+#include <nvgpu/vgpu/vgpu_ivc.h>
 
 int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g)
 {

drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c

@@ -23,9 +23,11 @@
 #include <nvgpu/dma.h>
 #include <nvgpu/error_notifier.h>
 #include <nvgpu/dma.h>
+#include <nvgpu/vgpu/vgpu_ivc.h>
 
 #include "vgpu.h"
 #include "gr_vgpu.h"
+#include "gk20a/gk20a.h"
 #include "gk20a/dbg_gpu_gk20a.h"
 #include "gk20a/channel_gk20a.h"
 #include "gk20a/tsg_gk20a.h"

drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h

@@ -26,6 +26,7 @@ struct gr_zcull_info;
 struct zbc_entry;
 struct zbc_query_params;
 struct dbg_session_gk20a;
+struct tsg_gk20a;
 
 void vgpu_gr_detect_sm_arch(struct gk20a *g);
 void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg);

drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c

@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU L2
  *
- * Copyright (c) 2014-2017 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,6 +16,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "gk20a/gk20a.h"
 #include "vgpu.h"
 #include "ltc_vgpu.h"
 

drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c

@@ -31,6 +31,7 @@
 
 #include "vgpu.h"
 #include "mm_vgpu.h"
+#include "gk20a/gk20a.h"
 #include "gk20a/mm_gk20a.h"
 #include "gm20b/mm_gm20b.h"
 

drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -17,6 +17,11 @@
 #ifndef _MM_VGPU_H_
 #define _MM_VGPU_H_
 
+struct nvgpu_mem;
+struct channel_gk20a;
+struct vm_gk20a_mapping_batch;
+struct gk20a_as_share;
+
 void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm,
 				u64 vaddr,
 				u64 size,

drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -17,6 +17,7 @@
 #include <linux/device.h>
 
 #include "vgpu.h"
+#include "common/linux/platform_gk20a.h"
 
 static ssize_t vgpu_load_show(struct device *dev,
 			      struct device_attribute *attr,

drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c

@@ -1,6 +1,4 @@
 /*
- * Virtualized GPU
- *
  * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -16,40 +14,15 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/mm.h>
-#include <linux/dma-mapping.h>
-#include <linux/pm_runtime.h>
-#include <linux/pm_qos.h>
-#include <linux/platform_device.h>
-#include <soc/tegra/chip-id.h>
-#include <uapi/linux/nvgpu.h>
-
-#include <nvgpu/kmem.h>
-#include <nvgpu/bug.h>
 #include <nvgpu/enabled.h>
-#include <nvgpu/debug.h>
 #include <nvgpu/bus.h>
-#include <nvgpu/soc.h>
+#include <nvgpu/vgpu/vgpu_ivc.h>
-#include <nvgpu/ctxsw_trace.h>
-#include <nvgpu/defaults.h>
 
+#include "gk20a/gk20a.h"
 #include "vgpu.h"
 #include "fecs_trace_vgpu.h"
-#include "clk_vgpu.h"
-#include "gk20a/tsg_gk20a.h"
-#include "gk20a/channel_gk20a.h"
-#include "gk20a/regops_gk20a.h"
-#include "gm20b/hal_gm20b.h"
 
-#include "common/linux/module.h"
+int vgpu_comm_init(struct gk20a *g)
-#include "common/linux/os_linux.h"
-#include "common/linux/ioctl.h"
-#include "common/linux/scale.h"
-#include "common/linux/driver_common.h"
-
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
-
-static inline int vgpu_comm_init(struct gk20a *g)
 {
 	size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
 
@@ -57,7 +30,7 @@ static inline int vgpu_comm_init(struct gk20a *g)
 				ARRAY_SIZE(queue_sizes));
 }
 
-static inline void vgpu_comm_deinit(void)
+void vgpu_comm_deinit(void)
 {
 	size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
 
@@ -83,7 +56,7 @@ int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
 	return err;
 }
 
-static u64 vgpu_connect(void)
+u64 vgpu_connect(void)
 {
 	struct tegra_vgpu_cmd_msg msg;
 	struct tegra_vgpu_connect_params *p = &msg.params.connect;
@@ -125,7 +98,7 @@ static void vgpu_handle_channel_event(struct gk20a *g,
 	}
 
 	if (info->id >= g->fifo.num_channels ||
-		info->event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX) {
+		info->event_id >= TEGRA_VGPU_CHANNEL_EVENT_ID_MAX) {
 		nvgpu_err(g, "invalid channel event");
 		return;
 	}
@@ -135,9 +108,7 @@ static void vgpu_handle_channel_event(struct gk20a *g,
 	gk20a_tsg_event_id_post_event(tsg, info->event_id);
 }
 
-
+int vgpu_intr_thread(void *dev_id)
-
-static int vgpu_intr_thread(void *dev_id)
 {
 	struct gk20a *g = dev_id;
 	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
@@ -201,11 +172,9 @@ static int vgpu_intr_thread(void *dev_id)
 	return 0;
 }
 
-static void vgpu_remove_support(struct gk20a *g)
+void vgpu_remove_support_common(struct gk20a *g)
 {
-	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
-	struct vgpu_priv_data *priv =
-		vgpu_get_priv_data_from_dev(dev_from_gk20a(g));
 	struct tegra_vgpu_intr_msg msg;
 	int err;
 
@@ -229,104 +198,9 @@ static void vgpu_remove_support(struct gk20a *g)
 				&msg, sizeof(msg));
 	WARN_ON(err);
 	nvgpu_thread_stop(&priv->intr_handler);
-
-	/* free mappings to registers, etc*/
-
-	if (l->bar1) {
-		iounmap(l->bar1);
-		l->bar1 = NULL;
-	}
 }
 
-static void vgpu_init_vars(struct gk20a *g, struct gk20a_platform *platform)
+void vgpu_detect_chip(struct gk20a *g)
-{
-	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
-
-	nvgpu_mutex_init(&g->poweron_lock);
-	nvgpu_mutex_init(&g->poweroff_lock);
-	l->regs_saved = l->regs;
-	l->bar1_saved = l->bar1;
-
-	nvgpu_init_list_node(&g->pending_sema_waits);
-	nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock);
-
-	g->aggressive_sync_destroy = platform->aggressive_sync_destroy;
-	g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh;
-	g->has_syncpoints = platform->has_syncpoints;
-	g->ptimer_src_freq = platform->ptimer_src_freq;
-	g->can_railgate = platform->can_railgate_init;
-	g->railgate_delay = platform->railgate_delay_init;
-
-	__nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES,
-			    platform->unify_address_spaces);
-}
-
-static int vgpu_init_support(struct platform_device *pdev)
-{
-	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	struct gk20a *g = get_gk20a(&pdev->dev);
-	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
-	void __iomem *regs;
-	int err = 0;
-
-	if (!r) {
-		nvgpu_err(g, "failed to get gk20a bar1");
-		err = -ENXIO;
-		goto fail;
-	}
-
-	if (r->name && !strcmp(r->name, "/vgpu")) {
-		regs = devm_ioremap_resource(&pdev->dev, r);
-		if (IS_ERR(regs)) {
-			nvgpu_err(g, "failed to remap gk20a bar1");
-			err = PTR_ERR(regs);
-			goto fail;
-		}
-		l->bar1 = regs;
-		l->bar1_mem = r;
-	}
-
-	nvgpu_mutex_init(&g->dbg_sessions_lock);
-	nvgpu_mutex_init(&g->client_lock);
-
-	nvgpu_init_list_node(&g->profiler_objects);
-
-	g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K);
-	if (!g->dbg_regops_tmp_buf) {
-		nvgpu_err(g, "couldn't allocate regops tmp buf");
-		return -ENOMEM;
-	}
-	g->dbg_regops_tmp_buf_ops =
-		SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]);
-
-	g->remove_support = vgpu_remove_support;
-	return 0;
-
- fail:
-	vgpu_remove_support(g);
-	return err;
-}
-
-int vgpu_pm_prepare_poweroff(struct device *dev)
-{
-	struct gk20a *g = get_gk20a(dev);
-	int ret = 0;
-
-	gk20a_dbg_fn("");
-
-	if (!g->power_on)
-		return 0;
-
-	ret = gk20a_channel_suspend(g);
-	if (ret)
-		return ret;
-
-	g->power_on = false;
-
-	return ret;
-}
-
-static void vgpu_detect_chip(struct gk20a *g)
 {
 	struct nvgpu_gpu_params *p = &g->params;
 	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
@@ -417,7 +291,7 @@ int vgpu_get_timestamps_zipper(struct gk20a *g,
 	return err;
 }
 
-static int vgpu_init_hal(struct gk20a *g)
+int vgpu_init_hal(struct gk20a *g)
 {
 	u32 ver = g->params.gpu_arch + g->params.gpu_impl;
 	int err;
@@ -439,158 +313,7 @@ static int vgpu_init_hal(struct gk20a *g)
 	return err;
 }
 
-int vgpu_pm_finalize_poweron(struct device *dev)
+int vgpu_get_constants(struct gk20a *g)
-{
-	struct gk20a *g = get_gk20a(dev);
-	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
-	int err;
-
-	gk20a_dbg_fn("");
-
-	if (g->power_on)
-		return 0;
-
-	g->power_on = true;
-
-	vgpu_detect_chip(g);
-	err = vgpu_init_hal(g);
-	if (err)
-		goto done;
-
-	if (g->ops.ltc.init_fs_state)
-		g->ops.ltc.init_fs_state(g);
-
-	err = vgpu_init_mm_support(g);
-	if (err) {
-		nvgpu_err(g, "failed to init gk20a mm");
-		goto done;
-	}
-
-	err = vgpu_init_fifo_support(g);
-	if (err) {
-		nvgpu_err(g, "failed to init gk20a fifo");
-		goto done;
-	}
-
-	err = vgpu_init_gr_support(g);
-	if (err) {
-		nvgpu_err(g, "failed to init gk20a gr");
-		goto done;
-	}
-
-	err = g->ops.chip_init_gpu_characteristics(g);
-	if (err) {
-		nvgpu_err(g, "failed to init gk20a gpu characteristics");
-		goto done;
-	}
-
-	err = nvgpu_finalize_poweron_linux(l);
-	if (err)
-		goto done;
-
-#ifdef CONFIG_GK20A_CTXSW_TRACE
-	gk20a_ctxsw_trace_init(g);
-#endif
-	gk20a_sched_ctrl_init(g);
-	gk20a_channel_resume(g);
-
-	g->sw_ready = true;
-
-done:
-	return err;
-}
-
-static int vgpu_qos_notify(struct notifier_block *nb,
-			  unsigned long n, void *data)
-{
-	struct gk20a_scale_profile *profile =
-			container_of(nb, struct gk20a_scale_profile,
-			qos_notify_block);
-	struct gk20a *g = get_gk20a(profile->dev);
-	u32 max_freq;
-	int err;
-
-	gk20a_dbg_fn("");
-
-	max_freq = (u32)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS);
-	err = vgpu_clk_cap_rate(profile->dev, max_freq);
-	if (err)
-		nvgpu_err(g, "%s failed, err=%d", __func__, err);
-
-	return NOTIFY_OK; /* need notify call further */
-}
-
-static int vgpu_pm_qos_init(struct device *dev)
-{
-	struct gk20a *g = get_gk20a(dev);
-	struct gk20a_scale_profile *profile = g->scale_profile;
-
-	if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) {
-		if (!profile)
-			return -EINVAL;
-	} else {
-		profile = nvgpu_kzalloc(g, sizeof(*profile));
-		if (!profile)
-			return -ENOMEM;
-		g->scale_profile = profile;
-	}
-
-	profile->dev = dev;
-	profile->qos_notify_block.notifier_call = vgpu_qos_notify;
-	pm_qos_add_max_notifier(PM_QOS_GPU_FREQ_BOUNDS,
-				&profile->qos_notify_block);
-	return 0;
-}
-
-static void vgpu_pm_qos_remove(struct device *dev)
-{
-	struct gk20a *g = get_gk20a(dev);
-
-	pm_qos_remove_max_notifier(PM_QOS_GPU_FREQ_BOUNDS,
-				&g->scale_profile->qos_notify_block);
-	nvgpu_kfree(g, g->scale_profile);
-	g->scale_profile = NULL;
-}
-
-static int vgpu_pm_init(struct device *dev)
-{
-	struct gk20a *g = get_gk20a(dev);
-	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
-	unsigned long *freqs;
-	int num_freqs;
-	int err = 0;
-
-	gk20a_dbg_fn("");
-
-	if (nvgpu_platform_is_simulation(g))
-		return 0;
-
-	__pm_runtime_disable(dev, false);
-
-	if (IS_ENABLED(CONFIG_GK20A_DEVFREQ))
-		gk20a_scale_init(dev);
-
-	if (l->devfreq) {
-		/* set min/max frequency based on frequency table */
-		err = vgpu_clk_get_freqs(dev, &freqs, &num_freqs);
-		if (err)
-			return err;
-
-		if (num_freqs < 1)
-			return -EINVAL;
-
-		l->devfreq->min_freq = freqs[0];
-		l->devfreq->max_freq = freqs[num_freqs - 1];
-	}
-
-	err = vgpu_pm_qos_init(dev);
-	if (err)
-		return err;
-
-	return err;
-}
-
-static int vgpu_get_constants(struct gk20a *g)
 {
 	struct tegra_vgpu_cmd_msg msg = {};
 	struct tegra_vgpu_constants_params *p = &msg.params.constants;
@@ -619,153 +342,3 @@ static int vgpu_get_constants(struct gk20a *g)
 	priv->constants = *p;
 	return 0;
 }
-
-int vgpu_probe(struct platform_device *pdev)
-{
-	struct nvgpu_os_linux *l;
-	struct gk20a *gk20a;
-	int err;
-	struct device *dev = &pdev->dev;
-	struct gk20a_platform *platform = gk20a_get_platform(dev);
-	struct vgpu_priv_data *priv;
-
-	if (!platform) {
-		dev_err(dev, "no platform data\n");
-		return -ENODATA;
-	}
-
-	gk20a_dbg_fn("");
-
-	l = kzalloc(sizeof(*l), GFP_KERNEL);
-	if (!l) {
-		dev_err(dev, "couldn't allocate gk20a support");
-		return -ENOMEM;
-	}
-	gk20a = &l->g;
-	nvgpu_init_gk20a(gk20a);
-
-	nvgpu_kmem_init(gk20a);
-
-	err = nvgpu_init_enabled_flags(gk20a);
-	if (err) {
-		kfree(gk20a);
-		return err;
-	}
-
-	l->dev = dev;
-	if (tegra_platform_is_vdk())
-		__nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true);
-
-	gk20a->is_virtual = true;
-
-	priv = nvgpu_kzalloc(gk20a, sizeof(*priv));
-	if (!priv) {
-		kfree(gk20a);
-		return -ENOMEM;
-	}
-
-	platform->g = gk20a;
-	platform->vgpu_priv = priv;
-
-	err = gk20a_user_init(dev, INTERFACE_NAME, &nvgpu_class);
-	if (err)
-		return err;
-
-	vgpu_init_support(pdev);
-
-	vgpu_init_vars(gk20a, platform);
-
-	init_rwsem(&l->busy_lock);
-
-	nvgpu_spinlock_init(&gk20a->mc_enable_lock);
-
-	gk20a->ch_wdt_timeout_ms = platform->ch_wdt_timeout_ms;
-
-	/* Initialize the platform interface. */
-	err = platform->probe(dev);
-	if (err) {
-		if (err == -EPROBE_DEFER)
-			nvgpu_info(gk20a, "platform probe failed");
-		else
-			nvgpu_err(gk20a, "platform probe failed");
-		return err;
-	}
-
-	if (platform->late_probe) {
-		err = platform->late_probe(dev);
-		if (err) {
-			nvgpu_err(gk20a, "late probe failed");
-			return err;
-		}
-	}
-
-	err = vgpu_comm_init(gk20a);
-	if (err) {
-		nvgpu_err(gk20a, "failed to init comm interface");
-		return -ENOSYS;
-	}
-
-	priv->virt_handle = vgpu_connect();
-	if (!priv->virt_handle) {
-		nvgpu_err(gk20a, "failed to connect to server node");
-		vgpu_comm_deinit();
-		return -ENOSYS;
-	}
-
-	err = vgpu_get_constants(gk20a);
-	if (err) {
-		vgpu_comm_deinit();
-		return err;
-	}
-
-	err = vgpu_pm_init(dev);
-	if (err) {
-		nvgpu_err(gk20a, "pm init failed");
-		return err;
-	}
-
-	err = nvgpu_thread_create(&priv->intr_handler, gk20a,
-			vgpu_intr_thread, "gk20a");
-	if (err)
-		return err;
-
-	gk20a_debug_init(gk20a, "gpu.0");
-
-	/* Set DMA parameters to allow larger sgt lists */
-	dev->dma_parms = &l->dma_parms;
-	dma_set_max_seg_size(dev, UINT_MAX);
-
-	gk20a->gr_idle_timeout_default = NVGPU_DEFAULT_GR_IDLE_TIMEOUT;
-	gk20a->timeouts_enabled = true;
-
-	vgpu_create_sysfs(dev);
-	gk20a_init_gr(gk20a);
-
-	gk20a_dbg_info("total ram pages : %lu", totalram_pages);
-	gk20a->gr.max_comptag_mem = totalram_pages
-				 >> (10 - (PAGE_SHIFT - 10));
-
-	nvgpu_ref_init(&gk20a->refcount);
-
-	return 0;
-}
-
-int vgpu_remove(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct gk20a *g = get_gk20a(dev);
-	gk20a_dbg_fn("");
-
-	vgpu_pm_qos_remove(dev);
-	if (g->remove_support)
-		g->remove_support(g);
-
-	vgpu_comm_deinit();
-	gk20a_sched_ctrl_cleanup(g);
-	gk20a_user_deinit(dev, &nvgpu_class);
-	vgpu_remove_sysfs(dev);
-	gk20a_get_platform(dev)->g = NULL;
-	gk20a_put(g);
-
-	return 0;
-}

drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h

@@ -1,6 +1,4 @@
 /*
- * Virtualized GPU Interfaces
- *
  * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -16,24 +14,23 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef _VIRT_H_
+#ifndef __VGPU_COMMON_H__
-#define _VIRT_H_
+#define __VGPU_COMMON_H__
+
+#include <nvgpu/types.h>
+#include <nvgpu/thread.h>
+#include <nvgpu/log.h>
+#include <nvgpu/vgpu/tegra_vgpu.h>
 
 struct device;
 struct tegra_vgpu_gr_intr_info;
 struct tegra_vgpu_fifo_intr_info;
 struct tegra_vgpu_cmd_msg;
-struct gk20a_platform;
 struct nvgpu_mem;
-
+struct gk20a;
-#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
+struct vm_gk20a;
-#include <nvgpu/vgpu/vgpu_ivc.h>
+struct nvgpu_gr_ctx;
-#include <nvgpu/vgpu/tegra_vgpu.h>
+struct nvgpu_cpu_time_correlation_sample;
-#include <nvgpu/thread.h>
-
-#include "gk20a/gk20a.h"
-#include "common/linux/platform_gk20a.h"
-#include "common/linux/os_linux.h"
 
 struct vgpu_priv_data {
 	u64 virt_handle;
@@ -41,18 +38,7 @@ struct vgpu_priv_data {
 	struct tegra_vgpu_constants_params constants;
 };
 
-static inline
+struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g);
-struct vgpu_priv_data *vgpu_get_priv_data_from_dev(struct device *dev)
-{
-	struct gk20a_platform *plat = gk20a_get_platform(dev);
-
-	return (struct vgpu_priv_data *)plat->vgpu_priv;
-}
-
-static inline struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g)
-{
-	return vgpu_get_priv_data_from_dev(dev_from_gk20a(g));
-}
 
 static inline u64 vgpu_get_handle(struct gk20a *g)
 {
@@ -66,10 +52,22 @@ static inline u64 vgpu_get_handle(struct gk20a *g)
 	return priv->virt_handle;
 }
 
-int vgpu_pm_prepare_poweroff(struct device *dev);
+int vgpu_comm_init(struct gk20a *g);
-int vgpu_pm_finalize_poweron(struct device *dev);
+void vgpu_comm_deinit(void);
-int vgpu_probe(struct platform_device *dev);
+int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
-int vgpu_remove(struct platform_device *dev);
+		size_t size_out);
+u64 vgpu_connect(void);
+int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
+int vgpu_intr_thread(void *dev_id);
+void vgpu_remove_support_common(struct gk20a *g);
+void vgpu_detect_chip(struct gk20a *g);
+int vgpu_init_gpu_characteristics(struct gk20a *g);
+int vgpu_read_ptimer(struct gk20a *g, u64 *value);
+int vgpu_get_timestamps_zipper(struct gk20a *g,
+		u32 source_id, u32 count,
+		struct nvgpu_cpu_time_correlation_sample *samples);
+int vgpu_init_hal(struct gk20a *g);
+int vgpu_get_constants(struct gk20a *g);
 u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem);
 int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
 int vgpu_gr_nonstall_isr(struct gk20a *g,
@@ -94,90 +92,12 @@ int vgpu_init_mm_support(struct gk20a *g);
 int vgpu_init_gr_support(struct gk20a *g);
 int vgpu_init_fifo_support(struct gk20a *g);
 
-int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
-int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
-		size_t size_out);
-
 int vgpu_gp10b_init_hal(struct gk20a *g);
 int vgpu_gv11b_init_hal(struct gk20a *g);
 
-int vgpu_init_gpu_characteristics(struct gk20a *g);
-
-void vgpu_create_sysfs(struct device *dev);
-void vgpu_remove_sysfs(struct device *dev);
 int vgpu_read_ptimer(struct gk20a *g, u64 *value);
 int vgpu_get_timestamps_zipper(struct gk20a *g,
 		u32 source_id, u32 count,
 		struct nvgpu_cpu_time_correlation_sample *samples);
-#else
-static inline int vgpu_pm_prepare_poweroff(struct device *dev)
-{
-	return -ENOSYS;
-}
-static inline int vgpu_pm_finalize_poweron(struct device *dev)
-{
-	return -ENOSYS;
-}
-static inline int vgpu_probe(struct platform_device *dev)
-{
-	return -ENOSYS;
-}
-static inline int vgpu_remove(struct platform_device *dev)
-{
-	return -ENOSYS;
-}
-static inline u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem)
-{
-	return 0;
-}
-static inline int vgpu_gr_isr(struct gk20a *g,
-			struct tegra_vgpu_gr_intr_info *info)
-{
-	return 0;
-}
-static inline int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
-				struct nvgpu_gr_ctx *gr_ctx,
-				struct vm_gk20a *vm,
-				u32 class,
-				u32 flags)
-{
-	return -ENOSYS;
-}
-static inline void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
-				struct nvgpu_gr_ctx *gr_ctx)
-{
-}
-static inline int vgpu_gr_init_ctx_state(struct gk20a *g)
-{
-	return -ENOSYS;
-}
-static inline int vgpu_fifo_isr(struct gk20a *g,
-			struct tegra_vgpu_fifo_intr_info *info)
-{
-	return 0;
-}
-static inline int vgpu_init_mm_support(struct gk20a *g)
-{
-	return -ENOSYS;
-}
-static inline int vgpu_init_gr_support(struct gk20a *g)
-{
-	return -ENOSYS;
-}
-static inline int vgpu_init_fifo_support(struct gk20a *g)
-{
-	return -ENOSYS;
-}
-
-static inline int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value)
-{
-	return -ENOSYS;
-}
-static inline int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
-		size_t size_out)
-{
-	return -ENOSYS;
-}
-#endif
 
 #endif

drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.c

@@ -0,0 +1,463 @@
+/*
+ * Virtualized GPU for Linux
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/mm.h>
+#include <linux/dma-mapping.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_qos.h>
+#include <linux/platform_device.h>
+#include <soc/tegra/chip-id.h>
+#include <uapi/linux/nvgpu.h>
+
+#include <nvgpu/kmem.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/debug.h>
+#include <nvgpu/bus.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/ctxsw_trace.h>
+#include <nvgpu/defaults.h>
+
+#include "vgpu.h"
+#include "vgpu_linux.h"
+#include "fecs_trace_vgpu.h"
+#include "clk_vgpu.h"
+#include "gk20a/tsg_gk20a.h"
+#include "gk20a/channel_gk20a.h"
+#include "gk20a/regops_gk20a.h"
+#include "gm20b/hal_gm20b.h"
+
+#include "common/linux/module.h"
+#include "common/linux/os_linux.h"
+#include "common/linux/ioctl.h"
+#include "common/linux/scale.h"
+#include "common/linux/driver_common.h"
+#include "common/linux/platform_gk20a.h"
+
+#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
+
+struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g)
+{
+	struct gk20a_platform *plat = gk20a_get_platform(dev_from_gk20a(g));
+
+	return (struct vgpu_priv_data *)plat->vgpu_priv;
+}
+
+static void vgpu_remove_support(struct gk20a *g)
+{
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+
+	vgpu_remove_support_common(g);
+
+	/* free mappings to registers, etc*/
+
+	if (l->bar1) {
+		iounmap(l->bar1);
+		l->bar1 = NULL;
+	}
+}
+
+static void vgpu_init_vars(struct gk20a *g, struct gk20a_platform *platform)
+{
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+
+	nvgpu_mutex_init(&g->poweron_lock);
+	nvgpu_mutex_init(&g->poweroff_lock);
+	l->regs_saved = l->regs;
+	l->bar1_saved = l->bar1;
+
+	nvgpu_init_list_node(&g->pending_sema_waits);
+	nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock);
+
+	g->aggressive_sync_destroy = platform->aggressive_sync_destroy;
+	g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh;
+	g->has_syncpoints = platform->has_syncpoints;
+	g->ptimer_src_freq = platform->ptimer_src_freq;
+	g->can_railgate = platform->can_railgate_init;
+	g->railgate_delay = platform->railgate_delay_init;
+
+	__nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES,
+			    platform->unify_address_spaces);
+}
+
+static int vgpu_init_support(struct platform_device *pdev)
+{
+	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	struct gk20a *g = get_gk20a(&pdev->dev);
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+	void __iomem *regs;
+	int err = 0;
+
+	if (!r) {
+		nvgpu_err(g, "failed to get gk20a bar1");
+		err = -ENXIO;
+		goto fail;
+	}
+
+	if (r->name && !strcmp(r->name, "/vgpu")) {
+		regs = devm_ioremap_resource(&pdev->dev, r);
+		if (IS_ERR(regs)) {
+			nvgpu_err(g, "failed to remap gk20a bar1");
+			err = PTR_ERR(regs);
+			goto fail;
+		}
+		l->bar1 = regs;
+		l->bar1_mem = r;
+	}
+
+	nvgpu_mutex_init(&g->dbg_sessions_lock);
+	nvgpu_mutex_init(&g->client_lock);
+
+	nvgpu_init_list_node(&g->profiler_objects);
+
+	g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K);
+	if (!g->dbg_regops_tmp_buf) {
+		nvgpu_err(g, "couldn't allocate regops tmp buf");
+		return -ENOMEM;
+	}
+	g->dbg_regops_tmp_buf_ops =
+		SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]);
+
+	g->remove_support = vgpu_remove_support;
+	return 0;
+
+ fail:
+	vgpu_remove_support(g);
+	return err;
+}
+
+int vgpu_pm_prepare_poweroff(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	int ret = 0;
+
+	gk20a_dbg_fn("");
+
+	if (!g->power_on)
+		return 0;
+
+	ret = gk20a_channel_suspend(g);
+	if (ret)
+		return ret;
+
+	g->power_on = false;
+
+	return ret;
+}
+
+int vgpu_pm_finalize_poweron(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+	int err;
+
+	gk20a_dbg_fn("");
+
+	if (g->power_on)
+		return 0;
+
+	g->power_on = true;
+
+	vgpu_detect_chip(g);
+	err = vgpu_init_hal(g);
+	if (err)
+		goto done;
+
+	if (g->ops.ltc.init_fs_state)
+		g->ops.ltc.init_fs_state(g);
+
+	err = vgpu_init_mm_support(g);
+	if (err) {
+		nvgpu_err(g, "failed to init gk20a mm");
+		goto done;
+	}
+
+	err = vgpu_init_fifo_support(g);
+	if (err) {
+		nvgpu_err(g, "failed to init gk20a fifo");
+		goto done;
+	}
+
+	err = vgpu_init_gr_support(g);
+	if (err) {
+		nvgpu_err(g, "failed to init gk20a gr");
+		goto done;
+	}
+
+	err = g->ops.chip_init_gpu_characteristics(g);
+	if (err) {
+		nvgpu_err(g, "failed to init gk20a gpu characteristics");
+		goto done;
+	}
+
+	err = nvgpu_finalize_poweron_linux(l);
+	if (err)
+		goto done;
+
+#ifdef CONFIG_GK20A_CTXSW_TRACE
+	gk20a_ctxsw_trace_init(g);
+#endif
+	gk20a_sched_ctrl_init(g);
+	gk20a_channel_resume(g);
+
+	g->sw_ready = true;
+
+done:
+	return err;
+}
+
+static int vgpu_qos_notify(struct notifier_block *nb,
+			  unsigned long n, void *data)
+{
+	struct gk20a_scale_profile *profile =
+			container_of(nb, struct gk20a_scale_profile,
+			qos_notify_block);
+	struct gk20a *g = get_gk20a(profile->dev);
+	u32 max_freq;
+	int err;
+
+	gk20a_dbg_fn("");
+
+	max_freq = (u32)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS);
+	err = vgpu_clk_cap_rate(profile->dev, max_freq);
+	if (err)
+		nvgpu_err(g, "%s failed, err=%d", __func__, err);
+
+	return NOTIFY_OK; /* need notify call further */
+}
+
+static int vgpu_pm_qos_init(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct gk20a_scale_profile *profile = g->scale_profile;
+
+	if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) {
+		if (!profile)
+			return -EINVAL;
+	} else {
+		profile = nvgpu_kzalloc(g, sizeof(*profile));
+		if (!profile)
+			return -ENOMEM;
+		g->scale_profile = profile;
+	}
+
+	profile->dev = dev;
+	profile->qos_notify_block.notifier_call = vgpu_qos_notify;
+	pm_qos_add_max_notifier(PM_QOS_GPU_FREQ_BOUNDS,
+				&profile->qos_notify_block);
+	return 0;
+}
+
+static void vgpu_pm_qos_remove(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+
+	pm_qos_remove_max_notifier(PM_QOS_GPU_FREQ_BOUNDS,
+				&g->scale_profile->qos_notify_block);
+	nvgpu_kfree(g, g->scale_profile);
+	g->scale_profile = NULL;
+}
+
+static int vgpu_pm_init(struct device *dev)
+{
+	struct gk20a *g = get_gk20a(dev);
+	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+	unsigned long *freqs;
+	int num_freqs;
+	int err = 0;
+
+	gk20a_dbg_fn("");
+
+	if (nvgpu_platform_is_simulation(g))
+		return 0;
+
+	__pm_runtime_disable(dev, false);
+
+	if (IS_ENABLED(CONFIG_GK20A_DEVFREQ))
+		gk20a_scale_init(dev);
+
+	if (l->devfreq) {
+		/* set min/max frequency based on frequency table */
+		err = vgpu_clk_get_freqs(dev, &freqs, &num_freqs);
+		if (err)
+			return err;
+
+		if (num_freqs < 1)
+			return -EINVAL;
+
+		l->devfreq->min_freq = freqs[0];
+		l->devfreq->max_freq = freqs[num_freqs - 1];
+	}
+
+	err = vgpu_pm_qos_init(dev);
+	if (err)
+		return err;
+
+	return err;
+}
+
+int vgpu_probe(struct platform_device *pdev)
+{
+	struct nvgpu_os_linux *l;
+	struct gk20a *gk20a;
+	int err;
+	struct device *dev = &pdev->dev;
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct vgpu_priv_data *priv;
+
+	if (!platform) {
+		dev_err(dev, "no platform data\n");
+		return -ENODATA;
+	}
+
+	gk20a_dbg_fn("");
+
+	l = kzalloc(sizeof(*l), GFP_KERNEL);
+	if (!l) {
+		dev_err(dev, "couldn't allocate gk20a support");
+		return -ENOMEM;
+	}
+	gk20a = &l->g;
+	nvgpu_init_gk20a(gk20a);
+
+	nvgpu_kmem_init(gk20a);
+
+	err = nvgpu_init_enabled_flags(gk20a);
+	if (err) {
+		kfree(gk20a);
+		return err;
+	}
+
+	l->dev = dev;
+	if (tegra_platform_is_vdk())
+		__nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true);
+
+	gk20a->is_virtual = true;
+
+	priv = nvgpu_kzalloc(gk20a, sizeof(*priv));
+	if (!priv) {
+		kfree(gk20a);
+		return -ENOMEM;
+	}
+
+	platform->g = gk20a;
+	platform->vgpu_priv = priv;
+
+	err = gk20a_user_init(dev, INTERFACE_NAME, &nvgpu_class);
+	if (err)
+		return err;
+
+	vgpu_init_support(pdev);
+
+	vgpu_init_vars(gk20a, platform);
+
+	init_rwsem(&l->busy_lock);
+
+	nvgpu_spinlock_init(&gk20a->mc_enable_lock);
+
+	gk20a->ch_wdt_timeout_ms = platform->ch_wdt_timeout_ms;
+
+	/* Initialize the platform interface. */
+	err = platform->probe(dev);
+	if (err) {
+		if (err == -EPROBE_DEFER)
+			nvgpu_info(gk20a, "platform probe failed");
+		else
+			nvgpu_err(gk20a, "platform probe failed");
+		return err;
+	}
+
+	if (platform->late_probe) {
+		err = platform->late_probe(dev);
+		if (err) {
+			nvgpu_err(gk20a, "late probe failed");
+			return err;
+		}
+	}
+
+	err = vgpu_comm_init(gk20a);
+	if (err) {
+		nvgpu_err(gk20a, "failed to init comm interface");
+		return -ENOSYS;
+	}
+
+	priv->virt_handle = vgpu_connect();
+	if (!priv->virt_handle) {
+		nvgpu_err(gk20a, "failed to connect to server node");
+		vgpu_comm_deinit();
+		return -ENOSYS;
+	}
+
+	err = vgpu_get_constants(gk20a);
+	if (err) {
+		vgpu_comm_deinit();
+		return err;
+	}
+
+	err = vgpu_pm_init(dev);
+	if (err) {
+		nvgpu_err(gk20a, "pm init failed");
+		return err;
+	}
+
+	err = nvgpu_thread_create(&priv->intr_handler, gk20a,
+			vgpu_intr_thread, "gk20a");
+	if (err)
+		return err;
+
+	gk20a_debug_init(gk20a, "gpu.0");
+
+	/* Set DMA parameters to allow larger sgt lists */
+	dev->dma_parms = &l->dma_parms;
+	dma_set_max_seg_size(dev, UINT_MAX);
+
+	gk20a->gr_idle_timeout_default = NVGPU_DEFAULT_GR_IDLE_TIMEOUT;
+	gk20a->timeouts_enabled = true;
+
+	vgpu_create_sysfs(dev);
+	gk20a_init_gr(gk20a);
+
+	gk20a_dbg_info("total ram pages : %lu", totalram_pages);
+	gk20a->gr.max_comptag_mem = totalram_pages
+				 >> (10 - (PAGE_SHIFT - 10));
+
+	nvgpu_ref_init(&gk20a->refcount);
+
+	return 0;
+}
+
+int vgpu_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct gk20a *g = get_gk20a(dev);
+
+	gk20a_dbg_fn("");
+
+	vgpu_pm_qos_remove(dev);
+	if (g->remove_support)
+		g->remove_support(g);
+
+	vgpu_comm_deinit();
+	gk20a_sched_ctrl_cleanup(g);
+	gk20a_user_deinit(dev, &nvgpu_class);
+	vgpu_remove_sysfs(dev);
+	gk20a_get_platform(dev)->g = NULL;
+	gk20a_put(g);
+
+	return 0;
+}

drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.h

@@ -0,0 +1,57 @@
+/*
+ * Virtualized GPU Linux Interfaces
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __VGPU_LINUX_H__
+#define __VGPU_LINUX_H__
+
+struct device;
+struct platform_device;
+
+#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
+
+#include "vgpu.h"
+
+int vgpu_pm_prepare_poweroff(struct device *dev);
+int vgpu_pm_finalize_poweron(struct device *dev);
+int vgpu_probe(struct platform_device *dev);
+int vgpu_remove(struct platform_device *dev);
+
+void vgpu_create_sysfs(struct device *dev);
+void vgpu_remove_sysfs(struct device *dev);
+#else
+/* define placeholders for functions used outside of vgpu */
+
+static inline int vgpu_pm_prepare_poweroff(struct device *dev)
+{
+	return -ENOSYS;
+}
+static inline int vgpu_pm_finalize_poweron(struct device *dev)
+{
+	return -ENOSYS;
+}
+static inline int vgpu_probe(struct platform_device *dev)
+{
+	return -ENOSYS;
+}
+static inline int vgpu_remove(struct platform_device *dev)
+{
+	return -ENOSYS;
+}
+#endif
+
+#endif

drivers/gpu/nvgpu/gk20a/gr_gk20a.h

@@ -28,6 +28,7 @@
 #include "mm_gk20a.h"
 
 #include <nvgpu/comptags.h>
+#include <nvgpu/cond.h>
 
 #define GR_IDLE_CHECK_DEFAULT		10 /* usec */
 #define GR_IDLE_CHECK_MAX		200 /* usec */

drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h

@@ -687,6 +687,7 @@ struct tegra_vgpu_fecs_trace_event_info {
 	u32 type;
 };
 
+#define TEGRA_VGPU_CHANNEL_EVENT_ID_MAX 6
 struct tegra_vgpu_channel_event_info {
 	u32 event_id;
 	u32 is_tsg;