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gpu: nvgpu: convert hw header functions to functional macros

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Using functional macros instead of static inline functions for defining
hw registers, fields, constants etc lets us not compile the dead code
in the build (non-gv11b for igpu safety build for instance).
This patch updates the all nvgpu hw headers to use define_style instead
of inline_style.

JIRA NVGPU-3733

Change-Id: I2d5d596fcfa0a75ce09444edad0a8c2851ee00dc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150879
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-07-09 14:54:07 +05:30
committed by mobile promotions
parent e0419c4199
commit 8a3f7a4496
212 changed files with 25180 additions and 91528 deletions
Download Patch File Download Diff File Expand all files Collapse all files

142
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,116 +59,32 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 bus_bar0_window_r(void)
{
return 0x00001700U;
}
static inline u32 bus_bar0_window_base_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 bus_bar0_window_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
{
return 0x2000000U;
}
static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
{
return 0x3000000U;
}
static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
{
return 0x00000010U;
}
static inline u32 bus_bar1_block_r(void)
{
return 0x00001704U;
}
static inline u32 bus_bar1_block_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 bus_bar1_block_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 bus_bar1_block_mode_virtual_f(void)
{
return 0x80000000U;
}
static inline u32 bus_bar2_block_r(void)
{
return 0x00001714U;
}
static inline u32 bus_bar2_block_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 bus_bar2_block_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 bus_bar2_block_mode_virtual_f(void)
{
return 0x80000000U;
}
static inline u32 bus_bar1_block_ptr_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 bus_bar2_block_ptr_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 bus_intr_0_r(void)
{
return 0x00001100U;
}
static inline u32 bus_intr_0_pri_squash_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 bus_intr_0_pri_fecserr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 bus_intr_0_pri_timeout_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 bus_intr_en_0_r(void)
{
return 0x00001140U;
}
static inline u32 bus_intr_en_0_pri_squash_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 bus_intr_en_0_pri_fecserr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 bus_intr_en_0_pri_timeout_m(void)
{
return U32(0x1U) << 3U;
}
#define bus_bar0_window_r() (0x00001700U)
#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U)
#define bus_bar0_window_target_vid_mem_f() (0x0U)
#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U)
#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U)
#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U)
#define bus_bar1_block_r() (0x00001704U)
#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define bus_bar1_block_target_vid_mem_f() (0x0U)
#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar1_block_mode_virtual_f() (0x80000000U)
#define bus_bar2_block_r() (0x00001714U)
#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define bus_bar2_block_target_vid_mem_f() (0x0U)
#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar2_block_mode_virtual_f() (0x80000000U)
#define bus_bar1_block_ptr_shift_v() (0x0000000cU)
#define bus_bar2_block_ptr_shift_v() (0x0000000cU)
#define bus_intr_0_r() (0x00001100U)
#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U)
#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U)
#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U)
#define bus_intr_en_0_r() (0x00001140U)
#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U)
#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U)
#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U)
#endif

184
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,148 +59,42 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ccsr_channel_inst_r(u32 i)
{
return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 ccsr_channel_inst__size_1_v(void)
{
return 0x00000080U;
}
static inline u32 ccsr_channel_inst_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 ccsr_channel_inst_bind_false_f(void)
{
return 0x0U;
}
static inline u32 ccsr_channel_inst_bind_true_f(void)
{
return 0x80000000U;
}
static inline u32 ccsr_channel_r(u32 i)
{
return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 ccsr_channel__size_1_v(void)
{
return 0x00000080U;
}
static inline u32 ccsr_channel_enable_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ccsr_channel_enable_in_use_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_enable_set_f(u32 v)
{
return (v & 0x1U) << 10U;
}
static inline u32 ccsr_channel_enable_set_true_f(void)
{
return 0x400U;
}
static inline u32 ccsr_channel_enable_clr_true_f(void)
{
return 0x800U;
}
static inline u32 ccsr_channel_runlist_f(u32 v)
{
return (v & 0xfU) << 16U;
}
static inline u32 ccsr_channel_status_v(u32 r)
{
return (r >> 24U) & 0xfU;
}
static inline u32 ccsr_channel_status_idle_v(void)
{
return 0x00000000U;
}
static inline u32 ccsr_channel_status_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
{
return 0x00000002U;
}
static inline u32 ccsr_channel_status_pending_acquire_v(void)
{
return 0x00000003U;
}
static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
{
return 0x00000004U;
}
static inline u32 ccsr_channel_status_on_pbdma_v(void)
{
return 0x00000005U;
}
static inline u32 ccsr_channel_status_on_pbdma_and_eng_v(void)
{
return 0x00000006U;
}
static inline u32 ccsr_channel_status_on_eng_v(void)
{
return 0x00000007U;
}
static inline u32 ccsr_channel_status_on_eng_pending_acquire_v(void)
{
return 0x00000008U;
}
static inline u32 ccsr_channel_status_on_eng_pending_v(void)
{
return 0x00000009U;
}
static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
{
return 0x0000000aU;
}
static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
{
return 0x0000000bU;
}
static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
{
return 0x0000000cU;
}
static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
{
return 0x0000000dU;
}
static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
{
return 0x0000000eU;
}
static inline u32 ccsr_channel_next_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 ccsr_channel_next_true_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_busy_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ccsr_channel_busy_true_v(void)
{
return 0x00000001U;
}
#define ccsr_channel_inst_r(i)\
(nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel_inst__size_1_v() (0x00000080U)
#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define ccsr_channel_inst_target_vid_mem_f() (0x0U)
#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U)
#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U)
#define ccsr_channel_inst_bind_false_f() (0x0U)
#define ccsr_channel_inst_bind_true_f() (0x80000000U)
#define ccsr_channel_r(i)\
(nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel__size_1_v() (0x00000080U)
#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U)
#define ccsr_channel_enable_in_use_v() (0x00000001U)
#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U)
#define ccsr_channel_enable_set_true_f() (0x400U)
#define ccsr_channel_enable_clr_true_f() (0x800U)
#define ccsr_channel_runlist_f(v) (((v)&0xfU) << 16U)
#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU)
#define ccsr_channel_status_idle_v() (0x00000000U)
#define ccsr_channel_status_pending_v() (0x00000001U)
#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U)
#define ccsr_channel_status_pending_acquire_v() (0x00000003U)
#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U)
#define ccsr_channel_status_on_pbdma_v() (0x00000005U)
#define ccsr_channel_status_on_pbdma_and_eng_v() (0x00000006U)
#define ccsr_channel_status_on_eng_v() (0x00000007U)
#define ccsr_channel_status_on_eng_pending_acquire_v() (0x00000008U)
#define ccsr_channel_status_on_eng_pending_v() (0x00000009U)
#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU)
#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU)
#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU)
#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU)
#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU)
#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U)
#define ccsr_channel_next_true_v() (0x00000001U)
#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U)
#define ccsr_channel_busy_true_v() (0x00000001U)
#endif

37
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,32 +59,11 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ce2_intr_status_r(void)
{
return 0x00106908U;
}
static inline u32 ce2_intr_status_blockpipe_pending_f(void)
{
return 0x1U;
}
static inline u32 ce2_intr_status_blockpipe_reset_f(void)
{
return 0x1U;
}
static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
{
return 0x2U;
}
static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
{
return 0x2U;
}
static inline u32 ce2_intr_status_launcherr_pending_f(void)
{
return 0x4U;
}
static inline u32 ce2_intr_status_launcherr_reset_f(void)
{
return 0x4U;
}
#define ce2_intr_status_r() (0x00106908U)
#define ce2_intr_status_blockpipe_pending_f() (0x1U)
#define ce2_intr_status_blockpipe_reset_f() (0x1U)
#define ce2_intr_status_nonblockpipe_pending_f() (0x2U)
#define ce2_intr_status_nonblockpipe_reset_f() (0x2U)
#define ce2_intr_status_launcherr_pending_f() (0x4U)
#define ce2_intr_status_launcherr_reset_f() (0x4U)
#endif

519
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,396 +59,129 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ctxsw_prog_fecs_header_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_gpccs_header_stride_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
{
return 0x00000008U;
}
static inline u32 ctxsw_prog_main_image_patch_count_o(void)
{
return 0x00000010U;
}
static inline u32 ctxsw_prog_main_image_context_id_o(void)
{
return 0x000000f0U;
}
static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
{
return 0x00000014U;
}
static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
{
return 0x00000018U;
}
static inline u32 ctxsw_prog_main_image_zcull_o(void)
{
return 0x0000001cU;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
{
return 0x00000001U;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
{
return 0x00000002U;
}
static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
{
return 0x00000020U;
}
static inline u32 ctxsw_prog_main_image_pm_o(void)
{
return 0x00000028U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
{
return U32(0x7U) << 0U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
{
return U32(0x7U) << 3U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
{
return 0x8U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
{
return 0x0000002cU;
}
static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
{
return 0x000000f4U;
}
static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
{
return 0x000000f8U;
}
static inline u32 ctxsw_prog_main_image_magic_value_o(void)
{
return 0x000000fcU;
}
static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
{
return 0x600dc0deU;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
{
return 0x000000f4U;
}
static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
{
return (r >> 16U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
{
return 0x000000f8U;
}
static inline u32 ctxsw_prog_local_magic_value_o(void)
{
return 0x000000fcU;
}
static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
{
return 0xad0becabU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
{
return 0x000000ecU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
{
return 0x00000005U;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_extended_num_smpc_quadrants_v(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
{
return 0x000000a0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
{
return 2U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
{
return 0x2U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
{
return 0x000000a4U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
{
return 0x000000a8U;
}
static inline u32 ctxsw_prog_main_image_misc_options_o(void)
{
return 0x0000003cU;
}
static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
{
return 0x000000acU;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
{
return 0x000000b0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
{
return U32(0xfffffffU) << 0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
{
return U32(0x3U) << 28U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
{
return 0x20000000U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
{
return 0x30000000U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
{
return 0x000000b4U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
{
return 0x00000080U;
}
static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
{
return 0x00000020U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
{
return 0x00000000U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
{
return 0x00000000U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
{
return 0x600dbeefU;
}
static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
{
return 0x00000008U;
}
static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void)
{
return 0x00000010U;
}
static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void)
{
return 0x00000014U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
{
return 0x00000018U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
{
return 0x0000001cU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
{
return (r >> 0U) & 0xffffffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
{
return U32(0xffU) << 24U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
{
return (r >> 24U) & 0xffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
{
return 0x00000001U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
{
return 0x1000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
{
return 0x00000002U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
{
return 0x2000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
{
return 0x0000000aU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
{
return 0xa000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
{
return 0x0000000bU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
{
return 0xb000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
{
return 0xc000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
{
return 0x0000000dU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
{
return 0xd000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
{
return 0x00000003U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
{
return 0x3000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
{
return 0x4000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
{
return 0x00000005U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
{
return 0x5000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
{
return 0x000000ffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
{
return 0xff000000U;
}
#define ctxsw_prog_fecs_header_v() (0x00000100U)
#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U)
#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U)
#define ctxsw_prog_main_image_patch_count_o() (0x00000010U)
#define ctxsw_prog_main_image_context_id_o() (0x000000f0U)
#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U)
#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U)
#define ctxsw_prog_main_image_zcull_o() (0x0000001cU)
#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U)
#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U)
#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U)
#define ctxsw_prog_main_image_pm_o() (0x00000028U)
#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U)
#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U)
#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U)
#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U)
#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U)
#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U)
#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU)
#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U)
#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U)
#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU)
#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU)
#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU)
#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U)
#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU)
#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U)
#define ctxsw_prog_local_magic_value_o() (0x000000fcU)
#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU)
#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU)
#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU)
#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U)
#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U)
#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\
(0x00000005U)
#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\
(0x00000004U)
#define ctxsw_prog_extended_num_smpc_quadrants_v() (0x00000004U)
#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\
(((v)&0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\
(((r) >> 0U) & 0x3U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U)
#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U)
#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U)
#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU)
#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U)
#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\
(((v)&0xffffU) << 0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\
(U32(0xfffffffU) << 0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m()\
(U32(0x3U) << 28U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f()\
(0x0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f()\
(0x20000000U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f()\
(0x30000000U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\
(((v)&0xffffffffU) << 0U)
#define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U)
#define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U)
#define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U)
#define ctxsw_prog_record_timestamp_magic_value_lo_v_value_v() (0x00000000U)
#define ctxsw_prog_record_timestamp_magic_value_hi_o() (0x00000004U)
#define ctxsw_prog_record_timestamp_magic_value_hi_v_value_v() (0x600dbeefU)
#define ctxsw_prog_record_timestamp_context_id_o() (0x00000008U)
#define ctxsw_prog_record_timestamp_context_ptr_o() (0x0000000cU)
#define ctxsw_prog_record_timestamp_new_context_id_o() (0x00000010U)
#define ctxsw_prog_record_timestamp_new_context_ptr_o() (0x00000014U)
#define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U)
#define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v) (((v)&0xffffffU) << 0U)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\
(((r) >> 0U) & 0xffffffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v) (((v)&0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\
(0x00000001U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f()\
(0x1000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v() (0x00000002U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f() (0x2000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v()\
(0x0000000aU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f() (0xa000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v()\
(0x0000000bU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f()\
(0xb000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v()\
(0x0000000cU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f()\
(0xc000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v()\
(0x0000000dU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f()\
(0xd000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v() (0x00000003U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f() (0x3000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v()\
(0x00000004U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f()\
(0x4000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v()\
(0x00000005U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f()\
(0x5000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v()\
(0x000000ffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f()\
(0xff000000U)
#endif

632
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,504 +59,134 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 falcon_falcon_irqsset_r(void)
{
return 0x00000000U;
}
static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
{
return 0x40U;
}
static inline u32 falcon_falcon_irqsclr_r(void)
{
return 0x00000004U;
}
static inline u32 falcon_falcon_irqstat_r(void)
{
return 0x00000008U;
}
static inline u32 falcon_falcon_irqstat_halt_true_f(void)
{
return 0x10U;
}
static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
{
return 0x20U;
}
static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
{
return 0x40U;
}
static inline u32 falcon_falcon_irqmode_r(void)
{
return 0x0000000cU;
}
static inline u32 falcon_falcon_irqmset_r(void)
{
return 0x00000010U;
}
static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqmclr_r(void)
{
return 0x00000014U;
}
static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_irqmask_r(void)
{
return 0x00000018U;
}
static inline u32 falcon_falcon_irqdest_r(void)
{
return 0x0000001cU;
}
static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
{
return (v & 0x1U) << 17U;
}
static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
{
return (v & 0x1U) << 18U;
}
static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
{
return (v & 0x1U) << 19U;
}
static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
{
return (v & 0x1U) << 20U;
}
static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
{
return (v & 0x1U) << 21U;
}
static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
{
return (v & 0x1U) << 22U;
}
static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
{
return (v & 0x1U) << 23U;
}
static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 falcon_falcon_curctx_r(void)
{
return 0x00000050U;
}
static inline u32 falcon_falcon_nxtctx_r(void)
{
return 0x00000054U;
}
static inline u32 falcon_falcon_mailbox0_r(void)
{
return 0x00000040U;
}
static inline u32 falcon_falcon_mailbox1_r(void)
{
return 0x00000044U;
}
static inline u32 falcon_falcon_itfen_r(void)
{
return 0x00000048U;
}
static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
{
return 0x1U;
}
static inline u32 falcon_falcon_idlestate_r(void)
{
return 0x0000004cU;
}
static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
{
return (r >> 1U) & 0x7fffU;
}
static inline u32 falcon_falcon_os_r(void)
{
return 0x00000080U;
}
static inline u32 falcon_falcon_engctl_r(void)
{
return 0x000000a4U;
}
static inline u32 falcon_falcon_cpuctl_r(void)
{
return 0x00000100U;
}
static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 falcon_falcon_cpuctl_stopped_m(void)
{
return U32(0x1U) << 5U;
}
static inline u32 falcon_falcon_imemc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_imemc_offs_f(u32 v)
{
return (v & 0x3fU) << 2U;
}
static inline u32 falcon_falcon_imemc_blk_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 falcon_falcon_imemc_secure_f(u32 v)
{
return (v & 0x1U) << 28U;
}
static inline u32 falcon_falcon_imemd_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_imemt_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_bootvec_r(void)
{
return 0x00000104U;
}
static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 falcon_falcon_dmactl_r(void)
{
return 0x0000010cU;
}
static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_hwcfg_r(void)
{
return 0x00000108U;
}
static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
{
return (r >> 0U) & 0x1ffU;
}
static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
{
return (r >> 9U) & 0x1ffU;
}
static inline u32 falcon_falcon_dmatrfbase_r(void)
{
return 0x00000110U;
}
static inline u32 falcon_falcon_dmatrfmoffs_r(void)
{
return 0x00000114U;
}
static inline u32 falcon_falcon_dmatrfcmd_r(void)
{
return 0x00000118U;
}
static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
{
return (v & 0x7U) << 8U;
}
static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
{
return (v & 0x7U) << 12U;
}
static inline u32 falcon_falcon_dmatrffboffs_r(void)
{
return 0x0000011cU;
}
static inline u32 falcon_falcon_imstat_r(void)
{
return 0x00000144U;
}
static inline u32 falcon_falcon_traceidx_r(void)
{
return 0x00000148U;
}
static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 falcon_falcon_traceidx_idx_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 falcon_falcon_tracepc_r(void)
{
return 0x0000014cU;
}
static inline u32 falcon_falcon_tracepc_pc_v(u32 r)
{
return (r >> 0U) & 0xffffffU;
}
static inline u32 falcon_falcon_exterraddr_r(void)
{
return 0x00000168U;
}
static inline u32 falcon_falcon_exterrstat_r(void)
{
return 0x0000016cU;
}
static inline u32 falcon_falcon_exterrstat_valid_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
{
return 0x00000001U;
}
static inline u32 falcon_falcon_icd_cmd_r(void)
{
return 0x00000200U;
}
static inline u32 falcon_falcon_icd_cmd_opc_s(void)
{
return 4U;
}
static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 falcon_falcon_icd_cmd_opc_m(void)
{
return U32(0xfU) << 0U;
}
static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
{
return 0x8U;
}
static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
{
return 0xeU;
}
static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
{
return (v & 0x1fU) << 8U;
}
static inline u32 falcon_falcon_icd_rdata_r(void)
{
return 0x0000020cU;
}
static inline u32 falcon_falcon_dmemc_r(u32 i)
{
return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
{
return (v & 0x3fU) << 2U;
}
static inline u32 falcon_falcon_dmemc_offs_m(void)
{
return U32(0x3fU) << 2U;
}
static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_dmemc_blk_m(void)
{
return U32(0xffU) << 8U;
}
static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
{
return (v & 0x1U) << 25U;
}
static inline u32 falcon_falcon_dmemd_r(u32 i)
{
return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 falcon_falcon_debug1_r(void)
{
return 0x00000090U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
{
return 1U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
{
return 0x0U;
}
static inline u32 falcon_falcon_debuginfo_r(void)
{
return 0x00000094U;
}
#define falcon_falcon_irqsset_r() (0x00000000U)
#define falcon_falcon_irqsset_swgen0_set_f() (0x40U)
#define falcon_falcon_irqsclr_r() (0x00000004U)
#define falcon_falcon_irqstat_r() (0x00000008U)
#define falcon_falcon_irqstat_halt_true_f() (0x10U)
#define falcon_falcon_irqstat_exterr_true_f() (0x20U)
#define falcon_falcon_irqstat_swgen0_true_f() (0x40U)
#define falcon_falcon_irqmode_r() (0x0000000cU)
#define falcon_falcon_irqmset_r() (0x00000010U)
#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqmclr_r() (0x00000014U)
#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_irqmask_r() (0x00000018U)
#define falcon_falcon_irqdest_r() (0x0000001cU)
#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U)
#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U)
#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U)
#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U)
#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U)
#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U)
#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U)
#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U)
#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U)
#define falcon_falcon_curctx_r() (0x00000050U)
#define falcon_falcon_nxtctx_r() (0x00000054U)
#define falcon_falcon_mailbox0_r() (0x00000040U)
#define falcon_falcon_mailbox1_r() (0x00000044U)
#define falcon_falcon_itfen_r() (0x00000048U)
#define falcon_falcon_itfen_ctxen_enable_f() (0x1U)
#define falcon_falcon_idlestate_r() (0x0000004cU)
#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U)
#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU)
#define falcon_falcon_os_r() (0x00000080U)
#define falcon_falcon_engctl_r() (0x000000a4U)
#define falcon_falcon_cpuctl_r() (0x00000100U)
#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U)
#define falcon_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U)
#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U)
#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U)
#define falcon_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemt_r(i)\
(nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_bootvec_r() (0x00000104U)
#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U)
#define falcon_falcon_dmactl_r() (0x0000010cU)
#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_hwcfg_r() (0x00000108U)
#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
#define falcon_falcon_dmatrfbase_r() (0x00000110U)
#define falcon_falcon_dmatrfmoffs_r() (0x00000114U)
#define falcon_falcon_dmatrfcmd_r() (0x00000118U)
#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U)
#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U)
#define falcon_falcon_dmatrffboffs_r() (0x0000011cU)
#define falcon_falcon_imstat_r() (0x00000144U)
#define falcon_falcon_traceidx_r() (0x00000148U)
#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU)
#define falcon_falcon_traceidx_idx_v(r) (((r) >> 0U) & 0xffU)
#define falcon_falcon_tracepc_r() (0x0000014cU)
#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU)
#define falcon_falcon_exterraddr_r() (0x0010a168U)
#define falcon_falcon_exterrstat_r() (0x0010a16cU)
#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U)
#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U)
#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U)
#define falcon_falcon_icd_cmd_r() (0x00000200U)
#define falcon_falcon_icd_cmd_opc_s() (4U)
#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U)
#define falcon_falcon_icd_rdata_r() (0x0000020cU)
#define falcon_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U)
#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U)
#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U)
#define falcon_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_debug1_r() (0x00000090U)
#define falcon_falcon_debug1_ctxsw_mode_s() (1U)
#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U)
#define falcon_falcon_debuginfo_r() (0x00000094U)
#endif

257
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fb_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,208 +59,55 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fb_mmu_ctrl_r(void)
{
return 0x00100c80U;
}
static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
{
return 0x1U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 fb_mmu_invalidate_pdb_r(void)
{
return 0x00100cb8U;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_invalidate_r(void)
{
return 0x00100cbcU;
}
static inline u32 fb_mmu_invalidate_all_va_true_f(void)
{
return 0x1U;
}
static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_invalidate_trigger_s(void)
{
return 1U;
}
static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 fb_mmu_invalidate_trigger_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_trigger_true_f(void)
{
return 0x80000000U;
}
static inline u32 fb_mmu_debug_wr_r(void)
{
return 0x00100cc8U;
}
static inline u32 fb_mmu_debug_wr_aperture_s(void)
{
return 2U;
}
static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 fb_mmu_debug_wr_aperture_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 fb_mmu_debug_wr_vol_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_wr_vol_true_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_debug_wr_vol_true_f(void)
{
return 0x4U;
}
static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
{
return 0x0000000cU;
}
static inline u32 fb_mmu_debug_rd_r(void)
{
return 0x00100cccU;
}
static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 fb_mmu_debug_rd_vol_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
{
return 0x0000000cU;
}
static inline u32 fb_mmu_debug_ctrl_r(void)
{
return 0x00100cc4U;
}
static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 fb_mmu_debug_ctrl_debug_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
{
return 0x10000U;
}
static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_vpr_info_r(void)
{
return 0x00100cd0U;
}
static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
{
return 0x00000001U;
}
static inline u32 fb_niso_flush_sysmem_addr_r(void)
{
return 0x00100c10U;
}
#define fb_mmu_ctrl_r() (0x00100c80U)
#define fb_mmu_ctrl_vm_pg_size_f(v) (((v)&0x1U) << 0U)
#define fb_mmu_ctrl_vm_pg_size_128kb_f() (0x0U)
#define fb_mmu_ctrl_vm_pg_size_64kb_f() (0x1U)
#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U)
#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U)
#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU)
#define fb_mmu_invalidate_pdb_r() (0x00100cb8U)
#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U)
#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U)
#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_invalidate_r() (0x00100cbcU)
#define fb_mmu_invalidate_all_va_true_f() (0x1U)
#define fb_mmu_invalidate_all_pdb_true_f() (0x2U)
#define fb_mmu_invalidate_trigger_s() (1U)
#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U)
#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U)
#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_invalidate_trigger_true_f() (0x80000000U)
#define fb_mmu_debug_wr_r() (0x00100cc8U)
#define fb_mmu_debug_wr_aperture_s() (2U)
#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_wr_vol_false_f() (0x0U)
#define fb_mmu_debug_wr_vol_true_v() (0x00000001U)
#define fb_mmu_debug_wr_vol_true_f() (0x4U)
#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_rd_r() (0x00100cccU)
#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_rd_vol_false_f() (0x0U)
#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_ctrl_r() (0x00100cc4U)
#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U)
#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U)
#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U)
#define fb_mmu_debug_ctrl_debug_enabled_f() (0x10000U)
#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U)
#define fb_mmu_debug_ctrl_debug_disabled_f() (0x0U)
#define fb_mmu_vpr_info_r() (0x00100cd0U)
#define fb_mmu_vpr_info_fetch_v(r) (((r) >> 2U) & 0x1U)
#define fb_mmu_vpr_info_fetch_false_v() (0x00000000U)
#define fb_mmu_vpr_info_fetch_true_v() (0x00000001U)
#define fb_niso_flush_sysmem_addr_r() (0x00100c10U)
#endif

728
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,572 +59,162 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fifo_bar1_base_r(void)
{
return 0x00002254U;
}
static inline u32 fifo_bar1_base_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 fifo_bar1_base_valid_false_f(void)
{
return 0x0U;
}
static inline u32 fifo_bar1_base_valid_true_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_runlist_base_r(void)
{
return 0x00002270U;
}
static inline u32 fifo_runlist_base_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 fifo_runlist_base_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 fifo_runlist_r(void)
{
return 0x00002274U;
}
static inline u32 fifo_runlist_engine_f(u32 v)
{
return (v & 0xfU) << 20U;
}
static inline u32 fifo_eng_runlist_base_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_eng_runlist_base__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_eng_runlist_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_eng_runlist__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_eng_runlist_length_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 fifo_eng_runlist_length_max_v(void)
{
return 0x0000ffffU;
}
static inline u32 fifo_eng_runlist_pending_true_f(void)
{
return 0x100000U;
}
static inline u32 fifo_runlist_timeslice_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002310U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_runlist_timeslice_timeout_128_f(void)
{
return 0x80U;
}
static inline u32 fifo_runlist_timeslice_timescale_3_f(void)
{
return 0x3000U;
}
static inline u32 fifo_runlist_timeslice_enable_true_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_eng_timeout_r(void)
{
return 0x00002a0cU;
}
static inline u32 fifo_eng_timeout_period_max_f(void)
{
return 0x7fffffffU;
}
static inline u32 fifo_eng_timeout_detection_enabled_f(void)
{
return 0x80000000U;
}
static inline u32 fifo_eng_timeout_detection_disabled_f(void)
{
return 0x0U;
}
static inline u32 fifo_pb_timeslice_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_pb_timeslice_timeout_16_f(void)
{
return 0x10U;
}
static inline u32 fifo_pb_timeslice_timescale_0_f(void)
{
return 0x0U;
}
static inline u32 fifo_pb_timeslice_enable_true_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_pbdma_map_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_intr_0_r(void)
{
return 0x00002100U;
}
static inline u32 fifo_intr_0_bind_error_pending_f(void)
{
return 0x1U;
}
static inline u32 fifo_intr_0_bind_error_reset_f(void)
{
return 0x1U;
}
static inline u32 fifo_intr_0_pio_error_pending_f(void)
{
return 0x10U;
}
static inline u32 fifo_intr_0_pio_error_reset_f(void)
{
return 0x10U;
}
static inline u32 fifo_intr_0_sched_error_pending_f(void)
{
return 0x100U;
}
static inline u32 fifo_intr_0_sched_error_reset_f(void)
{
return 0x100U;
}
static inline u32 fifo_intr_0_chsw_error_pending_f(void)
{
return 0x10000U;
}
static inline u32 fifo_intr_0_chsw_error_reset_f(void)
{
return 0x10000U;
}
static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
{
return 0x800000U;
}
static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
{
return 0x800000U;
}
static inline u32 fifo_intr_0_lb_error_pending_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_intr_0_lb_error_reset_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
{
return 0x8000000U;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
{
return 0x8000000U;
}
static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
{
return 0x20000000U;
}
static inline u32 fifo_intr_0_runlist_event_pending_f(void)
{
return 0x40000000U;
}
static inline u32 fifo_intr_0_channel_intr_pending_f(void)
{
return 0x80000000U;
}
static inline u32 fifo_intr_en_0_r(void)
{
return 0x00002140U;
}
static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
{
return (v & 0x1U) << 8U;
}
static inline u32 fifo_intr_en_0_sched_error_m(void)
{
return U32(0x1U) << 8U;
}
static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
{
return (v & 0x1U) << 28U;
}
static inline u32 fifo_intr_en_0_mmu_fault_m(void)
{
return U32(0x1U) << 28U;
}
static inline u32 fifo_intr_en_1_r(void)
{
return 0x00002528U;
}
static inline u32 fifo_intr_bind_error_r(void)
{
return 0x0000252cU;
}
static inline u32 fifo_intr_sched_error_r(void)
{
return 0x0000254cU;
}
static inline u32 fifo_intr_sched_error_code_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
{
return 0x0000000aU;
}
static inline u32 fifo_intr_chsw_error_r(void)
{
return 0x0000256cU;
}
static inline u32 fifo_intr_mmu_fault_id_r(void)
{
return 0x0000259cU;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
{
return 0x0U;
}
static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
{
return (r >> 0U) & 0xfffffffU;
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
{
return nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r)
{
return (r >> 7U) & 0x1U;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
{
return (r >> 6U) & 0x1U;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
{
return (r >> 8U) & 0x1fU;
}
static inline u32 fifo_intr_pbdma_id_r(void)
{
return 0x000025a0U;
}
static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
{
return (r >> (0U + i*1U)) & 0x1U;
}
static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_intr_runlist_r(void)
{
return 0x00002a00U;
}
static inline u32 fifo_fb_timeout_r(void)
{
return 0x00002a04U;
}
static inline u32 fifo_fb_timeout_period_m(void)
{
return U32(0x3fffffffU) << 0U;
}
static inline u32 fifo_fb_timeout_period_max_f(void)
{
return 0x3fffffffU;
}
static inline u32 fifo_pb_timeout_r(void)
{
return 0x00002a08U;
}
static inline u32 fifo_pb_timeout_detection_enabled_f(void)
{
return 0x80000000U;
}
static inline u32 fifo_error_sched_disable_r(void)
{
return 0x0000262cU;
}
static inline u32 fifo_sched_disable_r(void)
{
return 0x00002630U;
}
static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 fifo_sched_disable_runlist_m(u32 i)
{
return U32(0x1U) << (0U + i*1U);
}
static inline u32 fifo_sched_disable_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_preempt_r(void)
{
return 0x00002634U;
}
static inline u32 fifo_preempt_pending_true_f(void)
{
return 0x100000U;
}
static inline u32 fifo_preempt_type_channel_f(void)
{
return 0x0U;
}
static inline u32 fifo_preempt_type_tsg_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_preempt_chid_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 fifo_preempt_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 fifo_trigger_mmu_fault_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
{
return (v & 0x1fU) << 0U;
}
static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
{
return (v & 0x1U) << 8U;
}
static inline u32 fifo_engine_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_engine_status__size_1_v(void)
{
return 0x00000002U;
}
static inline u32 fifo_engine_status_id_v(u32 r)
{
return (r >> 0U) & 0xfffU;
}
static inline u32 fifo_engine_status_id_type_v(u32 r)
{
return (r >> 12U) & 0x1U;
}
static inline u32 fifo_engine_status_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctx_status_v(u32 r)
{
return (r >> 13U) & 0x7U;
}
static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_ctx_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
{
return 0x00000005U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
{
return 0x00000006U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
{
return 0x00000007U;
}
static inline u32 fifo_engine_status_next_id_v(u32 r)
{
return (r >> 16U) & 0xfffU;
}
static inline u32 fifo_engine_status_next_id_type_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 fifo_engine_status_next_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_next_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_faulted_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 fifo_engine_status_faulted_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_engine_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 fifo_engine_status_engine_idle_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_engine_busy_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctxsw_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
{
return 0x8000U;
}
static inline u32 fifo_pbdma_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_pbdma_status__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_id_v(u32 r)
{
return (r >> 0U) & 0xfffU;
}
static inline u32 fifo_pbdma_status_id_type_v(u32 r)
{
return (r >> 12U) & 0x1U;
}
static inline u32 fifo_pbdma_status_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
{
return (r >> 13U) & 0x7U;
}
static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
{
return 0x00000005U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
{
return 0x00000006U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
{
return 0x00000007U;
}
static inline u32 fifo_pbdma_status_next_id_v(u32 r)
{
return (r >> 16U) & 0xfffU;
}
static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chsw_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
{
return 0x00000001U;
}
#define fifo_bar1_base_r() (0x00002254U)
#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU)
#define fifo_bar1_base_valid_false_f() (0x0U)
#define fifo_bar1_base_valid_true_f() (0x10000000U)
#define fifo_runlist_base_r() (0x00002270U)
#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define fifo_runlist_base_target_vid_mem_f() (0x0U)
#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U)
#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U)
#define fifo_runlist_r() (0x00002274U)
#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U)
#define fifo_eng_runlist_base_r(i)\
(nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist_base__size_1_v() (0x00000001U)
#define fifo_eng_runlist_r(i)\
(nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist__size_1_v() (0x00000001U)
#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U)
#define fifo_eng_runlist_length_max_v() (0x0000ffffU)
#define fifo_eng_runlist_pending_true_f() (0x100000U)
#define fifo_runlist_timeslice_r(i)\
(nvgpu_safe_add_u32(0x00002310U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_runlist_timeslice_timeout_128_f() (0x80U)
#define fifo_runlist_timeslice_timescale_3_f() (0x3000U)
#define fifo_runlist_timeslice_enable_true_f() (0x10000000U)
#define fifo_eng_timeout_r() (0x00002a0cU)
#define fifo_eng_timeout_period_max_f() (0x7fffffffU)
#define fifo_eng_timeout_detection_enabled_f() (0x80000000U)
#define fifo_eng_timeout_detection_disabled_f() (0x0U)
#define fifo_pb_timeslice_r(i)\
(nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_pb_timeslice_timeout_16_f() (0x10U)
#define fifo_pb_timeslice_timescale_0_f() (0x0U)
#define fifo_pb_timeslice_enable_true_f() (0x10000000U)
#define fifo_pbdma_map_r(i)\
(nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_intr_0_r() (0x00002100U)
#define fifo_intr_0_bind_error_pending_f() (0x1U)
#define fifo_intr_0_bind_error_reset_f() (0x1U)
#define fifo_intr_0_pio_error_pending_f() (0x10U)
#define fifo_intr_0_pio_error_reset_f() (0x10U)
#define fifo_intr_0_sched_error_pending_f() (0x100U)
#define fifo_intr_0_sched_error_reset_f() (0x100U)
#define fifo_intr_0_chsw_error_pending_f() (0x10000U)
#define fifo_intr_0_chsw_error_reset_f() (0x10000U)
#define fifo_intr_0_fb_flush_timeout_pending_f() (0x800000U)
#define fifo_intr_0_fb_flush_timeout_reset_f() (0x800000U)
#define fifo_intr_0_lb_error_pending_f() (0x1000000U)
#define fifo_intr_0_lb_error_reset_f() (0x1000000U)
#define fifo_intr_0_dropped_mmu_fault_pending_f() (0x8000000U)
#define fifo_intr_0_dropped_mmu_fault_reset_f() (0x8000000U)
#define fifo_intr_0_mmu_fault_pending_f() (0x10000000U)
#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U)
#define fifo_intr_0_runlist_event_pending_f() (0x40000000U)
#define fifo_intr_0_channel_intr_pending_f() (0x80000000U)
#define fifo_intr_en_0_r() (0x00002140U)
#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U)
#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U)
#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U)
#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U)
#define fifo_intr_en_1_r() (0x00002528U)
#define fifo_intr_bind_error_r() (0x0000252cU)
#define fifo_intr_sched_error_r() (0x0000254cU)
#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U)
#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU)
#define fifo_intr_chsw_error_r() (0x0000256cU)
#define fifo_intr_mmu_fault_id_r() (0x0000259cU)
#define fifo_intr_mmu_fault_eng_id_graphics_v() (0x00000000U)
#define fifo_intr_mmu_fault_eng_id_graphics_f() (0x0U)
#define fifo_intr_mmu_fault_inst_r(i)\
(nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_inst_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define fifo_intr_mmu_fault_inst_ptr_align_shift_v() (0x0000000cU)
#define fifo_intr_mmu_fault_lo_r(i)\
(nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_hi_r(i)\
(nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_info_r(i)\
(nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_info_type_v(r) (((r) >> 0U) & 0xfU)
#define fifo_intr_mmu_fault_info_write_v(r) (((r) >> 7U) & 0x1U)
#define fifo_intr_mmu_fault_info_engine_subid_v(r) (((r) >> 6U) & 0x1U)
#define fifo_intr_mmu_fault_info_engine_subid_gpc_v() (0x00000000U)
#define fifo_intr_mmu_fault_info_engine_subid_hub_v() (0x00000001U)
#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x1fU)
#define fifo_intr_pbdma_id_r() (0x000025a0U)
#define fifo_intr_pbdma_id_status_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define fifo_intr_pbdma_id_status_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U)
#define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U)
#define fifo_intr_runlist_r() (0x00002a00U)
#define fifo_fb_timeout_r() (0x00002a04U)
#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U)
#define fifo_fb_timeout_period_max_f() (0x3fffffffU)
#define fifo_pb_timeout_r() (0x00002a08U)
#define fifo_pb_timeout_detection_enabled_f() (0x80000000U)
#define fifo_error_sched_disable_r() (0x0000262cU)
#define fifo_sched_disable_r() (0x00002630U)
#define fifo_sched_disable_runlist_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define fifo_sched_disable_runlist_m(i)\
(U32(0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_true_v() (0x00000001U)
#define fifo_preempt_r() (0x00002634U)
#define fifo_preempt_pending_true_f() (0x100000U)
#define fifo_preempt_type_channel_f() (0x0U)
#define fifo_preempt_type_tsg_f() (0x1000000U)
#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U)
#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U)
#define fifo_trigger_mmu_fault_r(i)\
(nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U)
#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U)
#define fifo_engine_status_r(i)\
(nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_engine_status__size_1_v() (0x00000002U)
#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU)
#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U)
#define fifo_engine_status_id_type_chid_v() (0x00000000U)
#define fifo_engine_status_id_type_tsgid_v() (0x00000001U)
#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U)
#define fifo_engine_status_ctx_status_invalid_v() (0x00000000U)
#define fifo_engine_status_ctx_status_valid_v() (0x00000001U)
#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U)
#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U)
#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U)
#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU)
#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U)
#define fifo_engine_status_next_id_type_chid_v() (0x00000000U)
#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U)
#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U)
#define fifo_engine_status_faulted_true_v() (0x00000001U)
#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U)
#define fifo_engine_status_engine_idle_v() (0x00000000U)
#define fifo_engine_status_engine_busy_v() (0x00000001U)
#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U)
#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U)
#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U)
#define fifo_pbdma_status_r(i)\
(nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_pbdma_status__size_1_v() (0x00000001U)
#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU)
#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U)
#define fifo_pbdma_status_id_type_chid_v() (0x00000000U)
#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U)
#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U)
#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U)
#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U)
#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U)
#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U)
#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU)
#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U)
#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U)
#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U)
#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U)
#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U)
#endif

162
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_flush_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,132 +59,36 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 flush_l2_system_invalidate_r(void)
{
return 0x00070004U;
}
static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_flush_dirty_r(void)
{
return 0x00070010U;
}
static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_clean_comptags_r(void)
{
return 0x0007000cU;
}
static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_fb_flush_r(void)
{
return 0x00070000U;
}
static inline u32 flush_fb_flush_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_fb_flush_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_fb_flush_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_fb_flush_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_fb_flush_outstanding_true_v(void)
{
return 0x00000001U;
}
#define flush_l2_system_invalidate_r() (0x00070004U)
#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U)
#define flush_l2_system_invalidate_pending_busy_f() (0x1U)
#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U)
#define flush_l2_flush_dirty_r() (0x00070010U)
#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U)
#define flush_l2_flush_dirty_pending_empty_f() (0x0U)
#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U)
#define flush_l2_flush_dirty_pending_busy_f() (0x1U)
#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U)
#define flush_l2_flush_dirty_outstanding_false_f() (0x0U)
#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U)
#define flush_l2_clean_comptags_r() (0x0007000cU)
#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U)
#define flush_l2_clean_comptags_pending_empty_f() (0x0U)
#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U)
#define flush_l2_clean_comptags_pending_busy_f() (0x1U)
#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U)
#define flush_l2_clean_comptags_outstanding_false_f() (0x0U)
#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U)
#define flush_fb_flush_r() (0x00070000U)
#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_fb_flush_pending_busy_v() (0x00000001U)
#define flush_fb_flush_pending_busy_f() (0x1U)
#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_fb_flush_outstanding_true_v() (0x00000001U)
#endif

282
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,228 +59,60 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 gmmu_pde_aperture_big_w(void)
{
return 0U;
}
static inline u32 gmmu_pde_aperture_big_invalid_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pde_aperture_big_video_memory_f(void)
{
return 0x1U;
}
static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 gmmu_pde_size_w(void)
{
return 0U;
}
static inline u32 gmmu_pde_size_full_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pde_address_big_sys_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 gmmu_pde_address_big_sys_w(void)
{
return 0U;
}
static inline u32 gmmu_pde_aperture_small_w(void)
{
return 1U;
}
static inline u32 gmmu_pde_aperture_small_invalid_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pde_aperture_small_video_memory_f(void)
{
return 0x1U;
}
static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 gmmu_pde_vol_small_w(void)
{
return 1U;
}
static inline u32 gmmu_pde_vol_small_true_f(void)
{
return 0x4U;
}
static inline u32 gmmu_pde_vol_small_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pde_vol_big_w(void)
{
return 1U;
}
static inline u32 gmmu_pde_vol_big_true_f(void)
{
return 0x8U;
}
static inline u32 gmmu_pde_vol_big_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pde_address_small_sys_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 gmmu_pde_address_small_sys_w(void)
{
return 1U;
}
static inline u32 gmmu_pde_address_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 gmmu_pde__size_v(void)
{
return 0x00000008U;
}
static inline u32 gmmu_pte__size_v(void)
{
return 0x00000008U;
}
static inline u32 gmmu_pte_valid_w(void)
{
return 0U;
}
static inline u32 gmmu_pte_valid_true_f(void)
{
return 0x1U;
}
static inline u32 gmmu_pte_valid_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pte_privilege_w(void)
{
return 0U;
}
static inline u32 gmmu_pte_privilege_true_f(void)
{
return 0x2U;
}
static inline u32 gmmu_pte_privilege_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pte_address_sys_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 gmmu_pte_address_sys_w(void)
{
return 0U;
}
static inline u32 gmmu_pte_address_vid_f(u32 v)
{
return (v & 0x1ffffffU) << 4U;
}
static inline u32 gmmu_pte_address_vid_w(void)
{
return 0U;
}
static inline u32 gmmu_pte_vol_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_vol_true_f(void)
{
return 0x1U;
}
static inline u32 gmmu_pte_vol_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pte_aperture_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_aperture_video_memory_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void)
{
return 0x4U;
}
static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void)
{
return 0x6U;
}
static inline u32 gmmu_pte_read_only_w(void)
{
return 0U;
}
static inline u32 gmmu_pte_read_only_true_f(void)
{
return 0x4U;
}
static inline u32 gmmu_pte_write_disable_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_write_disable_true_f(void)
{
return 0x80000000U;
}
static inline u32 gmmu_pte_read_disable_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_read_disable_true_f(void)
{
return 0x40000000U;
}
static inline u32 gmmu_pte_comptagline_s(void)
{
return 17U;
}
static inline u32 gmmu_pte_comptagline_f(u32 v)
{
return (v & 0x1ffffU) << 12U;
}
static inline u32 gmmu_pte_comptagline_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_address_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 gmmu_pte_kind_f(u32 v)
{
return (v & 0xffU) << 4U;
}
static inline u32 gmmu_pte_kind_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_kind_invalid_v(void)
{
return 0x000000ffU;
}
static inline u32 gmmu_pte_kind_pitch_v(void)
{
return 0x00000000U;
}
#define gmmu_pde_aperture_big_w() (0U)
#define gmmu_pde_aperture_big_invalid_f() (0x0U)
#define gmmu_pde_aperture_big_video_memory_f() (0x1U)
#define gmmu_pde_aperture_big_sys_mem_coh_f() (0x2U)
#define gmmu_pde_aperture_big_sys_mem_ncoh_f() (0x3U)
#define gmmu_pde_size_w() (0U)
#define gmmu_pde_size_full_f() (0x0U)
#define gmmu_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U)
#define gmmu_pde_address_big_sys_w() (0U)
#define gmmu_pde_aperture_small_w() (1U)
#define gmmu_pde_aperture_small_invalid_f() (0x0U)
#define gmmu_pde_aperture_small_video_memory_f() (0x1U)
#define gmmu_pde_aperture_small_sys_mem_coh_f() (0x2U)
#define gmmu_pde_aperture_small_sys_mem_ncoh_f() (0x3U)
#define gmmu_pde_vol_small_w() (1U)
#define gmmu_pde_vol_small_true_f() (0x4U)
#define gmmu_pde_vol_small_false_f() (0x0U)
#define gmmu_pde_vol_big_w() (1U)
#define gmmu_pde_vol_big_true_f() (0x8U)
#define gmmu_pde_vol_big_false_f() (0x0U)
#define gmmu_pde_address_small_sys_f(v) (((v)&0xfffffffU) << 4U)
#define gmmu_pde_address_small_sys_w() (1U)
#define gmmu_pde_address_shift_v() (0x0000000cU)
#define gmmu_pde__size_v() (0x00000008U)
#define gmmu_pte__size_v() (0x00000008U)
#define gmmu_pte_valid_w() (0U)
#define gmmu_pte_valid_true_f() (0x1U)
#define gmmu_pte_valid_false_f() (0x0U)
#define gmmu_pte_privilege_w() (0U)
#define gmmu_pte_privilege_true_f() (0x2U)
#define gmmu_pte_privilege_false_f() (0x0U)
#define gmmu_pte_address_sys_f(v) (((v)&0xfffffffU) << 4U)
#define gmmu_pte_address_sys_w() (0U)
#define gmmu_pte_address_vid_f(v) (((v)&0x1ffffffU) << 4U)
#define gmmu_pte_address_vid_w() (0U)
#define gmmu_pte_vol_w() (1U)
#define gmmu_pte_vol_true_f() (0x1U)
#define gmmu_pte_vol_false_f() (0x0U)
#define gmmu_pte_aperture_w() (1U)
#define gmmu_pte_aperture_video_memory_f() (0x0U)
#define gmmu_pte_aperture_sys_mem_coh_f() (0x4U)
#define gmmu_pte_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_pte_read_only_w() (0U)
#define gmmu_pte_read_only_true_f() (0x4U)
#define gmmu_pte_write_disable_w() (1U)
#define gmmu_pte_write_disable_true_f() (0x80000000U)
#define gmmu_pte_read_disable_w() (1U)
#define gmmu_pte_read_disable_true_f() (0x40000000U)
#define gmmu_pte_comptagline_s() (17U)
#define gmmu_pte_comptagline_f(v) (((v)&0x1ffffU) << 12U)
#define gmmu_pte_comptagline_w() (1U)
#define gmmu_pte_address_shift_v() (0x0000000cU)
#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U)
#define gmmu_pte_kind_w() (1U)
#define gmmu_pte_kind_invalid_v() (0x000000ffU)
#define gmmu_pte_kind_pitch_v() (0x00000000U)
#endif

4737
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
View File

File diff suppressed because it is too large Load Diff

522
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,400 +59,128 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ltc_pltcg_base_v(void)
{
return 0x00140000U;
}
static inline u32 ltc_pltcg_extent_v(void)
{
return 0x0017ffffU;
}
static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
{
return 0x001410c8U;
}
static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
{
return 0x00141200U;
}
static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
{
return 0x0017ea00U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
{
return 0x00141104U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
{
return (r >> 16U) & 0x3U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
{
return 0x00000000U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
{
return 0x00000002U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
{
return 0x0017e8c8U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
{
return 0x2U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
{
return 0x4U;
}
static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
{
return 0x001410c8U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
{
return 0x0017e8ccU;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
{
return (v & 0x1ffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
{
return 0x0017e8d0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
{
return (v & 0x1ffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
{
return 0x0001ffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
{
return 0x0017e8d4U;
}
static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
{
return 0x0000000bU;
}
static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
{
return (r >> 0U) & 0x3ffffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
{
return 0x0017e8dcU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
{
return (r >> 24U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(u32 r)
{
return (r >> 28U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
{
return 0x0017e91cU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
{
return (v & 0x1fU) << 16U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
{
return 0x0017ea44U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
{
return nvgpu_safe_add_u32(0x0017ea48U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
{
return 0x00000004U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
{
return 0x0017ea58U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
{
return 32U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
{
return (r >> 0U) & 0xffffffffU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
{
return 0x0017e924U;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
{
return 0x0017e828U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
{
return 0x00140828U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_intr_r(void)
{
return 0x00140820U;
}
static inline u32 ltc_ltcs_ltss_intr_r(void)
{
return 0x0017e820U;
}
static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
{
return U32(0x1U) << 20U;
}
static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void)
{
return U32(0x1U) << 21U;
}
static inline u32 ltc_ltc0_lts0_intr_r(void)
{
return 0x00141020U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
{
return 0x0017e910U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
{
return (r >> 8U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
{
return 0x00000003U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
{
return 0x300U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
{
return (r >> 29U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
{
return 0x20000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
{
return 0x40000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
{
return 0x0017e914U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
{
return (r >> 8U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
{
return 0x00000003U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
{
return 0x300U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
{
return 0x10000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
{
return (r >> 29U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
{
return 0x20000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
{
return 0x40000000U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
{
return 0x00140910U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
{
return 0x00140914U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1U;
}
#define ltc_pltcg_base_v() (0x00140000U)
#define ltc_pltcg_extent_v() (0x0017ffffU)
#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x001410c8U)
#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00141200U)
#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017ea00U)
#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00141104U)
#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U)
#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e8c8U)
#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U)
#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U)
#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x001410c8U)
#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e8ccU)
#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x1ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e8d0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x1ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0001ffffU)
#define ltc_ltcs_ltss_cbc_base_r() (0x0017e8d4U)
#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU)
#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU)
#define ltc_ltcs_ltss_cbc_param_r() (0x0017e8dcU)
#define ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(r)\
(((r) >> 0U) & 0xffffU)
#define ltc_ltcs_ltss_cbc_param_cache_line_size_v(r) (((r) >> 24U) & 0xfU)
#define ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(r) (((r) >> 28U) & 0xfU)
#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e91cU)
#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\
(((v)&0x1fU) << 16U)
#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017ea44U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
(nvgpu_safe_add_u32(0x0017ea48U, nvgpu_safe_mult_u32((i), 4U)))
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017ea58U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\
(((v)&0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\
(U32(0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\
(((r) >> 0U) & 0xffffffffU)
#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e924U)
#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U)
#define ltc_ltcs_ltss_g_elpg_r() (0x0017e828U)
#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U)
#define ltc_ltc0_ltss_g_elpg_r() (0x00140828U)
#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U)
#define ltc_ltc0_ltss_intr_r() (0x00140820U)
#define ltc_ltcs_ltss_intr_r() (0x0017e820U)
#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U)
#define ltc_ltcs_ltss_intr_en_illegal_compstat_m() (U32(0x1U) << 21U)
#define ltc_ltc0_lts0_intr_r() (0x00141020U)
#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e910U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\
(((r) >> 8U) & 0xfU)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\
(0x00000003U)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\
(((r) >> 28U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\
(0x10000000U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\
(((r) >> 29U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\
(0x20000000U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\
(((r) >> 30U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\
(0x40000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e914U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\
(((r) >> 8U) & 0xfU)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\
(((r) >> 16U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\
(((r) >> 28U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\
(((r) >> 29U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\
(0x20000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\
(((r) >> 30U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U)
#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x00140910U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x00140914U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U)
#endif

293
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_mc_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,236 +59,63 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 mc_boot_0_r(void)
{
return 0x00000000U;
}
static inline u32 mc_boot_0_architecture_v(u32 r)
{
return (r >> 24U) & 0x1fU;
}
static inline u32 mc_boot_0_implementation_v(u32 r)
{
return (r >> 20U) & 0xfU;
}
static inline u32 mc_boot_0_major_revision_v(u32 r)
{
return (r >> 4U) & 0xfU;
}
static inline u32 mc_boot_0_minor_revision_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 mc_intr_0_r(void)
{
return 0x00000100U;
}
static inline u32 mc_intr_0_pfifo_pending_f(void)
{
return 0x100U;
}
static inline u32 mc_intr_0_pgraph_pending_f(void)
{
return 0x1000U;
}
static inline u32 mc_intr_0_pmu_pending_f(void)
{
return 0x1000000U;
}
static inline u32 mc_intr_0_ltc_pending_f(void)
{
return 0x2000000U;
}
static inline u32 mc_intr_0_priv_ring_pending_f(void)
{
return 0x40000000U;
}
static inline u32 mc_intr_0_pbus_pending_f(void)
{
return 0x10000000U;
}
static inline u32 mc_intr_1_r(void)
{
return 0x00000104U;
}
static inline u32 mc_intr_mask_0_r(void)
{
return 0x00000640U;
}
static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
{
return 0x1000000U;
}
static inline u32 mc_intr_en_0_r(void)
{
return 0x00000140U;
}
static inline u32 mc_intr_en_0_inta_disabled_f(void)
{
return 0x0U;
}
static inline u32 mc_intr_en_0_inta_hardware_f(void)
{
return 0x1U;
}
static inline u32 mc_intr_mask_1_r(void)
{
return 0x00000644U;
}
static inline u32 mc_intr_mask_1_pmu_s(void)
{
return 1U;
}
static inline u32 mc_intr_mask_1_pmu_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 mc_intr_mask_1_pmu_m(void)
{
return U32(0x1U) << 24U;
}
static inline u32 mc_intr_mask_1_pmu_v(u32 r)
{
return (r >> 24U) & 0x1U;
}
static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
{
return 0x1000000U;
}
static inline u32 mc_intr_en_1_r(void)
{
return 0x00000144U;
}
static inline u32 mc_intr_en_1_inta_disabled_f(void)
{
return 0x0U;
}
static inline u32 mc_intr_en_1_inta_hardware_f(void)
{
return 0x1U;
}
static inline u32 mc_enable_r(void)
{
return 0x00000200U;
}
static inline u32 mc_enable_xbar_enabled_f(void)
{
return 0x4U;
}
static inline u32 mc_enable_l2_enabled_f(void)
{
return 0x8U;
}
static inline u32 mc_enable_pmedia_s(void)
{
return 1U;
}
static inline u32 mc_enable_pmedia_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 mc_enable_pmedia_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 mc_enable_pmedia_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 mc_enable_priv_ring_enabled_f(void)
{
return 0x20U;
}
static inline u32 mc_enable_ce0_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 mc_enable_pfifo_enabled_f(void)
{
return 0x100U;
}
static inline u32 mc_enable_pgraph_enabled_f(void)
{
return 0x1000U;
}
static inline u32 mc_enable_pwr_v(u32 r)
{
return (r >> 13U) & 0x1U;
}
static inline u32 mc_enable_pwr_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 mc_enable_pwr_enabled_f(void)
{
return 0x2000U;
}
static inline u32 mc_enable_pfb_enabled_f(void)
{
return 0x100000U;
}
static inline u32 mc_enable_ce2_m(void)
{
return U32(0x1U) << 21U;
}
static inline u32 mc_enable_ce2_enabled_f(void)
{
return 0x200000U;
}
static inline u32 mc_enable_blg_enabled_f(void)
{
return 0x8000000U;
}
static inline u32 mc_enable_perfmon_enabled_f(void)
{
return 0x10000000U;
}
static inline u32 mc_enable_hub_enabled_f(void)
{
return 0x20000000U;
}
static inline u32 mc_enable_pb_r(void)
{
return 0x00000204U;
}
static inline u32 mc_enable_pb_0_s(void)
{
return 1U;
}
static inline u32 mc_enable_pb_0_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 mc_enable_pb_0_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 mc_enable_pb_0_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 mc_enable_pb_0_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 mc_elpg_enable_r(void)
{
return 0x0000020cU;
}
static inline u32 mc_elpg_enable_xbar_enabled_f(void)
{
return 0x4U;
}
static inline u32 mc_elpg_enable_pfb_enabled_f(void)
{
return 0x100000U;
}
static inline u32 mc_elpg_enable_hub_enabled_f(void)
{
return 0x20000000U;
}
#define mc_boot_0_r() (0x00000000U)
#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU)
#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU)
#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU)
#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU)
#define mc_intr_0_r() (0x00000100U)
#define mc_intr_0_pfifo_pending_f() (0x100U)
#define mc_intr_0_pgraph_pending_f() (0x1000U)
#define mc_intr_0_pmu_pending_f() (0x1000000U)
#define mc_intr_0_ltc_pending_f() (0x2000000U)
#define mc_intr_0_priv_ring_pending_f() (0x40000000U)
#define mc_intr_0_pbus_pending_f() (0x10000000U)
#define mc_intr_1_r() (0x00000104U)
#define mc_intr_mask_0_r() (0x00000640U)
#define mc_intr_mask_0_pmu_enabled_f() (0x1000000U)
#define mc_intr_en_0_r() (0x00000140U)
#define mc_intr_en_0_inta_disabled_f() (0x0U)
#define mc_intr_en_0_inta_hardware_f() (0x1U)
#define mc_intr_mask_1_r() (0x00000644U)
#define mc_intr_mask_1_pmu_s() (1U)
#define mc_intr_mask_1_pmu_f(v) (((v)&0x1U) << 24U)
#define mc_intr_mask_1_pmu_m() (U32(0x1U) << 24U)
#define mc_intr_mask_1_pmu_v(r) (((r) >> 24U) & 0x1U)
#define mc_intr_mask_1_pmu_enabled_f() (0x1000000U)
#define mc_intr_en_1_r() (0x00000144U)
#define mc_intr_en_1_inta_disabled_f() (0x0U)
#define mc_intr_en_1_inta_hardware_f() (0x1U)
#define mc_enable_r() (0x00000200U)
#define mc_enable_xbar_enabled_f() (0x4U)
#define mc_enable_l2_enabled_f() (0x8U)
#define mc_enable_pmedia_s() (1U)
#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U)
#define mc_enable_pmedia_m() (U32(0x1U) << 4U)
#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U)
#define mc_enable_priv_ring_enabled_f() (0x20U)
#define mc_enable_ce0_m() (U32(0x1U) << 6U)
#define mc_enable_pfifo_enabled_f() (0x100U)
#define mc_enable_pgraph_enabled_f() (0x1000U)
#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U)
#define mc_enable_pwr_disabled_v() (0x00000000U)
#define mc_enable_pwr_enabled_f() (0x2000U)
#define mc_enable_pfb_enabled_f() (0x100000U)
#define mc_enable_ce2_m() (U32(0x1U) << 21U)
#define mc_enable_ce2_enabled_f() (0x200000U)
#define mc_enable_blg_enabled_f() (0x8000000U)
#define mc_enable_perfmon_enabled_f() (0x10000000U)
#define mc_enable_hub_enabled_f() (0x20000000U)
#define mc_enable_pb_r() (0x00000204U)
#define mc_enable_pb_0_s() (1U)
#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U)
#define mc_enable_pb_0_m() (U32(0x1U) << 0U)
#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U)
#define mc_enable_pb_0_enabled_v() (0x00000001U)
#define mc_enable_pb_sel_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define mc_elpg_enable_r() (0x0000020cU)
#define mc_elpg_enable_xbar_enabled_f() (0x4U)
#define mc_elpg_enable_pfb_enabled_f() (0x100000U)
#define mc_elpg_enable_hub_enabled_f() (0x20000000U)
#endif

686
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,520 +59,172 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pbdma_gp_entry1_r(void)
{
return 0x10000004U;
}
static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 pbdma_gp_entry1_length_f(u32 v)
{
return (v & 0x1fffffU) << 10U;
}
static inline u32 pbdma_gp_entry1_length_v(u32 r)
{
return (r >> 10U) & 0x1fffffU;
}
static inline u32 pbdma_gp_base_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_base__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 pbdma_gp_base_offset_f(u32 v)
{
return (v & 0x1fffffffU) << 3U;
}
static inline u32 pbdma_gp_base_rsvd_s(void)
{
return 3U;
}
static inline u32 pbdma_gp_base_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
{
return (v & 0x1fU) << 16U;
}
static inline u32 pbdma_gp_fetch_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_get_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_put_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_timeout_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_timeout__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 pbdma_timeout_period_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 pbdma_timeout_period_max_f(void)
{
return 0xffffffffU;
}
static inline u32 pbdma_pb_fetch_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_pb_fetch_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_get_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_get_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_put_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_put_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_formats_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_formats_gp_fermi0_f(void)
{
return 0x0U;
}
static inline u32 pbdma_formats_pb_fermi1_f(void)
{
return 0x100U;
}
static inline u32 pbdma_formats_mp_fermi0_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_pb_header_priv_user_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_method_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_subchannel_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_level_main_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_first_true_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_pb_header_type_inc_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_pb_header_type_non_inc_f(void)
{
return 0x60000000U;
}
static inline u32 pbdma_hdr_shadow_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_shadow_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_shadow_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_subdevice_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_subdevice_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 pbdma_subdevice_status_active_f(void)
{
return 0x10000000U;
}
static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_method0_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method0_addr_f(u32 v)
{
return (v & 0xfffU) << 2U;
}
static inline u32 pbdma_method0_addr_v(u32 r)
{
return (r >> 2U) & 0xfffU;
}
static inline u32 pbdma_method0_subch_v(u32 r)
{
return (r >> 16U) & 0x7U;
}
static inline u32 pbdma_method0_first_true_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_method0_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_method1_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method2_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method3_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_data0_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_target_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_target_engine_sw_f(void)
{
return 0x1fU;
}
static inline u32 pbdma_acquire_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_acquire_retry_man_2_f(void)
{
return 0x2U;
}
static inline u32 pbdma_acquire_retry_exp_2_f(void)
{
return 0x100U;
}
static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
{
return (v & 0xfU) << 11U;
}
static inline u32 pbdma_acquire_timeout_exp_max_v(void)
{
return 0x0000000fU;
}
static inline u32 pbdma_acquire_timeout_exp_max_f(void)
{
return 0x7800U;
}
static inline u32 pbdma_acquire_timeout_man_f(u32 v)
{
return (v & 0xffffU) << 15U;
}
static inline u32 pbdma_acquire_timeout_man_max_v(void)
{
return 0x0000ffffU;
}
static inline u32 pbdma_acquire_timeout_man_max_f(void)
{
return 0x7fff8000U;
}
static inline u32 pbdma_acquire_timeout_en_enable_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_acquire_timeout_en_disable_f(void)
{
return 0x0U;
}
static inline u32 pbdma_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_channel_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_signature_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_signature_hw_valid_f(void)
{
return 0xfaceU;
}
static inline u32 pbdma_signature_sw_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_userd_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_userd_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 pbdma_userd_addr_f(u32 v)
{
return (v & 0x7fffffU) << 9U;
}
static inline u32 pbdma_userd_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_userd_hi_addr_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 pbdma_hce_ctrl_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
{
return 0x20U;
}
static inline u32 pbdma_intr_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_0_memreq_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pbdma_intr_0_memreq_pending_f(void)
{
return 0x1U;
}
static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
{
return 0x2U;
}
static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
{
return 0x4U;
}
static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
{
return 0x8U;
}
static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
{
return 0x10U;
}
static inline u32 pbdma_intr_0_memflush_pending_f(void)
{
return 0x20U;
}
static inline u32 pbdma_intr_0_memop_pending_f(void)
{
return 0x40U;
}
static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
{
return 0x80U;
}
static inline u32 pbdma_intr_0_lbreq_pending_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
{
return 0x200U;
}
static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
{
return 0x400U;
}
static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
{
return 0x800U;
}
static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
{
return 0x1000U;
}
static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
{
return 0x2000U;
}
static inline u32 pbdma_intr_0_gpptr_pending_f(void)
{
return 0x4000U;
}
static inline u32 pbdma_intr_0_gpentry_pending_f(void)
{
return 0x8000U;
}
static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
{
return 0x10000U;
}
static inline u32 pbdma_intr_0_pbptr_pending_f(void)
{
return 0x20000U;
}
static inline u32 pbdma_intr_0_pbentry_pending_f(void)
{
return 0x40000U;
}
static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
{
return 0x80000U;
}
static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
{
return 0x100000U;
}
static inline u32 pbdma_intr_0_method_pending_f(void)
{
return 0x200000U;
}
static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_intr_0_device_pending_f(void)
{
return 0x800000U;
}
static inline u32 pbdma_intr_0_semaphore_pending_f(void)
{
return 0x2000000U;
}
static inline u32 pbdma_intr_0_acquire_pending_f(void)
{
return 0x4000000U;
}
static inline u32 pbdma_intr_0_pri_pending_f(void)
{
return 0x8000000U;
}
static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_intr_0_pbseg_pending_f(void)
{
return 0x40000000U;
}
static inline u32 pbdma_intr_0_signature_pending_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_intr_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_en_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_en_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_stall_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
{
return 0x1U;
}
static inline u32 pbdma_udma_nop_r(void)
{
return 0x00000008U;
}
static inline u32 pbdma_syncpointa_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_syncpointa_payload_v(u32 r)
{
return (r >> 0U) & 0xffffffffU;
}
static inline u32 pbdma_syncpointb_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_syncpointb_op_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 pbdma_syncpointb_op_wait_v(void)
{
return 0x00000000U;
}
static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
{
return 0x00000001U;
}
static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
{
return (r >> 8U) & 0xffU;
}
#define pbdma_gp_entry1_r() (0x10000004U)
#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU)
#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U)
#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU)
#define pbdma_gp_base_r(i)\
(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base__size_1_v() (0x00000001U)
#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U)
#define pbdma_gp_base_rsvd_s() (3U)
#define pbdma_gp_base_hi_r(i)\
(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U)
#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U)
#define pbdma_gp_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_get_r(i)\
(nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_put_r(i)\
(nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_timeout_r(i)\
(nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_timeout__size_1_v() (0x00000001U)
#define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U)
#define pbdma_timeout_period_max_f() (0xffffffffU)
#define pbdma_pb_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_pb_fetch_hi_r(i)\
(nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_get_r(i)\
(nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_get_hi_r(i)\
(nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_put_r(i)\
(nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_put_hi_r(i)\
(nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_formats_r(i)\
(nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_formats_gp_fermi0_f() (0x0U)
#define pbdma_formats_pb_fermi1_f() (0x100U)
#define pbdma_formats_mp_fermi0_f() (0x0U)
#define pbdma_pb_header_r(i)\
(nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_pb_header_priv_user_f() (0x0U)
#define pbdma_pb_header_method_zero_f() (0x0U)
#define pbdma_pb_header_subchannel_zero_f() (0x0U)
#define pbdma_pb_header_level_main_f() (0x0U)
#define pbdma_pb_header_first_true_f() (0x400000U)
#define pbdma_pb_header_type_inc_f() (0x20000000U)
#define pbdma_pb_header_type_non_inc_f() (0x60000000U)
#define pbdma_hdr_shadow_r(i)\
(nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_shadow_0_r(i)\
(nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_shadow_1_r(i)\
(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_r(i)\
(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U)
#define pbdma_subdevice_status_active_f() (0x10000000U)
#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U)
#define pbdma_method0_r(i)\
(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U)
#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU)
#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U)
#define pbdma_method0_first_true_f() (0x400000U)
#define pbdma_method0_valid_true_f() (0x80000000U)
#define pbdma_method1_r(i)\
(nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method2_r(i)\
(nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method3_r(i)\
(nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_data0_r(i)\
(nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_target_r(i)\
(nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_target_engine_sw_f() (0x1fU)
#define pbdma_acquire_r(i)\
(nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_acquire_retry_man_2_f() (0x2U)
#define pbdma_acquire_retry_exp_2_f() (0x100U)
#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U)
#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU)
#define pbdma_acquire_timeout_exp_max_f() (0x7800U)
#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U)
#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU)
#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U)
#define pbdma_acquire_timeout_en_enable_f() (0x80000000U)
#define pbdma_acquire_timeout_en_disable_f() (0x0U)
#define pbdma_status_r(i)\
(nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_channel_r(i)\
(nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_signature_r(i)\
(nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_signature_hw_valid_f() (0xfaceU)
#define pbdma_signature_sw_zero_f() (0x0U)
#define pbdma_userd_r(i)\
(nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_target_vid_mem_f() (0x0U)
#define pbdma_userd_target_sys_mem_coh_f() (0x2U)
#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U)
#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U)
#define pbdma_userd_hi_r(i)\
(nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U)
#define pbdma_hce_ctrl_r(i)\
(nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U)
#define pbdma_intr_0_r(i)\
(nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U)
#define pbdma_intr_0_memreq_pending_f() (0x1U)
#define pbdma_intr_0_memack_timeout_pending_f() (0x2U)
#define pbdma_intr_0_memack_extra_pending_f() (0x4U)
#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U)
#define pbdma_intr_0_memdat_extra_pending_f() (0x10U)
#define pbdma_intr_0_memflush_pending_f() (0x20U)
#define pbdma_intr_0_memop_pending_f() (0x40U)
#define pbdma_intr_0_lbconnect_pending_f() (0x80U)
#define pbdma_intr_0_lbreq_pending_f() (0x100U)
#define pbdma_intr_0_lback_timeout_pending_f() (0x200U)
#define pbdma_intr_0_lback_extra_pending_f() (0x400U)
#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U)
#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U)
#define pbdma_intr_0_gpfifo_pending_f() (0x2000U)
#define pbdma_intr_0_gpptr_pending_f() (0x4000U)
#define pbdma_intr_0_gpentry_pending_f() (0x8000U)
#define pbdma_intr_0_gpcrc_pending_f() (0x10000U)
#define pbdma_intr_0_pbptr_pending_f() (0x20000U)
#define pbdma_intr_0_pbentry_pending_f() (0x40000U)
#define pbdma_intr_0_pbcrc_pending_f() (0x80000U)
#define pbdma_intr_0_xbarconnect_pending_f() (0x100000U)
#define pbdma_intr_0_method_pending_f() (0x200000U)
#define pbdma_intr_0_methodcrc_pending_f() (0x400000U)
#define pbdma_intr_0_device_pending_f() (0x800000U)
#define pbdma_intr_0_semaphore_pending_f() (0x2000000U)
#define pbdma_intr_0_acquire_pending_f() (0x4000000U)
#define pbdma_intr_0_pri_pending_f() (0x8000000U)
#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U)
#define pbdma_intr_0_pbseg_pending_f() (0x40000000U)
#define pbdma_intr_0_signature_pending_f() (0x80000000U)
#define pbdma_intr_1_r(i)\
(nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_en_0_r(i)\
(nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_en_0_lbreq_enabled_f() (0x100U)
#define pbdma_intr_en_1_r(i)\
(nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_r(i)\
(nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_lbreq_enabled_f() (0x100U)
#define pbdma_intr_stall_1_r(i)\
(nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U)
#define pbdma_udma_nop_r() (0x00000008U)
#define pbdma_syncpointa_r(i)\
(nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_syncpointa_payload_v(r) (((r) >> 0U) & 0xffffffffU)
#define pbdma_syncpointb_r(i)\
(nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_syncpointb_op_v(r) (((r) >> 0U) & 0x3U)
#define pbdma_syncpointb_op_wait_v() (0x00000000U)
#define pbdma_syncpointb_wait_switch_v(r) (((r) >> 4U) & 0x1U)
#define pbdma_syncpointb_wait_switch_en_v() (0x00000001U)
#define pbdma_syncpointb_syncpt_index_v(r) (((r) >> 8U) & 0xffU)
#endif

192
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_perf_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,156 +59,42 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 perf_pmasys_control_r(void)
{
return 0x001b4000U;
}
static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
{
return 0x10U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
{
return (r >> 5U) & 0x1U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
{
return 0x20U;
}
static inline u32 perf_pmasys_mem_block_r(void)
{
return 0x001b4070U;
}
static inline u32 perf_pmasys_mem_block_base_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 perf_pmasys_mem_block_target_f(u32 v)
{
return (v & 0x3U) << 28U;
}
static inline u32 perf_pmasys_mem_block_target_v(u32 r)
{
return (r >> 28U) & 0x3U;
}
static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
{
return 0x00000000U;
}
static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
{
return 0x0U;
}
static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
{
return 0x00000002U;
}
static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
{
return 0x20000000U;
}
static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
{
return 0x00000003U;
}
static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 perf_pmasys_mem_block_valid_true_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_mem_block_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 perf_pmasys_mem_block_valid_false_v(void)
{
return 0x00000000U;
}
static inline u32 perf_pmasys_mem_block_valid_false_f(void)
{
return 0x0U;
}
static inline u32 perf_pmasys_outbase_r(void)
{
return 0x001b4074U;
}
static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
{
return (v & 0x7ffffffU) << 5U;
}
static inline u32 perf_pmasys_outbaseupper_r(void)
{
return 0x001b4078U;
}
static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 perf_pmasys_outsize_r(void)
{
return 0x001b407cU;
}
static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
{
return (v & 0x7ffffffU) << 5U;
}
static inline u32 perf_pmasys_mem_bytes_r(void)
{
return 0x001b4084U;
}
static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 perf_pmasys_mem_bump_r(void)
{
return 0x001b4088U;
}
static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 perf_pmasys_enginestatus_r(void)
{
return 0x001b40a4U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
{
return 0x10U;
}
#define perf_pmasys_control_r() (0x001b4000U)
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)
#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U)
#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U)
#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U)
#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U)
#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U)
#define perf_pmasys_mem_block_r() (0x001b4070U)
#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U)
#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U)
#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U)
#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U)
#define perf_pmasys_mem_block_target_lfb_f() (0x0U)
#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U)
#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U)
#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U)
#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U)
#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U)
#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U)
#define perf_pmasys_mem_block_valid_true_v() (0x00000001U)
#define perf_pmasys_mem_block_valid_true_f() (0x80000000U)
#define perf_pmasys_mem_block_valid_false_v() (0x00000000U)
#define perf_pmasys_mem_block_valid_false_f() (0x0U)
#define perf_pmasys_outbase_r() (0x001b4074U)
#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U)
#define perf_pmasys_outbaseupper_r() (0x001b4078U)
#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U)
#define perf_pmasys_outsize_r() (0x001b407cU)
#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U)
#define perf_pmasys_mem_bytes_r() (0x001b4084U)
#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U)
#define perf_pmasys_mem_bump_r() (0x001b4088U)
#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U)
#define perf_pmasys_enginestatus_r() (0x001b40a4U)
#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U)
#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U)
#endif

8
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pram_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,8 +59,6 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pram_data032_r(u32 i)
{
return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U));
}
#define pram_data032_r(i)\
(nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U)))
#endif

129
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,104 +59,31 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringmaster_command_r(void)
{
return 0x0012004cU;
}
static inline u32 pri_ringmaster_command_cmd_m(void)
{
return U32(0x3fU) << 0U;
}
static inline u32 pri_ringmaster_command_cmd_v(u32 r)
{
return (r >> 0U) & 0x3fU;
}
static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
{
return 0x00000000U;
}
static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
{
return 0x1U;
}
static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
{
return 0x2U;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
{
return 0x3U;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
{
return 0x0U;
}
static inline u32 pri_ringmaster_command_data_r(void)
{
return 0x00120048U;
}
static inline u32 pri_ringmaster_start_results_r(void)
{
return 0x00120050U;
}
static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
{
return 0x00000001U;
}
static inline u32 pri_ringmaster_intr_status0_r(void)
{
return 0x00120058U;
}
static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
{
return (r >> 8U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status1_r(void)
{
return 0x0012005cU;
}
static inline u32 pri_ringmaster_global_ctl_r(void)
{
return 0x00120060U;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
{
return 0x1U;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
{
return 0x0U;
}
static inline u32 pri_ringmaster_enum_fbp_r(void)
{
return 0x00120074U;
}
static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 pri_ringmaster_enum_gpc_r(void)
{
return 0x00120078U;
}
static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
#define pri_ringmaster_command_r() (0x0012004cU)
#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U)
#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU)
#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U)
#define pri_ringmaster_command_cmd_start_ring_f() (0x1U)
#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U)
#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U)
#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U)
#define pri_ringmaster_command_data_r() (0x00120048U)
#define pri_ringmaster_start_results_r() (0x00120050U)
#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U)
#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U)
#define pri_ringmaster_intr_status0_r() (0x00120058U)
#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\
(((r) >> 0U) & 0x1U)
#define pri_ringmaster_intr_status0_disconnect_fault_v(r) (((r) >> 1U) & 0x1U)
#define pri_ringmaster_intr_status0_overflow_fault_v(r) (((r) >> 2U) & 0x1U)
#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\
(((r) >> 8U) & 0x1U)
#define pri_ringmaster_intr_status1_r() (0x0012005cU)
#define pri_ringmaster_global_ctl_r() (0x00120060U)
#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U)
#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U)
#define pri_ringmaster_enum_fbp_r() (0x00120074U)
#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU)
#define pri_ringmaster_enum_gpc_r() (0x00120078U)
#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU)
#endif

28
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,24 +59,10 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
{
return nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
{
return 0x00128120U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
{
return 0x00128124U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
{
return 0x00128128U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
{
return 0x0012812cU;
}
#define pri_ringstation_gpc_master_config_r(i)\
(nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32((i), 4U)))
#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U)
#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U)
#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U)
#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU)
#endif

44
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,36 +59,14 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringstation_sys_master_config_r(u32 i)
{
return nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 pri_ringstation_sys_decode_config_r(void)
{
return 0x00122204U;
}
static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
{
return U32(0x7U) << 0U;
}
static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
{
return 0x1U;
}
static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
{
return 0x00122120U;
}
static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
{
return 0x00122124U;
}
static inline u32 pri_ringstation_sys_priv_error_info_r(void)
{
return 0x00122128U;
}
static inline u32 pri_ringstation_sys_priv_error_code_r(void)
{
return 0x0012212cU;
}
#define pri_ringstation_sys_master_config_r(i)\
(nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32((i), 4U)))
#define pri_ringstation_sys_decode_config_r() (0x00122204U)
#define pri_ringstation_sys_decode_config_ring_m() (U32(0x7U) << 0U)
#define pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()\
(0x1U)
#define pri_ringstation_sys_priv_error_adr_r() (0x00122120U)
#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U)
#define pri_ringstation_sys_priv_error_info_r() (0x00122128U)
#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU)
#endif

137
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_proj_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,112 +59,31 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 proj_gpc_base_v(void)
{
return 0x00500000U;
}
static inline u32 proj_gpc_shared_base_v(void)
{
return 0x00418000U;
}
static inline u32 proj_gpc_stride_v(void)
{
return 0x00008000U;
}
static inline u32 proj_gpc_priv_stride_v(void)
{
return 0x00000800U;
}
static inline u32 proj_ltc_stride_v(void)
{
return 0x00002000U;
}
static inline u32 proj_lts_stride_v(void)
{
return 0x00000400U;
}
static inline u32 proj_fbpa_stride_v(void)
{
return 0x00001000U;
}
static inline u32 proj_ppc_in_gpc_base_v(void)
{
return 0x00003000U;
}
static inline u32 proj_ppc_in_gpc_shared_base_v(void)
{
return 0x00003e00U;
}
static inline u32 proj_ppc_in_gpc_stride_v(void)
{
return 0x00000200U;
}
static inline u32 proj_rop_base_v(void)
{
return 0x00410000U;
}
static inline u32 proj_rop_shared_base_v(void)
{
return 0x00408800U;
}
static inline u32 proj_rop_stride_v(void)
{
return 0x00000400U;
}
static inline u32 proj_tpc_in_gpc_base_v(void)
{
return 0x00004000U;
}
static inline u32 proj_tpc_in_gpc_stride_v(void)
{
return 0x00000800U;
}
static inline u32 proj_tpc_in_gpc_shared_base_v(void)
{
return 0x00001800U;
}
static inline u32 proj_host_num_engines_v(void)
{
return 0x00000002U;
}
static inline u32 proj_host_num_pbdma_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_fbps_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_fbpas_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_gpcs_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_zcull_banks_v(void)
{
return 0x00000004U;
}
static inline u32 proj_scal_max_gpcs_v(void)
{
return 0x00000020U;
}
static inline u32 proj_scal_max_tpc_per_gpc_v(void)
{
return 0x00000008U;
}
#define proj_gpc_base_v() (0x00500000U)
#define proj_gpc_shared_base_v() (0x00418000U)
#define proj_gpc_stride_v() (0x00008000U)
#define proj_gpc_priv_stride_v() (0x00000800U)
#define proj_ltc_stride_v() (0x00002000U)
#define proj_lts_stride_v() (0x00000400U)
#define proj_fbpa_stride_v() (0x00001000U)
#define proj_ppc_in_gpc_base_v() (0x00003000U)
#define proj_ppc_in_gpc_shared_base_v() (0x00003e00U)
#define proj_ppc_in_gpc_stride_v() (0x00000200U)
#define proj_rop_base_v() (0x00410000U)
#define proj_rop_shared_base_v() (0x00408800U)
#define proj_rop_stride_v() (0x00000400U)
#define proj_tpc_in_gpc_base_v() (0x00004000U)
#define proj_tpc_in_gpc_stride_v() (0x00000800U)
#define proj_tpc_in_gpc_shared_base_v() (0x00001800U)
#define proj_host_num_engines_v() (0x00000002U)
#define proj_host_num_pbdma_v() (0x00000001U)
#define proj_scal_litter_num_tpc_per_gpc_v() (0x00000001U)
#define proj_scal_litter_num_fbps_v() (0x00000001U)
#define proj_scal_litter_num_fbpas_v() (0x00000001U)
#define proj_scal_litter_num_gpcs_v() (0x00000001U)
#define proj_scal_litter_num_pes_per_gpc_v() (0x00000001U)
#define proj_scal_litter_num_tpcs_per_pes_v() (0x00000001U)
#define proj_scal_litter_num_zcull_banks_v() (0x00000004U)
#define proj_scal_max_gpcs_v() (0x00000020U)
#define proj_scal_max_tpc_per_gpc_v() (0x00000008U)
#endif

1009
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
View File

File diff suppressed because it is too large Load Diff

492
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ram_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,396 +59,102 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ram_in_ramfc_s(void)
{
return 4096U;
}
static inline u32 ram_in_ramfc_w(void)
{
return 0U;
}
static inline u32 ram_in_page_dir_base_target_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ram_in_page_dir_base_target_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 ram_in_page_dir_base_vol_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_vol_true_f(void)
{
return 0x4U;
}
static inline u32 ram_in_page_dir_base_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_page_dir_base_lo_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_hi_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 ram_in_page_dir_base_hi_w(void)
{
return 129U;
}
static inline u32 ram_in_adr_limit_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_adr_limit_lo_w(void)
{
return 130U;
}
static inline u32 ram_in_adr_limit_hi_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 ram_in_adr_limit_hi_w(void)
{
return 131U;
}
static inline u32 ram_in_engine_cs_w(void)
{
return 132U;
}
static inline u32 ram_in_engine_cs_wfi_v(void)
{
return 0x00000000U;
}
static inline u32 ram_in_engine_cs_wfi_f(void)
{
return 0x0U;
}
static inline u32 ram_in_engine_cs_fg_v(void)
{
return 0x00000001U;
}
static inline u32 ram_in_engine_cs_fg_f(void)
{
return 0x8U;
}
static inline u32 ram_in_gr_cs_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_cs_wfi_f(void)
{
return 0x0U;
}
static inline u32 ram_in_gr_wfi_target_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_wfi_mode_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_wfi_mode_physical_v(void)
{
return 0x00000000U;
}
static inline u32 ram_in_gr_wfi_mode_physical_f(void)
{
return 0x0U;
}
static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
{
return 0x00000001U;
}
static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
{
return 0x4U;
}
static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
{
return 133U;
}
static inline u32 ram_in_base_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 ram_in_alloc_size_v(void)
{
return 0x00001000U;
}
static inline u32 ram_fc_size_val_v(void)
{
return 0x00000200U;
}
static inline u32 ram_fc_gp_put_w(void)
{
return 0U;
}
static inline u32 ram_fc_userd_w(void)
{
return 2U;
}
static inline u32 ram_fc_userd_hi_w(void)
{
return 3U;
}
static inline u32 ram_fc_signature_w(void)
{
return 4U;
}
static inline u32 ram_fc_gp_get_w(void)
{
return 5U;
}
static inline u32 ram_fc_pb_get_w(void)
{
return 6U;
}
static inline u32 ram_fc_pb_get_hi_w(void)
{
return 7U;
}
static inline u32 ram_fc_pb_top_level_get_w(void)
{
return 8U;
}
static inline u32 ram_fc_pb_top_level_get_hi_w(void)
{
return 9U;
}
static inline u32 ram_fc_acquire_w(void)
{
return 12U;
}
static inline u32 ram_fc_semaphorea_w(void)
{
return 14U;
}
static inline u32 ram_fc_semaphoreb_w(void)
{
return 15U;
}
static inline u32 ram_fc_semaphorec_w(void)
{
return 16U;
}
static inline u32 ram_fc_semaphored_w(void)
{
return 17U;
}
static inline u32 ram_fc_gp_base_w(void)
{
return 18U;
}
static inline u32 ram_fc_gp_base_hi_w(void)
{
return 19U;
}
static inline u32 ram_fc_gp_fetch_w(void)
{
return 20U;
}
static inline u32 ram_fc_pb_fetch_w(void)
{
return 21U;
}
static inline u32 ram_fc_pb_fetch_hi_w(void)
{
return 22U;
}
static inline u32 ram_fc_pb_put_w(void)
{
return 23U;
}
static inline u32 ram_fc_pb_put_hi_w(void)
{
return 24U;
}
static inline u32 ram_fc_pb_header_w(void)
{
return 33U;
}
static inline u32 ram_fc_pb_count_w(void)
{
return 34U;
}
static inline u32 ram_fc_subdevice_w(void)
{
return 37U;
}
static inline u32 ram_fc_formats_w(void)
{
return 39U;
}
static inline u32 ram_fc_syncpointa_w(void)
{
return 41U;
}
static inline u32 ram_fc_syncpointb_w(void)
{
return 42U;
}
static inline u32 ram_fc_target_w(void)
{
return 43U;
}
static inline u32 ram_fc_hce_ctrl_w(void)
{
return 57U;
}
static inline u32 ram_fc_chid_w(void)
{
return 58U;
}
static inline u32 ram_fc_chid_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 ram_fc_chid_id_w(void)
{
return 0U;
}
static inline u32 ram_fc_runlist_timeslice_w(void)
{
return 62U;
}
static inline u32 ram_fc_pb_timeslice_w(void)
{
return 63U;
}
static inline u32 ram_userd_base_shift_v(void)
{
return 0x00000009U;
}
static inline u32 ram_userd_chan_size_v(void)
{
return 0x00000200U;
}
static inline u32 ram_userd_put_w(void)
{
return 16U;
}
static inline u32 ram_userd_get_w(void)
{
return 17U;
}
static inline u32 ram_userd_ref_w(void)
{
return 18U;
}
static inline u32 ram_userd_put_hi_w(void)
{
return 19U;
}
static inline u32 ram_userd_ref_threshold_w(void)
{
return 20U;
}
static inline u32 ram_userd_top_level_get_w(void)
{
return 22U;
}
static inline u32 ram_userd_top_level_get_hi_w(void)
{
return 23U;
}
static inline u32 ram_userd_get_hi_w(void)
{
return 24U;
}
static inline u32 ram_userd_gp_get_w(void)
{
return 34U;
}
static inline u32 ram_userd_gp_put_w(void)
{
return 35U;
}
static inline u32 ram_userd_gp_top_level_get_w(void)
{
return 22U;
}
static inline u32 ram_userd_gp_top_level_get_hi_w(void)
{
return 23U;
}
static inline u32 ram_rl_entry_size_v(void)
{
return 0x00000008U;
}
static inline u32 ram_rl_entry_chid_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 ram_rl_entry_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 ram_rl_entry_type_f(u32 v)
{
return (v & 0x1U) << 13U;
}
static inline u32 ram_rl_entry_type_chid_f(void)
{
return 0x0U;
}
static inline u32 ram_rl_entry_type_tsg_f(void)
{
return 0x2000U;
}
static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
{
return (v & 0xfU) << 14U;
}
static inline u32 ram_rl_entry_timeslice_scale_v(u32 r)
{
return (r >> 14U) & 0xfU;
}
static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
{
return 0xc000U;
}
static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
{
return (v & 0xffU) << 18U;
}
static inline u32 ram_rl_entry_timeslice_timeout_v(u32 r)
{
return (r >> 18U) & 0xffU;
}
static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
{
return 0x2000000U;
}
static inline u32 ram_rl_entry_tsg_length_f(u32 v)
{
return (v & 0x3fU) << 26U;
}
#define ram_in_ramfc_s() (4096U)
#define ram_in_ramfc_w() (0U)
#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U)
#define ram_in_page_dir_base_target_w() (128U)
#define ram_in_page_dir_base_target_vid_mem_f() (0x0U)
#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U)
#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U)
#define ram_in_page_dir_base_vol_w() (128U)
#define ram_in_page_dir_base_vol_true_f() (0x4U)
#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U)
#define ram_in_page_dir_base_lo_w() (128U)
#define ram_in_page_dir_base_hi_f(v) (((v)&0xffU) << 0U)
#define ram_in_page_dir_base_hi_w() (129U)
#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U)
#define ram_in_adr_limit_lo_w() (130U)
#define ram_in_adr_limit_hi_f(v) (((v)&0xffU) << 0U)
#define ram_in_adr_limit_hi_w() (131U)
#define ram_in_engine_cs_w() (132U)
#define ram_in_engine_cs_wfi_v() (0x00000000U)
#define ram_in_engine_cs_wfi_f() (0x0U)
#define ram_in_engine_cs_fg_v() (0x00000001U)
#define ram_in_engine_cs_fg_f() (0x8U)
#define ram_in_gr_cs_w() (132U)
#define ram_in_gr_cs_wfi_f() (0x0U)
#define ram_in_gr_wfi_target_w() (132U)
#define ram_in_gr_wfi_mode_w() (132U)
#define ram_in_gr_wfi_mode_physical_v() (0x00000000U)
#define ram_in_gr_wfi_mode_physical_f() (0x0U)
#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U)
#define ram_in_gr_wfi_mode_virtual_f() (0x4U)
#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U)
#define ram_in_gr_wfi_ptr_lo_w() (132U)
#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U)
#define ram_in_gr_wfi_ptr_hi_w() (133U)
#define ram_in_base_shift_v() (0x0000000cU)
#define ram_in_alloc_size_v() (0x00001000U)
#define ram_fc_size_val_v() (0x00000200U)
#define ram_fc_gp_put_w() (0U)
#define ram_fc_userd_w() (2U)
#define ram_fc_userd_hi_w() (3U)
#define ram_fc_signature_w() (4U)
#define ram_fc_gp_get_w() (5U)
#define ram_fc_pb_get_w() (6U)
#define ram_fc_pb_get_hi_w() (7U)
#define ram_fc_pb_top_level_get_w() (8U)
#define ram_fc_pb_top_level_get_hi_w() (9U)
#define ram_fc_acquire_w() (12U)
#define ram_fc_semaphorea_w() (14U)
#define ram_fc_semaphoreb_w() (15U)
#define ram_fc_semaphorec_w() (16U)
#define ram_fc_semaphored_w() (17U)
#define ram_fc_gp_base_w() (18U)
#define ram_fc_gp_base_hi_w() (19U)
#define ram_fc_gp_fetch_w() (20U)
#define ram_fc_pb_fetch_w() (21U)
#define ram_fc_pb_fetch_hi_w() (22U)
#define ram_fc_pb_put_w() (23U)
#define ram_fc_pb_put_hi_w() (24U)
#define ram_fc_pb_header_w() (33U)
#define ram_fc_pb_count_w() (34U)
#define ram_fc_subdevice_w() (37U)
#define ram_fc_formats_w() (39U)
#define ram_fc_syncpointa_w() (41U)
#define ram_fc_syncpointb_w() (42U)
#define ram_fc_target_w() (43U)
#define ram_fc_hce_ctrl_w() (57U)
#define ram_fc_chid_w() (58U)
#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U)
#define ram_fc_chid_id_w() (0U)
#define ram_fc_runlist_timeslice_w() (62U)
#define ram_fc_pb_timeslice_w() (63U)
#define ram_userd_base_shift_v() (0x00000009U)
#define ram_userd_chan_size_v() (0x00000200U)
#define ram_userd_put_w() (16U)
#define ram_userd_get_w() (17U)
#define ram_userd_ref_w() (18U)
#define ram_userd_put_hi_w() (19U)
#define ram_userd_ref_threshold_w() (20U)
#define ram_userd_top_level_get_w() (22U)
#define ram_userd_top_level_get_hi_w() (23U)
#define ram_userd_get_hi_w() (24U)
#define ram_userd_gp_get_w() (34U)
#define ram_userd_gp_put_w() (35U)
#define ram_userd_gp_top_level_get_w() (22U)
#define ram_userd_gp_top_level_get_hi_w() (23U)
#define ram_rl_entry_size_v() (0x00000008U)
#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U)
#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U)
#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U)
#define ram_rl_entry_type_chid_f() (0x0U)
#define ram_rl_entry_type_tsg_f() (0x2000U)
#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U)
#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU)
#define ram_rl_entry_timeslice_scale_3_f() (0xc000U)
#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U)
#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU)
#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U)
#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U)
#endif

391
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_therm_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,312 +59,85 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 therm_use_a_r(void)
{
return 0x00020798U;
}
static inline u32 therm_use_a_ext_therm_0_enable_f(void)
{
return 0x1U;
}
static inline u32 therm_use_a_ext_therm_1_enable_f(void)
{
return 0x2U;
}
static inline u32 therm_use_a_ext_therm_2_enable_f(void)
{
return 0x4U;
}
static inline u32 therm_evt_ext_therm_0_r(void)
{
return 0x00020700U;
}
static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
{
return (v & 0x3fU) << 8U;
}
static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
{
return 0x00000000U;
}
static inline u32 therm_evt_ext_therm_0_priority_f(u32 v)
{
return (v & 0x1fU) << 24U;
}
static inline u32 therm_evt_ext_therm_1_r(void)
{
return 0x00020704U;
}
static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
{
return (v & 0x3fU) << 8U;
}
static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
{
return 0x00000000U;
}
static inline u32 therm_evt_ext_therm_1_priority_f(u32 v)
{
return (v & 0x1fU) << 24U;
}
static inline u32 therm_evt_ext_therm_2_r(void)
{
return 0x00020708U;
}
static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
{
return (v & 0x3fU) << 8U;
}
static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
{
return 0x00000000U;
}
static inline u32 therm_evt_ext_therm_2_priority_f(u32 v)
{
return (v & 0x1fU) << 24U;
}
static inline u32 therm_weight_1_r(void)
{
return 0x00020024U;
}
static inline u32 therm_config1_r(void)
{
return 0x00020050U;
}
static inline u32 therm_config2_r(void)
{
return 0x00020130U;
}
static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 therm_config2_grad_enable_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 therm_gate_ctrl_r(u32 i)
{
return nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 therm_gate_ctrl_eng_clk_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
{
return 0x0U;
}
static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
{
return 0x1U;
}
static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
{
return 0x2U;
}
static inline u32 therm_gate_ctrl_blk_clk_m(void)
{
return U32(0x3U) << 2U;
}
static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
{
return 0x0U;
}
static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
{
return 0x4U;
}
static inline u32 therm_gate_ctrl_eng_pwr_m(void)
{
return U32(0x3U) << 4U;
}
static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
{
return 0x10U;
}
static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
{
return 0x00000002U;
}
static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
{
return 0x20U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
{
return (v & 0x1fU) << 8U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
{
return U32(0x1fU) << 8U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
{
return (v & 0x7U) << 13U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
{
return U32(0x7U) << 13U;
}
static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
{
return (v & 0xfU) << 16U;
}
static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
{
return U32(0xfU) << 16U;
}
static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
{
return (v & 0xfU) << 20U;
}
static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
{
return U32(0xfU) << 20U;
}
static inline u32 therm_fecs_idle_filter_r(void)
{
return 0x00020288U;
}
static inline u32 therm_fecs_idle_filter_value_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 therm_hubmmu_idle_filter_r(void)
{
return 0x0002028cU;
}
static inline u32 therm_hubmmu_idle_filter_value_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 therm_clk_slowdown_r(u32 i)
{
return nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
{
return (v & 0x3fU) << 16U;
}
static inline u32 therm_clk_slowdown_idle_factor_m(void)
{
return U32(0x3fU) << 16U;
}
static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
{
return (r >> 16U) & 0x3fU;
}
static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
{
return 0x0U;
}
static inline u32 therm_grad_stepping_table_r(u32 i)
{
return nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
{
return (v & 0x3fU) << 0U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
{
return U32(0x3fU) << 0U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
{
return 0x1U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
{
return 0x2U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
{
return 0x6U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
{
return 0xeU;
}
static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
{
return (v & 0x3fU) << 6U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
{
return U32(0x3fU) << 6U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
{
return (v & 0x3fU) << 12U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
{
return U32(0x3fU) << 12U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
{
return (v & 0x3fU) << 18U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
{
return U32(0x3fU) << 18U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
{
return (v & 0x3fU) << 24U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
{
return U32(0x3fU) << 24U;
}
static inline u32 therm_grad_stepping0_r(void)
{
return 0x000202c0U;
}
static inline u32 therm_grad_stepping0_feature_s(void)
{
return 1U;
}
static inline u32 therm_grad_stepping0_feature_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 therm_grad_stepping0_feature_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 therm_grad_stepping0_feature_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 therm_grad_stepping0_feature_enable_f(void)
{
return 0x1U;
}
static inline u32 therm_grad_stepping1_r(void)
{
return 0x000202c4U;
}
static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
{
return (v & 0x1ffffU) << 0U;
}
static inline u32 therm_clk_timing_r(u32 i)
{
return nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 therm_clk_timing_grad_slowdown_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
{
return 0x10000U;
}
#define therm_use_a_r() (0x00020798U)
#define therm_use_a_ext_therm_0_enable_f() (0x1U)
#define therm_use_a_ext_therm_1_enable_f() (0x2U)
#define therm_use_a_ext_therm_2_enable_f() (0x4U)
#define therm_evt_ext_therm_0_r() (0x00020700U)
#define therm_evt_ext_therm_0_slow_factor_f(v) (((v)&0x3fU) << 8U)
#define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000000U)
#define therm_evt_ext_therm_0_priority_f(v) (((v)&0x1fU) << 24U)
#define therm_evt_ext_therm_1_r() (0x00020704U)
#define therm_evt_ext_therm_1_slow_factor_f(v) (((v)&0x3fU) << 8U)
#define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000000U)
#define therm_evt_ext_therm_1_priority_f(v) (((v)&0x1fU) << 24U)
#define therm_evt_ext_therm_2_r() (0x00020708U)
#define therm_evt_ext_therm_2_slow_factor_f(v) (((v)&0x3fU) << 8U)
#define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000000U)
#define therm_evt_ext_therm_2_priority_f(v) (((v)&0x1fU) << 24U)
#define therm_weight_1_r() (0x00020024U)
#define therm_config1_r() (0x00020050U)
#define therm_config2_r() (0x00020130U)
#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U)
#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U)
#define therm_gate_ctrl_r(i)\
(nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U)
#define therm_gate_ctrl_eng_clk_run_f() (0x0U)
#define therm_gate_ctrl_eng_clk_auto_f() (0x1U)
#define therm_gate_ctrl_eng_clk_stop_f() (0x2U)
#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U)
#define therm_gate_ctrl_blk_clk_run_f() (0x0U)
#define therm_gate_ctrl_blk_clk_auto_f() (0x4U)
#define therm_gate_ctrl_eng_pwr_m() (U32(0x3U) << 4U)
#define therm_gate_ctrl_eng_pwr_auto_f() (0x10U)
#define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U)
#define therm_gate_ctrl_eng_pwr_off_f() (0x20U)
#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U)
#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U)
#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U)
#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U)
#define therm_fecs_idle_filter_r() (0x00020288U)
#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U)
#define therm_hubmmu_idle_filter_r() (0x0002028cU)
#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U)
#define therm_clk_slowdown_r(i)\
(nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU)
#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U)
#define therm_grad_stepping_table_r(i)\
(nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU)
#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U)
#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U)
#define therm_grad_stepping0_r() (0x000202c0U)
#define therm_grad_stepping0_feature_s() (1U)
#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U)
#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U)
#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U)
#define therm_grad_stepping0_feature_enable_f() (0x1U)
#define therm_grad_stepping1_r() (0x000202c4U)
#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U)
#define therm_clk_timing_r(i)\
(nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U)
#endif

87
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,72 +59,21 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 timer_pri_timeout_r(void)
{
return 0x00009080U;
}
static inline u32 timer_pri_timeout_period_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 timer_pri_timeout_period_m(void)
{
return U32(0xffffffU) << 0U;
}
static inline u32 timer_pri_timeout_period_v(u32 r)
{
return (r >> 0U) & 0xffffffU;
}
static inline u32 timer_pri_timeout_en_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 timer_pri_timeout_en_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 timer_pri_timeout_en_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 timer_pri_timeout_en_en_enabled_f(void)
{
return 0x80000000U;
}
static inline u32 timer_pri_timeout_en_en_disabled_f(void)
{
return 0x0U;
}
static inline u32 timer_pri_timeout_save_0_r(void)
{
return 0x00009084U;
}
static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 timer_pri_timeout_save_0_addr_v(u32 r)
{
return (r >> 2U) & 0x3fffffU;
}
static inline u32 timer_pri_timeout_save_0_write_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 timer_pri_timeout_save_1_r(void)
{
return 0x00009088U;
}
static inline u32 timer_pri_timeout_fecs_errcode_r(void)
{
return 0x0000908cU;
}
static inline u32 timer_time_0_r(void)
{
return 0x00009400U;
}
static inline u32 timer_time_1_r(void)
{
return 0x00009410U;
}
#define timer_pri_timeout_r() (0x00009080U)
#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U)
#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U)
#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU)
#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U)
#define timer_pri_timeout_en_m() (U32(0x1U) << 31U)
#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U)
#define timer_pri_timeout_en_en_enabled_f() (0x80000000U)
#define timer_pri_timeout_en_en_disabled_f() (0x0U)
#define timer_pri_timeout_save_0_r() (0x00009084U)
#define timer_pri_timeout_save_0_fecs_tgt_v(r) (((r) >> 31U) & 0x1U)
#define timer_pri_timeout_save_0_addr_v(r) (((r) >> 2U) & 0x3fffffU)
#define timer_pri_timeout_save_0_write_v(r) (((r) >> 1U) & 0x1U)
#define timer_pri_timeout_save_1_r() (0x00009088U)
#define timer_pri_timeout_fecs_errcode_r() (0x0000908cU)
#define timer_time_0_r() (0x00009400U)
#define timer_time_1_r() (0x00009410U)
#endif

198
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_top_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,160 +59,44 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 top_num_gpcs_r(void)
{
return 0x00022430U;
}
static inline u32 top_num_gpcs_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_tpc_per_gpc_r(void)
{
return 0x00022434U;
}
static inline u32 top_tpc_per_gpc_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_num_fbps_r(void)
{
return 0x00022438U;
}
static inline u32 top_num_fbps_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_device_info_r(u32 i)
{
return nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 top_device_info__size_1_v(void)
{
return 0x00000040U;
}
static inline u32 top_device_info_chain_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 top_device_info_chain_enable_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_chain_disable_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_engine_enum_v(u32 r)
{
return (r >> 26U) & 0xfU;
}
static inline u32 top_device_info_runlist_enum_v(u32 r)
{
return (r >> 21U) & 0xfU;
}
static inline u32 top_device_info_intr_enum_v(u32 r)
{
return (r >> 15U) & 0x1fU;
}
static inline u32 top_device_info_reset_enum_v(u32 r)
{
return (r >> 9U) & 0x1fU;
}
static inline u32 top_device_info_type_enum_v(u32 r)
{
return (r >> 2U) & 0x1fffffffU;
}
static inline u32 top_device_info_type_enum_graphics_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_type_enum_graphics_f(void)
{
return 0x0U;
}
static inline u32 top_device_info_type_enum_copy0_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_type_enum_copy0_f(void)
{
return 0x4U;
}
static inline u32 top_device_info_type_enum_copy1_v(void)
{
return 0x00000002U;
}
static inline u32 top_device_info_type_enum_copy1_f(void)
{
return 0x8U;
}
static inline u32 top_device_info_type_enum_copy2_v(void)
{
return 0x00000003U;
}
static inline u32 top_device_info_type_enum_copy2_f(void)
{
return 0xcU;
}
static inline u32 top_device_info_engine_v(u32 r)
{
return (r >> 5U) & 0x1U;
}
static inline u32 top_device_info_runlist_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 top_device_info_intr_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 top_device_info_reset_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 top_device_info_entry_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 top_device_info_entry_not_valid_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_entry_enum_v(void)
{
return 0x00000002U;
}
static inline u32 top_device_info_entry_engine_type_v(void)
{
return 0x00000003U;
}
static inline u32 top_device_info_entry_data_v(void)
{
return 0x00000001U;
}
static inline u32 top_fs_status_fbp_r(void)
{
return 0x00022548U;
}
static inline u32 top_fs_status_fbp_cluster_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 top_fs_status_fbp_cluster_enable_v(void)
{
return 0x00000000U;
}
static inline u32 top_fs_status_fbp_cluster_enable_f(void)
{
return 0x0U;
}
static inline u32 top_fs_status_fbp_cluster_disable_v(void)
{
return 0x00000001U;
}
static inline u32 top_fs_status_fbp_cluster_disable_f(void)
{
return 0x1U;
}
#define top_num_gpcs_r() (0x00022430U)
#define top_num_gpcs_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_tpc_per_gpc_r() (0x00022434U)
#define top_tpc_per_gpc_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_num_fbps_r() (0x00022438U)
#define top_num_fbps_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_device_info_r(i)\
(nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32((i), 4U)))
#define top_device_info__size_1_v() (0x00000040U)
#define top_device_info_chain_v(r) (((r) >> 31U) & 0x1U)
#define top_device_info_chain_enable_v() (0x00000001U)
#define top_device_info_chain_disable_v() (0x00000000U)
#define top_device_info_engine_enum_v(r) (((r) >> 26U) & 0xfU)
#define top_device_info_runlist_enum_v(r) (((r) >> 21U) & 0xfU)
#define top_device_info_intr_enum_v(r) (((r) >> 15U) & 0x1fU)
#define top_device_info_reset_enum_v(r) (((r) >> 9U) & 0x1fU)
#define top_device_info_type_enum_v(r) (((r) >> 2U) & 0x1fffffffU)
#define top_device_info_type_enum_graphics_v() (0x00000000U)
#define top_device_info_type_enum_graphics_f() (0x0U)
#define top_device_info_type_enum_copy0_v() (0x00000001U)
#define top_device_info_type_enum_copy0_f() (0x4U)
#define top_device_info_type_enum_copy1_v() (0x00000002U)
#define top_device_info_type_enum_copy1_f() (0x8U)
#define top_device_info_type_enum_copy2_v() (0x00000003U)
#define top_device_info_type_enum_copy2_f() (0xcU)
#define top_device_info_engine_v(r) (((r) >> 5U) & 0x1U)
#define top_device_info_runlist_v(r) (((r) >> 4U) & 0x1U)
#define top_device_info_intr_v(r) (((r) >> 3U) & 0x1U)
#define top_device_info_reset_v(r) (((r) >> 2U) & 0x1U)
#define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U)
#define top_device_info_entry_not_valid_v() (0x00000000U)
#define top_device_info_entry_enum_v() (0x00000002U)
#define top_device_info_entry_engine_type_v() (0x00000003U)
#define top_device_info_entry_data_v() (0x00000001U)
#define top_fs_status_fbp_r() (0x00022548U)
#define top_fs_status_fbp_cluster_v(r) (((r) >> 0U) & 0xffffU)
#define top_fs_status_fbp_cluster_enable_v() (0x00000000U)
#define top_fs_status_fbp_cluster_enable_f() (0x0U)
#define top_fs_status_fbp_cluster_disable_v() (0x00000001U)
#define top_fs_status_fbp_cluster_disable_f() (0x1U)
#endif

325
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_trim_gk20a.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,260 +59,71 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 trim_sys_gpcpll_cfg_r(void)
{
return 0x00137000U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
{
return 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
{
return 0x00000000U;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void)
{
return 0x10U;
}
static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r)
{
return (r >> 17U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void)
{
return 0x20000U;
}
static inline u32 trim_sys_gpcpll_coeff_r(void)
{
return 0x00137004U;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
{
return U32(0xffU) << 0U;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
{
return U32(0xffU) << 8U;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
{
return (r >> 8U) & 0xffU;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
{
return (v & 0x3fU) << 16U;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
{
return U32(0x3fU) << 16U;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
{
return (r >> 16U) & 0x3fU;
}
static inline u32 trim_sys_sel_vco_r(void)
{
return 0x00137100U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
{
return 0x00000000U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void)
{
return 0x1U;
}
static inline u32 trim_sys_gpc2clk_out_r(void)
{
return 0x00137250U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void)
{
return 6U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
{
return (v & 0x3fU) << 0U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
{
return U32(0x3fU) << 0U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
{
return (r >> 0U) & 0x3fU;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void)
{
return 0x3cU;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void)
{
return 6U;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v)
{
return (v & 0x3fU) << 8U;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
{
return U32(0x3fU) << 8U;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r)
{
return (r >> 8U) & 0x3fU;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
{
return 0x80000000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i)
{
return nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32(i, 512U));
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
{
return (v & 0x3fffU) << 0U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
{
return 0x10000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
{
return 0x100000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
{
return 0x1000000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i)
{
return nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32(i, 512U));
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r)
{
return (r >> 0U) & 0xfffffU;
}
static inline u32 trim_sys_gpcpll_cfg2_r(void)
{
return 0x0013700cU;
}
static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
{
return U32(0xffU) << 24U;
}
static inline u32 trim_sys_gpcpll_cfg3_r(void)
{
return 0x00137018U;
}
static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
{
return (v & 0xffU) << 16U;
}
static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
{
return U32(0xffU) << 16U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
{
return 0x0013701cU;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
{
return U32(0x1U) << 22U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
{
return 0x400000U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
{
return 0x80000000U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void)
{
return 0x0U;
}
static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void)
{
return 0x001328a0U;
}
static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r)
{
return (r >> 24U) & 0x1U;
}
#define trim_sys_gpcpll_cfg_r() (0x00137000U)
#define trim_sys_gpcpll_cfg_enable_m() (U32(0x1U) << 0U)
#define trim_sys_gpcpll_cfg_enable_v(r) (((r) >> 0U) & 0x1U)
#define trim_sys_gpcpll_cfg_enable_no_f() (0x0U)
#define trim_sys_gpcpll_cfg_enable_yes_f() (0x1U)
#define trim_sys_gpcpll_cfg_iddq_m() (U32(0x1U) << 1U)
#define trim_sys_gpcpll_cfg_iddq_v(r) (((r) >> 1U) & 0x1U)
#define trim_sys_gpcpll_cfg_iddq_power_on_v() (0x00000000U)
#define trim_sys_gpcpll_cfg_enb_lckdet_m() (U32(0x1U) << 4U)
#define trim_sys_gpcpll_cfg_enb_lckdet_power_on_f() (0x0U)
#define trim_sys_gpcpll_cfg_enb_lckdet_power_off_f() (0x10U)
#define trim_sys_gpcpll_cfg_pll_lock_v(r) (((r) >> 17U) & 0x1U)
#define trim_sys_gpcpll_cfg_pll_lock_true_f() (0x20000U)
#define trim_sys_gpcpll_coeff_r() (0x00137004U)
#define trim_sys_gpcpll_coeff_mdiv_f(v) (((v)&0xffU) << 0U)
#define trim_sys_gpcpll_coeff_mdiv_m() (U32(0xffU) << 0U)
#define trim_sys_gpcpll_coeff_mdiv_v(r) (((r) >> 0U) & 0xffU)
#define trim_sys_gpcpll_coeff_ndiv_f(v) (((v)&0xffU) << 8U)
#define trim_sys_gpcpll_coeff_ndiv_m() (U32(0xffU) << 8U)
#define trim_sys_gpcpll_coeff_ndiv_v(r) (((r) >> 8U) & 0xffU)
#define trim_sys_gpcpll_coeff_pldiv_f(v) (((v)&0x3fU) << 16U)
#define trim_sys_gpcpll_coeff_pldiv_m() (U32(0x3fU) << 16U)
#define trim_sys_gpcpll_coeff_pldiv_v(r) (((r) >> 16U) & 0x3fU)
#define trim_sys_sel_vco_r() (0x00137100U)
#define trim_sys_sel_vco_gpc2clk_out_m() (U32(0x1U) << 0U)
#define trim_sys_sel_vco_gpc2clk_out_init_v() (0x00000000U)
#define trim_sys_sel_vco_gpc2clk_out_init_f() (0x0U)
#define trim_sys_sel_vco_gpc2clk_out_bypass_f() (0x0U)
#define trim_sys_sel_vco_gpc2clk_out_vco_f() (0x1U)
#define trim_sys_gpc2clk_out_r() (0x00137250U)
#define trim_sys_gpc2clk_out_bypdiv_s() (6U)
#define trim_sys_gpc2clk_out_bypdiv_f(v) (((v)&0x3fU) << 0U)
#define trim_sys_gpc2clk_out_bypdiv_m() (U32(0x3fU) << 0U)
#define trim_sys_gpc2clk_out_bypdiv_v(r) (((r) >> 0U) & 0x3fU)
#define trim_sys_gpc2clk_out_bypdiv_by31_f() (0x3cU)
#define trim_sys_gpc2clk_out_vcodiv_s() (6U)
#define trim_sys_gpc2clk_out_vcodiv_f(v) (((v)&0x3fU) << 8U)
#define trim_sys_gpc2clk_out_vcodiv_m() (U32(0x3fU) << 8U)
#define trim_sys_gpc2clk_out_vcodiv_v(r) (((r) >> 8U) & 0x3fU)
#define trim_sys_gpc2clk_out_vcodiv_by1_f() (0x0U)
#define trim_sys_gpc2clk_out_sdiv14_m() (U32(0x1U) << 31U)
#define trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() (0x80000000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_r(i)\
(nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32((i), 512U)))
#define trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(v) (((v)&0x3fffU) << 0U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U)
#define trim_gpc_clk_cntr_ncgpcclk_cnt_r(i)\
(nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32((i), 512U)))
#define trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(r) (((r) >> 0U) & 0xfffffU)
#define trim_sys_gpcpll_cfg2_r() (0x0013700cU)
#define trim_sys_gpcpll_cfg2_pll_stepa_f(v) (((v)&0xffU) << 24U)
#define trim_sys_gpcpll_cfg2_pll_stepa_m() (U32(0xffU) << 24U)
#define trim_sys_gpcpll_cfg3_r() (0x00137018U)
#define trim_sys_gpcpll_cfg3_pll_stepb_f(v) (((v)&0xffU) << 16U)
#define trim_sys_gpcpll_cfg3_pll_stepb_m() (U32(0xffU) << 16U)
#define trim_sys_gpcpll_ndiv_slowdown_r() (0x0013701cU)
#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m() (U32(0x1U) << 22U)
#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f() (0x400000U)
#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f() (0x0U)
#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m() (U32(0x1U) << 31U)
#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f() (0x80000000U)
#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f() (0x0U)
#define trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r() (0x001328a0U)
#define trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(r)\
(((r) >> 24U) & 0x1U)
#endif

227
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,184 +59,49 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 bus_bar0_window_r(void)
{
return 0x00001700U;
}
static inline u32 bus_bar0_window_base_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 bus_bar0_window_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
{
return 0x2000000U;
}
static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
{
return 0x3000000U;
}
static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
{
return 0x00000010U;
}
static inline u32 bus_bar1_block_r(void)
{
return 0x00001704U;
}
static inline u32 bus_bar1_block_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 bus_bar1_block_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 bus_bar1_block_mode_virtual_f(void)
{
return 0x80000000U;
}
static inline u32 bus_bar2_block_r(void)
{
return 0x00001714U;
}
static inline u32 bus_bar2_block_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 bus_bar2_block_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 bus_bar2_block_mode_virtual_f(void)
{
return 0x80000000U;
}
static inline u32 bus_bar1_block_ptr_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 bus_bar2_block_ptr_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 bus_bind_status_r(void)
{
return 0x00001710U;
}
static inline u32 bus_bind_status_bar1_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 bus_bind_status_bar1_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar1_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
{
return 0x2U;
}
static inline u32 bus_bind_status_bar2_pending_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 bus_bind_status_bar2_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 bus_bind_status_bar2_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar2_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 bus_bind_status_bar2_pending_busy_f(void)
{
return 0x4U;
}
static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 bus_bind_status_bar2_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar2_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
{
return 0x8U;
}
static inline u32 bus_intr_0_r(void)
{
return 0x00001100U;
}
static inline u32 bus_intr_0_pri_squash_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 bus_intr_0_pri_fecserr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 bus_intr_0_pri_timeout_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 bus_intr_en_0_r(void)
{
return 0x00001140U;
}
static inline u32 bus_intr_en_0_pri_squash_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 bus_intr_en_0_pri_fecserr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 bus_intr_en_0_pri_timeout_m(void)
{
return U32(0x1U) << 3U;
}
#define bus_bar0_window_r() (0x00001700U)
#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U)
#define bus_bar0_window_target_vid_mem_f() (0x0U)
#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U)
#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U)
#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U)
#define bus_bar1_block_r() (0x00001704U)
#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define bus_bar1_block_target_vid_mem_f() (0x0U)
#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar1_block_mode_virtual_f() (0x80000000U)
#define bus_bar2_block_r() (0x00001714U)
#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define bus_bar2_block_target_vid_mem_f() (0x0U)
#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar2_block_mode_virtual_f() (0x80000000U)
#define bus_bar1_block_ptr_shift_v() (0x0000000cU)
#define bus_bar2_block_ptr_shift_v() (0x0000000cU)
#define bus_bind_status_r() (0x00001710U)
#define bus_bind_status_bar1_pending_v(r) (((r) >> 0U) & 0x1U)
#define bus_bind_status_bar1_pending_empty_f() (0x0U)
#define bus_bind_status_bar1_pending_busy_f() (0x1U)
#define bus_bind_status_bar1_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define bus_bind_status_bar1_outstanding_false_f() (0x0U)
#define bus_bind_status_bar1_outstanding_true_f() (0x2U)
#define bus_bind_status_bar2_pending_v(r) (((r) >> 2U) & 0x1U)
#define bus_bind_status_bar2_pending_empty_v() (0x00000000U)
#define bus_bind_status_bar2_pending_empty_f() (0x0U)
#define bus_bind_status_bar2_pending_busy_v() (0x00000001U)
#define bus_bind_status_bar2_pending_busy_f() (0x4U)
#define bus_bind_status_bar2_outstanding_v(r) (((r) >> 3U) & 0x1U)
#define bus_bind_status_bar2_outstanding_false_v() (0x00000000U)
#define bus_bind_status_bar2_outstanding_false_f() (0x0U)
#define bus_bind_status_bar2_outstanding_true_v() (0x00000001U)
#define bus_bind_status_bar2_outstanding_true_f() (0x8U)
#define bus_intr_0_r() (0x00001100U)
#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U)
#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U)
#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U)
#define bus_intr_en_0_r() (0x00001140U)
#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U)
#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U)
#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U)
#endif

184
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,148 +59,42 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ccsr_channel_inst_r(u32 i)
{
return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 ccsr_channel_inst__size_1_v(void)
{
return 0x00000200U;
}
static inline u32 ccsr_channel_inst_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 ccsr_channel_inst_bind_false_f(void)
{
return 0x0U;
}
static inline u32 ccsr_channel_inst_bind_true_f(void)
{
return 0x80000000U;
}
static inline u32 ccsr_channel_r(u32 i)
{
return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 ccsr_channel__size_1_v(void)
{
return 0x00000200U;
}
static inline u32 ccsr_channel_enable_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ccsr_channel_enable_in_use_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_enable_set_f(u32 v)
{
return (v & 0x1U) << 10U;
}
static inline u32 ccsr_channel_enable_set_true_f(void)
{
return 0x400U;
}
static inline u32 ccsr_channel_enable_clr_true_f(void)
{
return 0x800U;
}
static inline u32 ccsr_channel_status_v(u32 r)
{
return (r >> 24U) & 0xfU;
}
static inline u32 ccsr_channel_status_idle_v(void)
{
return 0x00000000U;
}
static inline u32 ccsr_channel_status_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
{
return 0x00000002U;
}
static inline u32 ccsr_channel_status_pending_acquire_v(void)
{
return 0x00000003U;
}
static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
{
return 0x00000004U;
}
static inline u32 ccsr_channel_status_on_pbdma_v(void)
{
return 0x00000005U;
}
static inline u32 ccsr_channel_status_on_pbdma_and_eng_v(void)
{
return 0x00000006U;
}
static inline u32 ccsr_channel_status_on_eng_v(void)
{
return 0x00000007U;
}
static inline u32 ccsr_channel_status_on_eng_pending_acquire_v(void)
{
return 0x00000008U;
}
static inline u32 ccsr_channel_status_on_eng_pending_v(void)
{
return 0x00000009U;
}
static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
{
return 0x0000000aU;
}
static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
{
return 0x0000000bU;
}
static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
{
return 0x0000000cU;
}
static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
{
return 0x0000000dU;
}
static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
{
return 0x0000000eU;
}
static inline u32 ccsr_channel_next_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 ccsr_channel_next_true_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
{
return 0x100U;
}
static inline u32 ccsr_channel_busy_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ccsr_channel_busy_true_v(void)
{
return 0x00000001U;
}
#define ccsr_channel_inst_r(i)\
(nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel_inst__size_1_v() (0x00000200U)
#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define ccsr_channel_inst_target_vid_mem_f() (0x0U)
#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U)
#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U)
#define ccsr_channel_inst_bind_false_f() (0x0U)
#define ccsr_channel_inst_bind_true_f() (0x80000000U)
#define ccsr_channel_r(i)\
(nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel__size_1_v() (0x00000200U)
#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U)
#define ccsr_channel_enable_in_use_v() (0x00000001U)
#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U)
#define ccsr_channel_enable_set_true_f() (0x400U)
#define ccsr_channel_enable_clr_true_f() (0x800U)
#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU)
#define ccsr_channel_status_idle_v() (0x00000000U)
#define ccsr_channel_status_pending_v() (0x00000001U)
#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U)
#define ccsr_channel_status_pending_acquire_v() (0x00000003U)
#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U)
#define ccsr_channel_status_on_pbdma_v() (0x00000005U)
#define ccsr_channel_status_on_pbdma_and_eng_v() (0x00000006U)
#define ccsr_channel_status_on_eng_v() (0x00000007U)
#define ccsr_channel_status_on_eng_pending_acquire_v() (0x00000008U)
#define ccsr_channel_status_on_eng_pending_v() (0x00000009U)
#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU)
#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU)
#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU)
#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU)
#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU)
#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U)
#define ccsr_channel_next_true_v() (0x00000001U)
#define ccsr_channel_force_ctx_reload_true_f() (0x100U)
#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U)
#define ccsr_channel_busy_true_v() (0x00000001U)
#endif

37
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,32 +59,11 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ce2_intr_status_r(void)
{
return 0x00106908U;
}
static inline u32 ce2_intr_status_blockpipe_pending_f(void)
{
return 0x1U;
}
static inline u32 ce2_intr_status_blockpipe_reset_f(void)
{
return 0x1U;
}
static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
{
return 0x2U;
}
static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
{
return 0x2U;
}
static inline u32 ce2_intr_status_launcherr_pending_f(void)
{
return 0x4U;
}
static inline u32 ce2_intr_status_launcherr_reset_f(void)
{
return 0x4U;
}
#define ce2_intr_status_r() (0x00106908U)
#define ce2_intr_status_blockpipe_pending_f() (0x1U)
#define ce2_intr_status_blockpipe_reset_f() (0x1U)
#define ce2_intr_status_nonblockpipe_pending_f() (0x2U)
#define ce2_intr_status_nonblockpipe_reset_f() (0x2U)
#define ce2_intr_status_launcherr_pending_f() (0x4U)
#define ce2_intr_status_launcherr_reset_f() (0x4U)
#endif

554
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,424 +59,136 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ctxsw_prog_fecs_header_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_gpccs_header_stride_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
{
return 0x00000008U;
}
static inline u32 ctxsw_prog_main_image_ctl_o(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_main_image_ctl_cde_enabled_f(void)
{
return 0x400U;
}
static inline u32 ctxsw_prog_main_image_ctl_cde_disabled_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_patch_count_o(void)
{
return 0x00000010U;
}
static inline u32 ctxsw_prog_main_image_context_id_o(void)
{
return 0x000000f0U;
}
static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
{
return 0x00000014U;
}
static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
{
return 0x00000018U;
}
static inline u32 ctxsw_prog_main_image_zcull_o(void)
{
return 0x0000001cU;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
{
return 0x00000001U;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
{
return 0x00000002U;
}
static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
{
return 0x00000020U;
}
static inline u32 ctxsw_prog_main_image_pm_o(void)
{
return 0x00000028U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
{
return U32(0x7U) << 0U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
{
return U32(0x7U) << 3U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
{
return 0x8U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pm_pc_sampling_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 ctxsw_prog_main_image_pm_pc_sampling_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
{
return 0x0000002cU;
}
static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
{
return 0x000000f4U;
}
static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
{
return 0x000000f8U;
}
static inline u32 ctxsw_prog_main_image_magic_value_o(void)
{
return 0x000000fcU;
}
static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
{
return 0x600dc0deU;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
{
return 0x000000f4U;
}
static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
{
return (r >> 16U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
{
return 0x000000f8U;
}
static inline u32 ctxsw_prog_local_magic_value_o(void)
{
return 0x000000fcU;
}
static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
{
return 0xad0becabU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
{
return 0x000000ecU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
{
return 0x00000000U;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
{
return 0x00000002U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
{
return 0x000000a0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
{
return 2U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
{
return 0x2U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
{
return 0x000000a4U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
{
return 0x000000a8U;
}
static inline u32 ctxsw_prog_main_image_misc_options_o(void)
{
return 0x0000003cU;
}
static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
{
return 0x000000acU;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
{
return 0x000000b0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
{
return U32(0xfffffffU) << 0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
{
return U32(0x3U) << 28U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
{
return 0x20000000U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
{
return 0x30000000U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
{
return 0x000000b4U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
{
return 0x00000080U;
}
static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
{
return 0x00000020U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
{
return 0x00000000U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
{
return 0x00000000U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
{
return 0x600dbeefU;
}
static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
{
return 0x00000008U;
}
static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void)
{
return 0x00000010U;
}
static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void)
{
return 0x00000014U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
{
return 0x00000018U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
{
return 0x0000001cU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
{
return (r >> 0U) & 0xffffffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
{
return U32(0xffU) << 24U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
{
return (r >> 24U) & 0xffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
{
return 0x00000001U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
{
return 0x1000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
{
return 0x00000002U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
{
return 0x2000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
{
return 0x0000000aU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
{
return 0xa000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
{
return 0x0000000bU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
{
return 0xb000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
{
return 0xc000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
{
return 0x0000000dU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
{
return 0xd000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
{
return 0x00000003U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
{
return 0x3000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
{
return 0x4000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
{
return 0x00000005U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
{
return 0x5000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
{
return 0x000000ffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
{
return 0xff000000U;
}
static inline u32 ctxsw_prog_main_image_preemption_options_o(void)
{
return 0x00000060U;
}
static inline u32 ctxsw_prog_main_image_preemption_options_control_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f(void)
{
return 0x1U;
}
#define ctxsw_prog_fecs_header_v() (0x00000100U)
#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U)
#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U)
#define ctxsw_prog_main_image_ctl_o() (0x0000000cU)
#define ctxsw_prog_main_image_ctl_cde_enabled_f() (0x400U)
#define ctxsw_prog_main_image_ctl_cde_disabled_f() (0x0U)
#define ctxsw_prog_main_image_patch_count_o() (0x00000010U)
#define ctxsw_prog_main_image_context_id_o() (0x000000f0U)
#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U)
#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U)
#define ctxsw_prog_main_image_zcull_o() (0x0000001cU)
#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U)
#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U)
#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U)
#define ctxsw_prog_main_image_pm_o() (0x00000028U)
#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U)
#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U)
#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U)
#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U)
#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U)
#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U)
#define ctxsw_prog_main_image_pm_pc_sampling_f(v) (((v)&0x1U) << 6U)
#define ctxsw_prog_main_image_pm_pc_sampling_m() (U32(0x1U) << 6U)
#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU)
#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U)
#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U)
#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU)
#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU)
#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU)
#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U)
#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU)
#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U)
#define ctxsw_prog_local_magic_value_o() (0x000000fcU)
#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU)
#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU)
#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU)
#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U)
#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U)
#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\
(0x00000000U)
#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\
(0x00000002U)
#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\
(((v)&0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\
(((r) >> 0U) & 0x3U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U)
#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U)
#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U)
#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU)
#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U)
#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\
(((v)&0xffffU) << 0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\
(U32(0xfffffffU) << 0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m()\
(U32(0x3U) << 28U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f()\
(0x0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f()\
(0x20000000U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f()\
(0x30000000U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\
(((v)&0xffffffffU) << 0U)
#define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U)
#define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U)
#define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U)
#define ctxsw_prog_record_timestamp_magic_value_lo_v_value_v() (0x00000000U)
#define ctxsw_prog_record_timestamp_magic_value_hi_o() (0x00000004U)
#define ctxsw_prog_record_timestamp_magic_value_hi_v_value_v() (0x600dbeefU)
#define ctxsw_prog_record_timestamp_context_id_o() (0x00000008U)
#define ctxsw_prog_record_timestamp_context_ptr_o() (0x0000000cU)
#define ctxsw_prog_record_timestamp_new_context_id_o() (0x00000010U)
#define ctxsw_prog_record_timestamp_new_context_ptr_o() (0x00000014U)
#define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U)
#define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v) (((v)&0xffffffU) << 0U)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\
(((r) >> 0U) & 0xffffffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v) (((v)&0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\
(0x00000001U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f()\
(0x1000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v() (0x00000002U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f() (0x2000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v()\
(0x0000000aU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f() (0xa000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v()\
(0x0000000bU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f()\
(0xb000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v()\
(0x0000000cU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f()\
(0xc000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v()\
(0x0000000dU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f()\
(0xd000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v() (0x00000003U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f() (0x3000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v()\
(0x00000004U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f()\
(0x4000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v()\
(0x00000005U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f()\
(0x5000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v()\
(0x000000ffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f()\
(0xff000000U)
#define ctxsw_prog_main_image_preemption_options_o() (0x00000060U)
#define ctxsw_prog_main_image_preemption_options_control_f(v) (((v)&0x3U) << 0U)
#define ctxsw_prog_main_image_preemption_options_control_cta_enabled_f() (0x1U)
#endif

697
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,556 +59,147 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 falcon_falcon_irqsset_r(void)
{
return 0x00000000U;
}
static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
{
return 0x40U;
}
static inline u32 falcon_falcon_irqsclr_r(void)
{
return 0x00000004U;
}
static inline u32 falcon_falcon_irqstat_r(void)
{
return 0x00000008U;
}
static inline u32 falcon_falcon_irqstat_halt_true_f(void)
{
return 0x10U;
}
static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
{
return 0x20U;
}
static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
{
return 0x40U;
}
static inline u32 falcon_falcon_irqmode_r(void)
{
return 0x0000000cU;
}
static inline u32 falcon_falcon_irqmset_r(void)
{
return 0x00000010U;
}
static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqmclr_r(void)
{
return 0x00000014U;
}
static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_irqmask_r(void)
{
return 0x00000018U;
}
static inline u32 falcon_falcon_irqdest_r(void)
{
return 0x0000001cU;
}
static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
{
return (v & 0x1U) << 17U;
}
static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
{
return (v & 0x1U) << 18U;
}
static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
{
return (v & 0x1U) << 19U;
}
static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
{
return (v & 0x1U) << 20U;
}
static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
{
return (v & 0x1U) << 21U;
}
static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
{
return (v & 0x1U) << 22U;
}
static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
{
return (v & 0x1U) << 23U;
}
static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 falcon_falcon_curctx_r(void)
{
return 0x00000050U;
}
static inline u32 falcon_falcon_nxtctx_r(void)
{
return 0x00000054U;
}
static inline u32 falcon_falcon_mailbox0_r(void)
{
return 0x00000040U;
}
static inline u32 falcon_falcon_mailbox1_r(void)
{
return 0x00000044U;
}
static inline u32 falcon_falcon_itfen_r(void)
{
return 0x00000048U;
}
static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
{
return 0x1U;
}
static inline u32 falcon_falcon_idlestate_r(void)
{
return 0x0000004cU;
}
static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
{
return (r >> 1U) & 0x7fffU;
}
static inline u32 falcon_falcon_os_r(void)
{
return 0x00000080U;
}
static inline u32 falcon_falcon_engctl_r(void)
{
return 0x000000a4U;
}
static inline u32 falcon_falcon_cpuctl_r(void)
{
return 0x00000100U;
}
static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 falcon_falcon_cpuctl_stopped_m(void)
{
return U32(0x1U) << 5U;
}
static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
{
return (r >> 6U) & 0x1U;
}
static inline u32 falcon_falcon_cpuctl_alias_r(void)
{
return 0x00000130U;
}
static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_imemc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_imemc_offs_f(u32 v)
{
return (v & 0x3fU) << 2U;
}
static inline u32 falcon_falcon_imemc_blk_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 falcon_falcon_imemc_secure_f(u32 v)
{
return (v & 0x1U) << 28U;
}
static inline u32 falcon_falcon_imemd_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_imemt_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_sctl_r(void)
{
return 0x00000240U;
}
static inline u32 falcon_falcon_mmu_phys_sec_r(void)
{
return 0x00100ce4U;
}
static inline u32 falcon_falcon_bootvec_r(void)
{
return 0x00000104U;
}
static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 falcon_falcon_dmactl_r(void)
{
return 0x0000010cU;
}
static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_hwcfg_r(void)
{
return 0x00000108U;
}
static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
{
return (r >> 0U) & 0x1ffU;
}
static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
{
return (r >> 9U) & 0x1ffU;
}
static inline u32 falcon_falcon_hwcfg1_r(void)
{
return 0x0000012cU;
}
static inline u32 falcon_falcon_hwcfg1_imem_ports_v(u32 r)
{
return (r >> 8U) & 0xfU;
}
static inline u32 falcon_falcon_hwcfg1_dmem_ports_v(u32 r)
{
return (r >> 12U) & 0xfU;
}
static inline u32 falcon_falcon_dmatrfbase_r(void)
{
return 0x00000110U;
}
static inline u32 falcon_falcon_dmatrfmoffs_r(void)
{
return 0x00000114U;
}
static inline u32 falcon_falcon_dmatrfcmd_r(void)
{
return 0x00000118U;
}
static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
{
return (v & 0x7U) << 8U;
}
static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
{
return (v & 0x7U) << 12U;
}
static inline u32 falcon_falcon_dmatrffboffs_r(void)
{
return 0x0000011cU;
}
static inline u32 falcon_falcon_imctl_debug_r(void)
{
return 0x0000015cU;
}
static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v)
{
return (v & 0x7U) << 24U;
}
static inline u32 falcon_falcon_imstat_r(void)
{
return 0x00000144U;
}
static inline u32 falcon_falcon_traceidx_r(void)
{
return 0x00000148U;
}
static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 falcon_falcon_traceidx_idx_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 falcon_falcon_tracepc_r(void)
{
return 0x0000014cU;
}
static inline u32 falcon_falcon_tracepc_pc_v(u32 r)
{
return (r >> 0U) & 0xffffffU;
}
static inline u32 falcon_falcon_exterraddr_r(void)
{
return 0x00000168U;
}
static inline u32 falcon_falcon_exterrstat_r(void)
{
return 0x0000016cU;
}
static inline u32 falcon_falcon_exterrstat_valid_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
{
return 0x00000001U;
}
static inline u32 falcon_falcon_icd_cmd_r(void)
{
return 0x00000200U;
}
static inline u32 falcon_falcon_icd_cmd_opc_s(void)
{
return 4U;
}
static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 falcon_falcon_icd_cmd_opc_m(void)
{
return U32(0xfU) << 0U;
}
static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
{
return 0x8U;
}
static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
{
return 0xeU;
}
static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
{
return (v & 0x1fU) << 8U;
}
static inline u32 falcon_falcon_icd_rdata_r(void)
{
return 0x0000020cU;
}
static inline u32 falcon_falcon_dmemc_r(u32 i)
{
return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
{
return (v & 0x3fU) << 2U;
}
static inline u32 falcon_falcon_dmemc_offs_m(void)
{
return U32(0x3fU) << 2U;
}
static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_dmemc_blk_m(void)
{
return U32(0xffU) << 8U;
}
static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
{
return (v & 0x1U) << 25U;
}
static inline u32 falcon_falcon_dmemd_r(u32 i)
{
return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 falcon_falcon_debug1_r(void)
{
return 0x00000090U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
{
return 1U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
{
return 0x0U;
}
static inline u32 falcon_falcon_debuginfo_r(void)
{
return 0x00000094U;
}
#define falcon_falcon_irqsset_r() (0x00000000U)
#define falcon_falcon_irqsset_swgen0_set_f() (0x40U)
#define falcon_falcon_irqsclr_r() (0x00000004U)
#define falcon_falcon_irqstat_r() (0x00000008U)
#define falcon_falcon_irqstat_halt_true_f() (0x10U)
#define falcon_falcon_irqstat_exterr_true_f() (0x20U)
#define falcon_falcon_irqstat_swgen0_true_f() (0x40U)
#define falcon_falcon_irqmode_r() (0x0000000cU)
#define falcon_falcon_irqmset_r() (0x00000010U)
#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqmclr_r() (0x00000014U)
#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_irqmask_r() (0x00000018U)
#define falcon_falcon_irqdest_r() (0x0000001cU)
#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U)
#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U)
#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U)
#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U)
#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U)
#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U)
#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U)
#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U)
#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U)
#define falcon_falcon_curctx_r() (0x00000050U)
#define falcon_falcon_nxtctx_r() (0x00000054U)
#define falcon_falcon_mailbox0_r() (0x00000040U)
#define falcon_falcon_mailbox1_r() (0x00000044U)
#define falcon_falcon_itfen_r() (0x00000048U)
#define falcon_falcon_itfen_ctxen_enable_f() (0x1U)
#define falcon_falcon_idlestate_r() (0x0000004cU)
#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U)
#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU)
#define falcon_falcon_os_r() (0x00000080U)
#define falcon_falcon_engctl_r() (0x000000a4U)
#define falcon_falcon_cpuctl_r() (0x00000100U)
#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define falcon_falcon_cpuctl_alias_r() (0x00000130U)
#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U)
#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U)
#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U)
#define falcon_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemt_r(i)\
(nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_sctl_r() (0x00000240U)
#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define falcon_falcon_bootvec_r() (0x00000104U)
#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U)
#define falcon_falcon_dmactl_r() (0x0000010cU)
#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_hwcfg_r() (0x00000108U)
#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
#define falcon_falcon_hwcfg1_r() (0x0000012cU)
#define falcon_falcon_hwcfg1_imem_ports_v(r) (((r) >> 8U) & 0xfU)
#define falcon_falcon_hwcfg1_dmem_ports_v(r) (((r) >> 12U) & 0xfU)
#define falcon_falcon_dmatrfbase_r() (0x00000110U)
#define falcon_falcon_dmatrfmoffs_r() (0x00000114U)
#define falcon_falcon_dmatrfcmd_r() (0x00000118U)
#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U)
#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U)
#define falcon_falcon_dmatrffboffs_r() (0x0000011cU)
#define falcon_falcon_imctl_debug_r() (0x0000015cU)
#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U)
#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U)
#define falcon_falcon_imstat_r() (0x00000144U)
#define falcon_falcon_traceidx_r() (0x00000148U)
#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU)
#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U)
#define falcon_falcon_tracepc_r() (0x0000014cU)
#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU)
#define falcon_falcon_exterraddr_r() (0x0010a168U)
#define falcon_falcon_exterrstat_r() (0x0010a16cU)
#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U)
#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U)
#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U)
#define falcon_falcon_icd_cmd_r() (0x00000200U)
#define falcon_falcon_icd_cmd_opc_s() (4U)
#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U)
#define falcon_falcon_icd_rdata_r() (0x0000020cU)
#define falcon_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U)
#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U)
#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U)
#define falcon_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_debug1_r() (0x00000090U)
#define falcon_falcon_debug1_ctxsw_mode_s() (1U)
#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U)
#define falcon_falcon_debuginfo_r() (0x00000094U)
#endif

352
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,284 +59,74 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fb_fbhub_num_active_ltcs_r(void)
{
return 0x00100800U;
}
static inline u32 fb_mmu_ctrl_r(void)
{
return 0x00100c80U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
{
return (r >> 11U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
{
return 0x800U;
}
static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_v(u32 r)
{
return (r >> 12U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_true_f(void)
{
return 0x1000U;
}
static inline u32 fb_priv_mmu_phy_secure_r(void)
{
return 0x00100ce4U;
}
static inline u32 fb_mmu_invalidate_pdb_r(void)
{
return 0x00100cb8U;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_invalidate_r(void)
{
return 0x00100cbcU;
}
static inline u32 fb_mmu_invalidate_all_va_true_f(void)
{
return 0x1U;
}
static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_invalidate_trigger_s(void)
{
return 1U;
}
static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 fb_mmu_invalidate_trigger_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_trigger_true_f(void)
{
return 0x80000000U;
}
static inline u32 fb_mmu_debug_wr_r(void)
{
return 0x00100cc8U;
}
static inline u32 fb_mmu_debug_wr_aperture_s(void)
{
return 2U;
}
static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 fb_mmu_debug_wr_aperture_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 fb_mmu_debug_wr_vol_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_wr_vol_true_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_debug_wr_vol_true_f(void)
{
return 0x4U;
}
static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
{
return 0x0000000cU;
}
static inline u32 fb_mmu_debug_rd_r(void)
{
return 0x00100cccU;
}
static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 fb_mmu_debug_rd_vol_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
{
return 0x0000000cU;
}
static inline u32 fb_mmu_debug_ctrl_r(void)
{
return 0x00100cc4U;
}
static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 fb_mmu_debug_ctrl_debug_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
{
return 0x10000U;
}
static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_vpr_info_r(void)
{
return 0x00100cd0U;
}
static inline u32 fb_mmu_vpr_info_index_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 fb_mmu_vpr_info_index_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void)
{
return 0x00000002U;
}
static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void)
{
return 0x00000003U;
}
static inline u32 fb_mmu_vpr_info_fetch_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_wpr_info_r(void)
{
return 0x00100cd4U;
}
static inline u32 fb_mmu_wpr_info_index_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 fb_mmu_wpr_info_index_allow_read_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_wpr_info_index_allow_write_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_wpr_info_index_wpr1_addr_lo_v(void)
{
return 0x00000002U;
}
static inline u32 fb_mmu_wpr_info_index_wpr1_addr_hi_v(void)
{
return 0x00000003U;
}
static inline u32 fb_mmu_wpr_info_index_wpr2_addr_lo_v(void)
{
return 0x00000004U;
}
static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void)
{
return 0x00000005U;
}
static inline u32 fb_niso_flush_sysmem_addr_r(void)
{
return 0x00100c10U;
}
#define fb_fbhub_num_active_ltcs_r() (0x00100800U)
#define fb_mmu_ctrl_r() (0x00100c80U)
#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U)
#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U)
#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU)
#define fb_mmu_ctrl_use_pdb_big_page_size_v(r) (((r) >> 11U) & 0x1U)
#define fb_mmu_ctrl_use_pdb_big_page_size_true_f() (0x800U)
#define fb_mmu_ctrl_use_pdb_big_page_size_false_f() (0x0U)
#define fb_mmu_ctrl_use_full_comp_tag_line_v(r) (((r) >> 12U) & 0x1U)
#define fb_mmu_ctrl_use_full_comp_tag_line_true_f() (0x1000U)
#define fb_priv_mmu_phy_secure_r() (0x00100ce4U)
#define fb_mmu_invalidate_pdb_r() (0x00100cb8U)
#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U)
#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U)
#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_invalidate_r() (0x00100cbcU)
#define fb_mmu_invalidate_all_va_true_f() (0x1U)
#define fb_mmu_invalidate_all_pdb_true_f() (0x2U)
#define fb_mmu_invalidate_trigger_s() (1U)
#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U)
#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U)
#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_invalidate_trigger_true_f() (0x80000000U)
#define fb_mmu_debug_wr_r() (0x00100cc8U)
#define fb_mmu_debug_wr_aperture_s() (2U)
#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_wr_vol_false_f() (0x0U)
#define fb_mmu_debug_wr_vol_true_v() (0x00000001U)
#define fb_mmu_debug_wr_vol_true_f() (0x4U)
#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_rd_r() (0x00100cccU)
#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_rd_vol_false_f() (0x0U)
#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_ctrl_r() (0x00100cc4U)
#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U)
#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U)
#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U)
#define fb_mmu_debug_ctrl_debug_enabled_f() (0x10000U)
#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U)
#define fb_mmu_debug_ctrl_debug_disabled_f() (0x0U)
#define fb_mmu_vpr_info_r() (0x00100cd0U)
#define fb_mmu_vpr_info_index_f(v) (((v)&0x3U) << 0U)
#define fb_mmu_vpr_info_index_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_vpr_info_index_addr_lo_v() (0x00000000U)
#define fb_mmu_vpr_info_index_addr_hi_v() (0x00000001U)
#define fb_mmu_vpr_info_index_cya_lo_v() (0x00000002U)
#define fb_mmu_vpr_info_index_cya_hi_v() (0x00000003U)
#define fb_mmu_vpr_info_fetch_f(v) (((v)&0x1U) << 2U)
#define fb_mmu_vpr_info_fetch_v(r) (((r) >> 2U) & 0x1U)
#define fb_mmu_vpr_info_fetch_false_v() (0x00000000U)
#define fb_mmu_vpr_info_fetch_true_v() (0x00000001U)
#define fb_mmu_wpr_info_r() (0x00100cd4U)
#define fb_mmu_wpr_info_index_f(v) (((v)&0xfU) << 0U)
#define fb_mmu_wpr_info_index_allow_read_v() (0x00000000U)
#define fb_mmu_wpr_info_index_allow_write_v() (0x00000001U)
#define fb_mmu_wpr_info_index_wpr1_addr_lo_v() (0x00000002U)
#define fb_mmu_wpr_info_index_wpr1_addr_hi_v() (0x00000003U)
#define fb_mmu_wpr_info_index_wpr2_addr_lo_v() (0x00000004U)
#define fb_mmu_wpr_info_index_wpr2_addr_hi_v() (0x00000005U)
#define fb_niso_flush_sysmem_addr_r() (0x00100c10U)
#endif

667
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,524 +59,149 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fifo_bar1_base_r(void)
{
return 0x00002254U;
}
static inline u32 fifo_bar1_base_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 fifo_bar1_base_valid_false_f(void)
{
return 0x0U;
}
static inline u32 fifo_bar1_base_valid_true_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_runlist_base_r(void)
{
return 0x00002270U;
}
static inline u32 fifo_runlist_base_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 fifo_runlist_base_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 fifo_runlist_r(void)
{
return 0x00002274U;
}
static inline u32 fifo_runlist_engine_f(u32 v)
{
return (v & 0xfU) << 20U;
}
static inline u32 fifo_eng_runlist_base_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_eng_runlist_base__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_eng_runlist_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_eng_runlist__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_eng_runlist_length_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 fifo_eng_runlist_length_max_v(void)
{
return 0x0000ffffU;
}
static inline u32 fifo_eng_runlist_pending_true_f(void)
{
return 0x100000U;
}
static inline u32 fifo_pb_timeslice_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_pb_timeslice_timeout_16_f(void)
{
return 0x10U;
}
static inline u32 fifo_pb_timeslice_timescale_0_f(void)
{
return 0x0U;
}
static inline u32 fifo_pb_timeslice_enable_true_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_pbdma_map_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_intr_0_r(void)
{
return 0x00002100U;
}
static inline u32 fifo_intr_0_bind_error_pending_f(void)
{
return 0x1U;
}
static inline u32 fifo_intr_0_bind_error_reset_f(void)
{
return 0x1U;
}
static inline u32 fifo_intr_0_sched_error_pending_f(void)
{
return 0x100U;
}
static inline u32 fifo_intr_0_sched_error_reset_f(void)
{
return 0x100U;
}
static inline u32 fifo_intr_0_chsw_error_pending_f(void)
{
return 0x10000U;
}
static inline u32 fifo_intr_0_chsw_error_reset_f(void)
{
return 0x10000U;
}
static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
{
return 0x800000U;
}
static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
{
return 0x800000U;
}
static inline u32 fifo_intr_0_lb_error_pending_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_intr_0_lb_error_reset_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
{
return 0x8000000U;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
{
return 0x8000000U;
}
static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
{
return 0x20000000U;
}
static inline u32 fifo_intr_0_runlist_event_pending_f(void)
{
return 0x40000000U;
}
static inline u32 fifo_intr_0_channel_intr_pending_f(void)
{
return 0x80000000U;
}
static inline u32 fifo_intr_en_0_r(void)
{
return 0x00002140U;
}
static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
{
return (v & 0x1U) << 8U;
}
static inline u32 fifo_intr_en_0_sched_error_m(void)
{
return U32(0x1U) << 8U;
}
static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
{
return (v & 0x1U) << 28U;
}
static inline u32 fifo_intr_en_0_mmu_fault_m(void)
{
return U32(0x1U) << 28U;
}
static inline u32 fifo_intr_en_1_r(void)
{
return 0x00002528U;
}
static inline u32 fifo_intr_bind_error_r(void)
{
return 0x0000252cU;
}
static inline u32 fifo_intr_sched_error_r(void)
{
return 0x0000254cU;
}
static inline u32 fifo_intr_sched_error_code_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
{
return 0x0000000aU;
}
static inline u32 fifo_intr_chsw_error_r(void)
{
return 0x0000256cU;
}
static inline u32 fifo_intr_mmu_fault_id_r(void)
{
return 0x0000259cU;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
{
return 0x0U;
}
static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
{
return (r >> 0U) & 0xfffffffU;
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
{
return nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r)
{
return (r >> 7U) & 0x1U;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
{
return (r >> 6U) & 0x1U;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
{
return (r >> 8U) & 0x3fU;
}
static inline u32 fifo_intr_pbdma_id_r(void)
{
return 0x000025a0U;
}
static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
{
return (r >> (0U + i*1U)) & 0x1U;
}
static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_intr_runlist_r(void)
{
return 0x00002a00U;
}
static inline u32 fifo_fb_timeout_r(void)
{
return 0x00002a04U;
}
static inline u32 fifo_fb_timeout_period_m(void)
{
return U32(0x3fffffffU) << 0U;
}
static inline u32 fifo_fb_timeout_period_max_f(void)
{
return 0x3fffffffU;
}
static inline u32 fifo_error_sched_disable_r(void)
{
return 0x0000262cU;
}
static inline u32 fifo_sched_disable_r(void)
{
return 0x00002630U;
}
static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 fifo_sched_disable_runlist_m(u32 i)
{
return U32(0x1U) << (0U + i*1U);
}
static inline u32 fifo_sched_disable_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_preempt_r(void)
{
return 0x00002634U;
}
static inline u32 fifo_preempt_pending_true_f(void)
{
return 0x100000U;
}
static inline u32 fifo_preempt_type_channel_f(void)
{
return 0x0U;
}
static inline u32 fifo_preempt_type_tsg_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_preempt_chid_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 fifo_preempt_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 fifo_trigger_mmu_fault_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
{
return (v & 0x1fU) << 0U;
}
static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
{
return (v & 0x1U) << 8U;
}
static inline u32 fifo_engine_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_engine_status__size_1_v(void)
{
return 0x00000002U;
}
static inline u32 fifo_engine_status_id_v(u32 r)
{
return (r >> 0U) & 0xfffU;
}
static inline u32 fifo_engine_status_id_type_v(u32 r)
{
return (r >> 12U) & 0x1U;
}
static inline u32 fifo_engine_status_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctx_status_v(u32 r)
{
return (r >> 13U) & 0x7U;
}
static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_ctx_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
{
return 0x00000005U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
{
return 0x00000006U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
{
return 0x00000007U;
}
static inline u32 fifo_engine_status_next_id_v(u32 r)
{
return (r >> 16U) & 0xfffU;
}
static inline u32 fifo_engine_status_next_id_type_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 fifo_engine_status_next_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_next_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_faulted_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 fifo_engine_status_faulted_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_engine_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 fifo_engine_status_engine_idle_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_engine_busy_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctxsw_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
{
return 0x8000U;
}
static inline u32 fifo_pbdma_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_pbdma_status__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_id_v(u32 r)
{
return (r >> 0U) & 0xfffU;
}
static inline u32 fifo_pbdma_status_id_type_v(u32 r)
{
return (r >> 12U) & 0x1U;
}
static inline u32 fifo_pbdma_status_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
{
return (r >> 13U) & 0x7U;
}
static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
{
return 0x00000005U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
{
return 0x00000006U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
{
return 0x00000007U;
}
static inline u32 fifo_pbdma_status_next_id_v(u32 r)
{
return (r >> 16U) & 0xfffU;
}
static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chsw_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
{
return 0x00000001U;
}
#define fifo_bar1_base_r() (0x00002254U)
#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU)
#define fifo_bar1_base_valid_false_f() (0x0U)
#define fifo_bar1_base_valid_true_f() (0x10000000U)
#define fifo_runlist_base_r() (0x00002270U)
#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define fifo_runlist_base_target_vid_mem_f() (0x0U)
#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U)
#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U)
#define fifo_runlist_r() (0x00002274U)
#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U)
#define fifo_eng_runlist_base_r(i)\
(nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist_base__size_1_v() (0x00000001U)
#define fifo_eng_runlist_r(i)\
(nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist__size_1_v() (0x00000001U)
#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U)
#define fifo_eng_runlist_length_max_v() (0x0000ffffU)
#define fifo_eng_runlist_pending_true_f() (0x100000U)
#define fifo_pb_timeslice_r(i)\
(nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_pb_timeslice_timeout_16_f() (0x10U)
#define fifo_pb_timeslice_timescale_0_f() (0x0U)
#define fifo_pb_timeslice_enable_true_f() (0x10000000U)
#define fifo_pbdma_map_r(i)\
(nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_intr_0_r() (0x00002100U)
#define fifo_intr_0_bind_error_pending_f() (0x1U)
#define fifo_intr_0_bind_error_reset_f() (0x1U)
#define fifo_intr_0_sched_error_pending_f() (0x100U)
#define fifo_intr_0_sched_error_reset_f() (0x100U)
#define fifo_intr_0_chsw_error_pending_f() (0x10000U)
#define fifo_intr_0_chsw_error_reset_f() (0x10000U)
#define fifo_intr_0_fb_flush_timeout_pending_f() (0x800000U)
#define fifo_intr_0_fb_flush_timeout_reset_f() (0x800000U)
#define fifo_intr_0_lb_error_pending_f() (0x1000000U)
#define fifo_intr_0_lb_error_reset_f() (0x1000000U)
#define fifo_intr_0_dropped_mmu_fault_pending_f() (0x8000000U)
#define fifo_intr_0_dropped_mmu_fault_reset_f() (0x8000000U)
#define fifo_intr_0_mmu_fault_pending_f() (0x10000000U)
#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U)
#define fifo_intr_0_runlist_event_pending_f() (0x40000000U)
#define fifo_intr_0_channel_intr_pending_f() (0x80000000U)
#define fifo_intr_en_0_r() (0x00002140U)
#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U)
#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U)
#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U)
#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U)
#define fifo_intr_en_1_r() (0x00002528U)
#define fifo_intr_bind_error_r() (0x0000252cU)
#define fifo_intr_sched_error_r() (0x0000254cU)
#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U)
#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU)
#define fifo_intr_chsw_error_r() (0x0000256cU)
#define fifo_intr_mmu_fault_id_r() (0x0000259cU)
#define fifo_intr_mmu_fault_eng_id_graphics_v() (0x00000000U)
#define fifo_intr_mmu_fault_eng_id_graphics_f() (0x0U)
#define fifo_intr_mmu_fault_inst_r(i)\
(nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_inst_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define fifo_intr_mmu_fault_inst_ptr_align_shift_v() (0x0000000cU)
#define fifo_intr_mmu_fault_lo_r(i)\
(nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_hi_r(i)\
(nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_info_r(i)\
(nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_info_type_v(r) (((r) >> 0U) & 0xfU)
#define fifo_intr_mmu_fault_info_write_v(r) (((r) >> 7U) & 0x1U)
#define fifo_intr_mmu_fault_info_engine_subid_v(r) (((r) >> 6U) & 0x1U)
#define fifo_intr_mmu_fault_info_engine_subid_gpc_v() (0x00000000U)
#define fifo_intr_mmu_fault_info_engine_subid_hub_v() (0x00000001U)
#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x3fU)
#define fifo_intr_pbdma_id_r() (0x000025a0U)
#define fifo_intr_pbdma_id_status_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define fifo_intr_pbdma_id_status_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U)
#define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U)
#define fifo_intr_runlist_r() (0x00002a00U)
#define fifo_fb_timeout_r() (0x00002a04U)
#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U)
#define fifo_fb_timeout_period_max_f() (0x3fffffffU)
#define fifo_error_sched_disable_r() (0x0000262cU)
#define fifo_sched_disable_r() (0x00002630U)
#define fifo_sched_disable_runlist_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define fifo_sched_disable_runlist_m(i)\
(U32(0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_true_v() (0x00000001U)
#define fifo_preempt_r() (0x00002634U)
#define fifo_preempt_pending_true_f() (0x100000U)
#define fifo_preempt_type_channel_f() (0x0U)
#define fifo_preempt_type_tsg_f() (0x1000000U)
#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U)
#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U)
#define fifo_trigger_mmu_fault_r(i)\
(nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U)
#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U)
#define fifo_engine_status_r(i)\
(nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_engine_status__size_1_v() (0x00000002U)
#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU)
#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U)
#define fifo_engine_status_id_type_chid_v() (0x00000000U)
#define fifo_engine_status_id_type_tsgid_v() (0x00000001U)
#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U)
#define fifo_engine_status_ctx_status_invalid_v() (0x00000000U)
#define fifo_engine_status_ctx_status_valid_v() (0x00000001U)
#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U)
#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U)
#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U)
#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU)
#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U)
#define fifo_engine_status_next_id_type_chid_v() (0x00000000U)
#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U)
#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U)
#define fifo_engine_status_faulted_true_v() (0x00000001U)
#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U)
#define fifo_engine_status_engine_idle_v() (0x00000000U)
#define fifo_engine_status_engine_busy_v() (0x00000001U)
#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U)
#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U)
#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U)
#define fifo_pbdma_status_r(i)\
(nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_pbdma_status__size_1_v() (0x00000001U)
#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU)
#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U)
#define fifo_pbdma_status_id_type_chid_v() (0x00000000U)
#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U)
#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U)
#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U)
#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U)
#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U)
#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U)
#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU)
#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U)
#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U)
#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U)
#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U)
#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U)
#endif

162
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,132 +59,36 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 flush_l2_system_invalidate_r(void)
{
return 0x00070004U;
}
static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_flush_dirty_r(void)
{
return 0x00070010U;
}
static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_clean_comptags_r(void)
{
return 0x0007000cU;
}
static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_fb_flush_r(void)
{
return 0x00070000U;
}
static inline u32 flush_fb_flush_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_fb_flush_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_fb_flush_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_fb_flush_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_fb_flush_outstanding_true_v(void)
{
return 0x00000001U;
}
#define flush_l2_system_invalidate_r() (0x00070004U)
#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U)
#define flush_l2_system_invalidate_pending_busy_f() (0x1U)
#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U)
#define flush_l2_flush_dirty_r() (0x00070010U)
#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U)
#define flush_l2_flush_dirty_pending_empty_f() (0x0U)
#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U)
#define flush_l2_flush_dirty_pending_busy_f() (0x1U)
#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U)
#define flush_l2_flush_dirty_outstanding_false_f() (0x0U)
#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U)
#define flush_l2_clean_comptags_r() (0x0007000cU)
#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U)
#define flush_l2_clean_comptags_pending_empty_f() (0x0U)
#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U)
#define flush_l2_clean_comptags_pending_busy_f() (0x1U)
#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U)
#define flush_l2_clean_comptags_outstanding_false_f() (0x0U)
#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U)
#define flush_fb_flush_r() (0x00070000U)
#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_fb_flush_pending_busy_v() (0x00000001U)
#define flush_fb_flush_pending_busy_f() (0x1U)
#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_fb_flush_outstanding_true_v() (0x00000001U)
#endif

116
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,92 +59,30 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fuse_status_opt_gpc_r(void)
{
return 0x00021c1cU;
}
static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
{
return 0x00021944U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
{
return 0x00021948U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
{
return 0x1U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
{
return 0x0U;
}
static inline u32 fuse_status_opt_fbio_r(void)
{
return 0x00021c14U;
}
static inline u32 fuse_status_opt_fbio_data_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 fuse_status_opt_fbio_data_m(void)
{
return U32(0xffffU) << 0U;
}
static inline u32 fuse_status_opt_fbio_data_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
{
return nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fuse_status_opt_fbp_r(void)
{
return 0x00021d38U;
}
static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
{
return (r >> (0U + i*1U)) & 0x1U;
}
static inline u32 fuse_opt_sec_debug_en_r(void)
{
return 0x00021218U;
}
static inline u32 fuse_opt_priv_sec_en_r(void)
{
return 0x00021434U;
}
#define fuse_status_opt_gpc_r() (0x00021c1cU)
#define fuse_status_opt_tpc_gpc_r(i)\
(nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_tpc_gpc_r(i)\
(nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U)
#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0x3U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0x3U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0x3U)
#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U)
#define fuse_status_opt_fbio_r() (0x00021c14U)
#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U)
#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U)
#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU)
#define fuse_status_opt_rop_l2_fbp_r(i)\
(nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_status_opt_fbp_r() (0x00021d38U)
#define fuse_status_opt_fbp_idx_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U)
#define fuse_opt_sec_debug_en_r() (0x00021218U)
#define fuse_opt_priv_sec_en_r() (0x00021434U)
#endif

282
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,228 +59,60 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 gmmu_pde_aperture_big_w(void)
{
return 0U;
}
static inline u32 gmmu_pde_aperture_big_invalid_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pde_aperture_big_video_memory_f(void)
{
return 0x1U;
}
static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 gmmu_pde_size_w(void)
{
return 0U;
}
static inline u32 gmmu_pde_size_full_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pde_address_big_sys_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 gmmu_pde_address_big_sys_w(void)
{
return 0U;
}
static inline u32 gmmu_pde_aperture_small_w(void)
{
return 1U;
}
static inline u32 gmmu_pde_aperture_small_invalid_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pde_aperture_small_video_memory_f(void)
{
return 0x1U;
}
static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 gmmu_pde_vol_small_w(void)
{
return 1U;
}
static inline u32 gmmu_pde_vol_small_true_f(void)
{
return 0x4U;
}
static inline u32 gmmu_pde_vol_small_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pde_vol_big_w(void)
{
return 1U;
}
static inline u32 gmmu_pde_vol_big_true_f(void)
{
return 0x8U;
}
static inline u32 gmmu_pde_vol_big_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pde_address_small_sys_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 gmmu_pde_address_small_sys_w(void)
{
return 1U;
}
static inline u32 gmmu_pde_address_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 gmmu_pde__size_v(void)
{
return 0x00000008U;
}
static inline u32 gmmu_pte__size_v(void)
{
return 0x00000008U;
}
static inline u32 gmmu_pte_valid_w(void)
{
return 0U;
}
static inline u32 gmmu_pte_valid_true_f(void)
{
return 0x1U;
}
static inline u32 gmmu_pte_valid_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pte_privilege_w(void)
{
return 0U;
}
static inline u32 gmmu_pte_privilege_true_f(void)
{
return 0x2U;
}
static inline u32 gmmu_pte_privilege_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pte_address_sys_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 gmmu_pte_address_sys_w(void)
{
return 0U;
}
static inline u32 gmmu_pte_address_vid_f(u32 v)
{
return (v & 0x1ffffffU) << 4U;
}
static inline u32 gmmu_pte_address_vid_w(void)
{
return 0U;
}
static inline u32 gmmu_pte_vol_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_vol_true_f(void)
{
return 0x1U;
}
static inline u32 gmmu_pte_vol_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pte_aperture_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_aperture_video_memory_f(void)
{
return 0x0U;
}
static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void)
{
return 0x4U;
}
static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void)
{
return 0x6U;
}
static inline u32 gmmu_pte_read_only_w(void)
{
return 0U;
}
static inline u32 gmmu_pte_read_only_true_f(void)
{
return 0x4U;
}
static inline u32 gmmu_pte_write_disable_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_write_disable_true_f(void)
{
return 0x80000000U;
}
static inline u32 gmmu_pte_read_disable_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_read_disable_true_f(void)
{
return 0x40000000U;
}
static inline u32 gmmu_pte_comptagline_s(void)
{
return 17U;
}
static inline u32 gmmu_pte_comptagline_f(u32 v)
{
return (v & 0x1ffffU) << 12U;
}
static inline u32 gmmu_pte_comptagline_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_address_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 gmmu_pte_kind_f(u32 v)
{
return (v & 0xffU) << 4U;
}
static inline u32 gmmu_pte_kind_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_kind_invalid_v(void)
{
return 0x000000ffU;
}
static inline u32 gmmu_pte_kind_pitch_v(void)
{
return 0x00000000U;
}
#define gmmu_pde_aperture_big_w() (0U)
#define gmmu_pde_aperture_big_invalid_f() (0x0U)
#define gmmu_pde_aperture_big_video_memory_f() (0x1U)
#define gmmu_pde_aperture_big_sys_mem_coh_f() (0x2U)
#define gmmu_pde_aperture_big_sys_mem_ncoh_f() (0x3U)
#define gmmu_pde_size_w() (0U)
#define gmmu_pde_size_full_f() (0x0U)
#define gmmu_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U)
#define gmmu_pde_address_big_sys_w() (0U)
#define gmmu_pde_aperture_small_w() (1U)
#define gmmu_pde_aperture_small_invalid_f() (0x0U)
#define gmmu_pde_aperture_small_video_memory_f() (0x1U)
#define gmmu_pde_aperture_small_sys_mem_coh_f() (0x2U)
#define gmmu_pde_aperture_small_sys_mem_ncoh_f() (0x3U)
#define gmmu_pde_vol_small_w() (1U)
#define gmmu_pde_vol_small_true_f() (0x4U)
#define gmmu_pde_vol_small_false_f() (0x0U)
#define gmmu_pde_vol_big_w() (1U)
#define gmmu_pde_vol_big_true_f() (0x8U)
#define gmmu_pde_vol_big_false_f() (0x0U)
#define gmmu_pde_address_small_sys_f(v) (((v)&0xfffffffU) << 4U)
#define gmmu_pde_address_small_sys_w() (1U)
#define gmmu_pde_address_shift_v() (0x0000000cU)
#define gmmu_pde__size_v() (0x00000008U)
#define gmmu_pte__size_v() (0x00000008U)
#define gmmu_pte_valid_w() (0U)
#define gmmu_pte_valid_true_f() (0x1U)
#define gmmu_pte_valid_false_f() (0x0U)
#define gmmu_pte_privilege_w() (0U)
#define gmmu_pte_privilege_true_f() (0x2U)
#define gmmu_pte_privilege_false_f() (0x0U)
#define gmmu_pte_address_sys_f(v) (((v)&0xfffffffU) << 4U)
#define gmmu_pte_address_sys_w() (0U)
#define gmmu_pte_address_vid_f(v) (((v)&0x1ffffffU) << 4U)
#define gmmu_pte_address_vid_w() (0U)
#define gmmu_pte_vol_w() (1U)
#define gmmu_pte_vol_true_f() (0x1U)
#define gmmu_pte_vol_false_f() (0x0U)
#define gmmu_pte_aperture_w() (1U)
#define gmmu_pte_aperture_video_memory_f() (0x0U)
#define gmmu_pte_aperture_sys_mem_coh_f() (0x4U)
#define gmmu_pte_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_pte_read_only_w() (0U)
#define gmmu_pte_read_only_true_f() (0x4U)
#define gmmu_pte_write_disable_w() (1U)
#define gmmu_pte_write_disable_true_f() (0x80000000U)
#define gmmu_pte_read_disable_w() (1U)
#define gmmu_pte_read_disable_true_f() (0x40000000U)
#define gmmu_pte_comptagline_s() (17U)
#define gmmu_pte_comptagline_f(v) (((v)&0x1ffffU) << 12U)
#define gmmu_pte_comptagline_w() (1U)
#define gmmu_pte_address_shift_v() (0x0000000cU)
#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U)
#define gmmu_pte_kind_w() (1U)
#define gmmu_pte_kind_invalid_v() (0x000000ffU)
#define gmmu_pte_kind_pitch_v() (0x00000000U)
#endif

4875
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
View File

File diff suppressed because it is too large Load Diff

552
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,424 +59,134 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ltc_pltcg_base_v(void)
{
return 0x00140000U;
}
static inline u32 ltc_pltcg_extent_v(void)
{
return 0x0017ffffU;
}
static inline u32 ltc_ltc0_ltss_v(void)
{
return 0x00140200U;
}
static inline u32 ltc_ltc0_lts0_v(void)
{
return 0x00140400U;
}
static inline u32 ltc_ltcs_ltss_v(void)
{
return 0x0017e200U;
}
static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
{
return 0x0014046cU;
}
static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
{
return 0x00140518U;
}
static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
{
return 0x0017e318U;
}
static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
{
return U32(0x1U) << 15U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
{
return 0x00140494U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
{
return (r >> 16U) & 0x3U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
{
return 0x00000000U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
{
return 0x00000002U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
{
return 0x0017e26cU;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
{
return 0x2U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
{
return 0x4U;
}
static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
{
return 0x0014046cU;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
{
return 0x0017e270U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
{
return (v & 0x1ffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
{
return 0x0017e274U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
{
return (v & 0x1ffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
{
return 0x0001ffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
{
return 0x0017e278U;
}
static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
{
return 0x0000000bU;
}
static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
{
return (r >> 0U) & 0x3ffffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
{
return 0x0017e27cU;
}
static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
{
return 0x0017e000U;
}
static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
{
return 0x0017e280U;
}
static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
{
return (r >> 24U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
{
return (r >> 28U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
{
return 0x0017e2acU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
{
return (v & 0x1fU) << 16U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
{
return 0x0017e338U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
{
return nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
{
return 0x00000004U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
{
return 0x0017e34cU;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
{
return 32U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
{
return (r >> 0U) & 0xffffffffU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
{
return 0x0017e2b0U;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
{
return 0x0017e214U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
{
return 0x00140214U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_intr_r(void)
{
return 0x0017e20cU;
}
static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
{
return U32(0x1U) << 20U;
}
static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void)
{
return U32(0x1U) << 21U;
}
static inline u32 ltc_ltc0_lts0_intr_r(void)
{
return 0x0014040cU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
{
return 0x0017e2a0U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
{
return (r >> 8U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
{
return 0x00000003U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
{
return 0x300U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
{
return (r >> 29U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
{
return 0x20000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
{
return 0x40000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
{
return 0x0017e2a4U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
{
return (r >> 8U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
{
return 0x00000003U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
{
return 0x300U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
{
return 0x10000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
{
return (r >> 29U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
{
return 0x20000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
{
return 0x40000000U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
{
return 0x001402a0U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
{
return 0x001402a4U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1U;
}
#define ltc_pltcg_base_v() (0x00140000U)
#define ltc_pltcg_extent_v() (0x0017ffffU)
#define ltc_ltc0_ltss_v() (0x00140200U)
#define ltc_ltc0_lts0_v() (0x00140400U)
#define ltc_ltcs_ltss_v() (0x0017e200U)
#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x0014046cU)
#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00140518U)
#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017e318U)
#define ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m() (U32(0x1U) << 15U)
#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00140494U)
#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U)
#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e26cU)
#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U)
#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U)
#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU)
#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U)
#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x1ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x1ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0001ffffU)
#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U)
#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU)
#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU)
#define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU)
#define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U)
#define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U)
#define ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(r)\
(((r) >> 0U) & 0xffffU)
#define ltc_ltcs_ltss_cbc_param_cache_line_size_v(r) (((r) >> 24U) & 0xfU)
#define ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU)
#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU)
#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\
(((v)&0x1fU) << 16U)
#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
(nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U)))
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\
(((v)&0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\
(U32(0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\
(((r) >> 0U) & 0xffffffffU)
#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e2b0U)
#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U)
#define ltc_ltcs_ltss_g_elpg_r() (0x0017e214U)
#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U)
#define ltc_ltc0_ltss_g_elpg_r() (0x00140214U)
#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U)
#define ltc_ltcs_ltss_intr_r() (0x0017e20cU)
#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U)
#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m() (U32(0x1U) << 30U)
#define ltc_ltcs_ltss_intr_en_illegal_compstat_m() (U32(0x1U) << 21U)
#define ltc_ltc0_lts0_intr_r() (0x0014040cU)
#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\
(((r) >> 8U) & 0xfU)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\
(0x00000003U)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\
(((r) >> 28U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\
(0x10000000U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\
(((r) >> 29U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\
(0x20000000U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\
(((r) >> 30U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\
(0x40000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e2a4U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\
(((r) >> 8U) & 0xfU)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\
(((r) >> 16U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\
(((r) >> 28U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\
(((r) >> 29U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\
(0x20000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\
(((r) >> 30U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U)
#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x001402a0U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x001402a4U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U)
#endif

289
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,232 +59,63 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 mc_boot_0_r(void)
{
return 0x00000000U;
}
static inline u32 mc_boot_0_architecture_v(u32 r)
{
return (r >> 24U) & 0x1fU;
}
static inline u32 mc_boot_0_implementation_v(u32 r)
{
return (r >> 20U) & 0xfU;
}
static inline u32 mc_boot_0_major_revision_v(u32 r)
{
return (r >> 4U) & 0xfU;
}
static inline u32 mc_boot_0_minor_revision_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 mc_intr_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 mc_intr_pfifo_pending_f(void)
{
return 0x100U;
}
static inline u32 mc_intr_pmu_pending_f(void)
{
return 0x1000000U;
}
static inline u32 mc_intr_ltc_pending_f(void)
{
return 0x2000000U;
}
static inline u32 mc_intr_priv_ring_pending_f(void)
{
return 0x40000000U;
}
static inline u32 mc_intr_pbus_pending_f(void)
{
return 0x10000000U;
}
static inline u32 mc_intr_mask_0_r(void)
{
return 0x00000640U;
}
static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
{
return 0x1000000U;
}
static inline u32 mc_intr_en_0_r(void)
{
return 0x00000140U;
}
static inline u32 mc_intr_en_0_inta_disabled_f(void)
{
return 0x0U;
}
static inline u32 mc_intr_en_0_inta_hardware_f(void)
{
return 0x1U;
}
static inline u32 mc_intr_mask_1_r(void)
{
return 0x00000644U;
}
static inline u32 mc_intr_mask_1_pmu_s(void)
{
return 1U;
}
static inline u32 mc_intr_mask_1_pmu_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 mc_intr_mask_1_pmu_m(void)
{
return U32(0x1U) << 24U;
}
static inline u32 mc_intr_mask_1_pmu_v(u32 r)
{
return (r >> 24U) & 0x1U;
}
static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
{
return 0x1000000U;
}
static inline u32 mc_intr_en_1_r(void)
{
return 0x00000144U;
}
static inline u32 mc_intr_en_1_inta_disabled_f(void)
{
return 0x0U;
}
static inline u32 mc_intr_en_1_inta_hardware_f(void)
{
return 0x1U;
}
static inline u32 mc_enable_r(void)
{
return 0x00000200U;
}
static inline u32 mc_enable_xbar_enabled_f(void)
{
return 0x4U;
}
static inline u32 mc_enable_l2_enabled_f(void)
{
return 0x8U;
}
static inline u32 mc_enable_pmedia_s(void)
{
return 1U;
}
static inline u32 mc_enable_pmedia_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 mc_enable_pmedia_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 mc_enable_pmedia_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 mc_enable_priv_ring_enabled_f(void)
{
return 0x20U;
}
static inline u32 mc_enable_ce0_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 mc_enable_pfifo_enabled_f(void)
{
return 0x100U;
}
static inline u32 mc_enable_pgraph_enabled_f(void)
{
return 0x1000U;
}
static inline u32 mc_enable_pwr_v(u32 r)
{
return (r >> 13U) & 0x1U;
}
static inline u32 mc_enable_pwr_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 mc_enable_pwr_enabled_f(void)
{
return 0x2000U;
}
static inline u32 mc_enable_pfb_enabled_f(void)
{
return 0x100000U;
}
static inline u32 mc_enable_ce2_m(void)
{
return U32(0x1U) << 21U;
}
static inline u32 mc_enable_ce2_enabled_f(void)
{
return 0x200000U;
}
static inline u32 mc_enable_blg_enabled_f(void)
{
return 0x8000000U;
}
static inline u32 mc_enable_perfmon_enabled_f(void)
{
return 0x10000000U;
}
static inline u32 mc_enable_hub_enabled_f(void)
{
return 0x20000000U;
}
static inline u32 mc_intr_ltc_r(void)
{
return 0x0000017cU;
}
static inline u32 mc_enable_pb_r(void)
{
return 0x00000204U;
}
static inline u32 mc_enable_pb_0_s(void)
{
return 1U;
}
static inline u32 mc_enable_pb_0_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 mc_enable_pb_0_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 mc_enable_pb_0_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 mc_enable_pb_0_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 mc_elpg_enable_r(void)
{
return 0x0000020cU;
}
static inline u32 mc_elpg_enable_xbar_enabled_f(void)
{
return 0x4U;
}
static inline u32 mc_elpg_enable_pfb_enabled_f(void)
{
return 0x100000U;
}
static inline u32 mc_elpg_enable_hub_enabled_f(void)
{
return 0x20000000U;
}
#define mc_boot_0_r() (0x00000000U)
#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU)
#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU)
#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU)
#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU)
#define mc_intr_r(i)\
(nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32((i), 4U)))
#define mc_intr_pfifo_pending_f() (0x100U)
#define mc_intr_pmu_pending_f() (0x1000000U)
#define mc_intr_ltc_pending_f() (0x2000000U)
#define mc_intr_priv_ring_pending_f() (0x40000000U)
#define mc_intr_pbus_pending_f() (0x10000000U)
#define mc_intr_mask_0_r() (0x00000640U)
#define mc_intr_mask_0_pmu_enabled_f() (0x1000000U)
#define mc_intr_en_0_r() (0x00000140U)
#define mc_intr_en_0_inta_disabled_f() (0x0U)
#define mc_intr_en_0_inta_hardware_f() (0x1U)
#define mc_intr_mask_1_r() (0x00000644U)
#define mc_intr_mask_1_pmu_s() (1U)
#define mc_intr_mask_1_pmu_f(v) (((v)&0x1U) << 24U)
#define mc_intr_mask_1_pmu_m() (U32(0x1U) << 24U)
#define mc_intr_mask_1_pmu_v(r) (((r) >> 24U) & 0x1U)
#define mc_intr_mask_1_pmu_enabled_f() (0x1000000U)
#define mc_intr_en_1_r() (0x00000144U)
#define mc_intr_en_1_inta_disabled_f() (0x0U)
#define mc_intr_en_1_inta_hardware_f() (0x1U)
#define mc_enable_r() (0x00000200U)
#define mc_enable_xbar_enabled_f() (0x4U)
#define mc_enable_l2_enabled_f() (0x8U)
#define mc_enable_pmedia_s() (1U)
#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U)
#define mc_enable_pmedia_m() (U32(0x1U) << 4U)
#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U)
#define mc_enable_priv_ring_enabled_f() (0x20U)
#define mc_enable_ce0_m() (U32(0x1U) << 6U)
#define mc_enable_pfifo_enabled_f() (0x100U)
#define mc_enable_pgraph_enabled_f() (0x1000U)
#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U)
#define mc_enable_pwr_disabled_v() (0x00000000U)
#define mc_enable_pwr_enabled_f() (0x2000U)
#define mc_enable_pfb_enabled_f() (0x100000U)
#define mc_enable_ce2_m() (U32(0x1U) << 21U)
#define mc_enable_ce2_enabled_f() (0x200000U)
#define mc_enable_blg_enabled_f() (0x8000000U)
#define mc_enable_perfmon_enabled_f() (0x10000000U)
#define mc_enable_hub_enabled_f() (0x20000000U)
#define mc_intr_ltc_r() (0x0000017cU)
#define mc_enable_pb_r() (0x00000204U)
#define mc_enable_pb_0_s() (1U)
#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U)
#define mc_enable_pb_0_m() (U32(0x1U) << 0U)
#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U)
#define mc_enable_pb_0_enabled_v() (0x00000001U)
#define mc_enable_pb_sel_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define mc_elpg_enable_r() (0x0000020cU)
#define mc_elpg_enable_xbar_enabled_f() (0x4U)
#define mc_elpg_enable_pfb_enabled_f() (0x100000U)
#define mc_elpg_enable_hub_enabled_f() (0x20000000U)
#endif

712
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,540 +59,178 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pbdma_gp_entry1_r(void)
{
return 0x10000004U;
}
static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 pbdma_gp_entry1_length_f(u32 v)
{
return (v & 0x1fffffU) << 10U;
}
static inline u32 pbdma_gp_entry1_length_v(u32 r)
{
return (r >> 10U) & 0x1fffffU;
}
static inline u32 pbdma_gp_base_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_base__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 pbdma_gp_base_offset_f(u32 v)
{
return (v & 0x1fffffffU) << 3U;
}
static inline u32 pbdma_gp_base_rsvd_s(void)
{
return 3U;
}
static inline u32 pbdma_gp_base_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
{
return (v & 0x1fU) << 16U;
}
static inline u32 pbdma_gp_fetch_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_get_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_put_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_timeout_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_timeout__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 pbdma_timeout_period_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 pbdma_timeout_period_max_f(void)
{
return 0xffffffffU;
}
static inline u32 pbdma_pb_fetch_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_pb_fetch_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_get_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_get_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_put_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_put_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_formats_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_formats_gp_fermi0_f(void)
{
return 0x0U;
}
static inline u32 pbdma_formats_pb_fermi1_f(void)
{
return 0x100U;
}
static inline u32 pbdma_formats_mp_fermi0_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_pb_header_priv_user_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_method_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_subchannel_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_level_main_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_first_true_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_pb_header_type_inc_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_pb_header_type_non_inc_f(void)
{
return 0x60000000U;
}
static inline u32 pbdma_hdr_shadow_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_shadow_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_shadow_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_subdevice_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_subdevice_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 pbdma_subdevice_status_active_f(void)
{
return 0x10000000U;
}
static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_method0_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method0_fifo_size_v(void)
{
return 0x00000004U;
}
static inline u32 pbdma_method0_addr_f(u32 v)
{
return (v & 0xfffU) << 2U;
}
static inline u32 pbdma_method0_addr_v(u32 r)
{
return (r >> 2U) & 0xfffU;
}
static inline u32 pbdma_method0_subch_v(u32 r)
{
return (r >> 16U) & 0x7U;
}
static inline u32 pbdma_method0_first_true_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_method0_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_method1_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method2_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method3_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_data0_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_target_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_target_engine_sw_f(void)
{
return 0x1fU;
}
static inline u32 pbdma_acquire_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_acquire_retry_man_2_f(void)
{
return 0x2U;
}
static inline u32 pbdma_acquire_retry_exp_2_f(void)
{
return 0x100U;
}
static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
{
return (v & 0xfU) << 11U;
}
static inline u32 pbdma_acquire_timeout_exp_max_v(void)
{
return 0x0000000fU;
}
static inline u32 pbdma_acquire_timeout_exp_max_f(void)
{
return 0x7800U;
}
static inline u32 pbdma_acquire_timeout_man_f(u32 v)
{
return (v & 0xffffU) << 15U;
}
static inline u32 pbdma_acquire_timeout_man_max_v(void)
{
return 0x0000ffffU;
}
static inline u32 pbdma_acquire_timeout_man_max_f(void)
{
return 0x7fff8000U;
}
static inline u32 pbdma_acquire_timeout_en_enable_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_acquire_timeout_en_disable_f(void)
{
return 0x0U;
}
static inline u32 pbdma_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_channel_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_signature_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_signature_hw_valid_f(void)
{
return 0xfaceU;
}
static inline u32 pbdma_signature_sw_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_userd_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_userd_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 pbdma_userd_addr_f(u32 v)
{
return (v & 0x7fffffU) << 9U;
}
static inline u32 pbdma_userd_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_userd_hi_addr_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 pbdma_hce_ctrl_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
{
return 0x20U;
}
static inline u32 pbdma_intr_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_0_memreq_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pbdma_intr_0_memreq_pending_f(void)
{
return 0x1U;
}
static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
{
return 0x2U;
}
static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
{
return 0x4U;
}
static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
{
return 0x8U;
}
static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
{
return 0x10U;
}
static inline u32 pbdma_intr_0_memflush_pending_f(void)
{
return 0x20U;
}
static inline u32 pbdma_intr_0_memop_pending_f(void)
{
return 0x40U;
}
static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
{
return 0x80U;
}
static inline u32 pbdma_intr_0_lbreq_pending_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
{
return 0x200U;
}
static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
{
return 0x400U;
}
static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
{
return 0x800U;
}
static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
{
return 0x1000U;
}
static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
{
return 0x2000U;
}
static inline u32 pbdma_intr_0_gpptr_pending_f(void)
{
return 0x4000U;
}
static inline u32 pbdma_intr_0_gpentry_pending_f(void)
{
return 0x8000U;
}
static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
{
return 0x10000U;
}
static inline u32 pbdma_intr_0_pbptr_pending_f(void)
{
return 0x20000U;
}
static inline u32 pbdma_intr_0_pbentry_pending_f(void)
{
return 0x40000U;
}
static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
{
return 0x80000U;
}
static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
{
return 0x100000U;
}
static inline u32 pbdma_intr_0_method_pending_f(void)
{
return 0x200000U;
}
static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_intr_0_device_pending_f(void)
{
return 0x800000U;
}
static inline u32 pbdma_intr_0_semaphore_pending_f(void)
{
return 0x2000000U;
}
static inline u32 pbdma_intr_0_acquire_pending_f(void)
{
return 0x4000000U;
}
static inline u32 pbdma_intr_0_pri_pending_f(void)
{
return 0x8000000U;
}
static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_intr_0_pbseg_pending_f(void)
{
return 0x40000000U;
}
static inline u32 pbdma_intr_0_signature_pending_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_intr_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_en_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_en_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_stall_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
{
return 0x1U;
}
static inline u32 pbdma_udma_nop_r(void)
{
return 0x00000008U;
}
static inline u32 pbdma_syncpointa_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_syncpointa_payload_v(u32 r)
{
return (r >> 0U) & 0xffffffffU;
}
static inline u32 pbdma_syncpointb_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_syncpointb_op_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 pbdma_syncpointb_op_wait_v(void)
{
return 0x00000000U;
}
static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
{
return 0x00000001U;
}
static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
{
return (r >> 8U) & 0xffU;
}
static inline u32 pbdma_runlist_timeslice_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
{
return 0x80U;
}
static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
{
return 0x3000U;
}
static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
{
return 0x10000000U;
}
#define pbdma_gp_entry1_r() (0x10000004U)
#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU)
#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U)
#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU)
#define pbdma_gp_base_r(i)\
(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base__size_1_v() (0x00000001U)
#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U)
#define pbdma_gp_base_rsvd_s() (3U)
#define pbdma_gp_base_hi_r(i)\
(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U)
#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U)
#define pbdma_gp_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_get_r(i)\
(nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_put_r(i)\
(nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_timeout_r(i)\
(nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_timeout__size_1_v() (0x00000001U)
#define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U)
#define pbdma_timeout_period_max_f() (0xffffffffU)
#define pbdma_pb_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_pb_fetch_hi_r(i)\
(nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_get_r(i)\
(nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_get_hi_r(i)\
(nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_put_r(i)\
(nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_put_hi_r(i)\
(nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_formats_r(i)\
(nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_formats_gp_fermi0_f() (0x0U)
#define pbdma_formats_pb_fermi1_f() (0x100U)
#define pbdma_formats_mp_fermi0_f() (0x0U)
#define pbdma_pb_header_r(i)\
(nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_pb_header_priv_user_f() (0x0U)
#define pbdma_pb_header_method_zero_f() (0x0U)
#define pbdma_pb_header_subchannel_zero_f() (0x0U)
#define pbdma_pb_header_level_main_f() (0x0U)
#define pbdma_pb_header_first_true_f() (0x400000U)
#define pbdma_pb_header_type_inc_f() (0x20000000U)
#define pbdma_pb_header_type_non_inc_f() (0x60000000U)
#define pbdma_hdr_shadow_r(i)\
(nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_shadow_0_r(i)\
(nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_shadow_1_r(i)\
(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_r(i)\
(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U)
#define pbdma_subdevice_status_active_f() (0x10000000U)
#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U)
#define pbdma_method0_r(i)\
(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method0_fifo_size_v() (0x00000004U)
#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U)
#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU)
#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U)
#define pbdma_method0_first_true_f() (0x400000U)
#define pbdma_method0_valid_true_f() (0x80000000U)
#define pbdma_method1_r(i)\
(nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method2_r(i)\
(nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method3_r(i)\
(nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_data0_r(i)\
(nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_target_r(i)\
(nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_target_engine_sw_f() (0x1fU)
#define pbdma_acquire_r(i)\
(nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_acquire_retry_man_2_f() (0x2U)
#define pbdma_acquire_retry_exp_2_f() (0x100U)
#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U)
#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU)
#define pbdma_acquire_timeout_exp_max_f() (0x7800U)
#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U)
#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU)
#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U)
#define pbdma_acquire_timeout_en_enable_f() (0x80000000U)
#define pbdma_acquire_timeout_en_disable_f() (0x0U)
#define pbdma_status_r(i)\
(nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_channel_r(i)\
(nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_signature_r(i)\
(nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_signature_hw_valid_f() (0xfaceU)
#define pbdma_signature_sw_zero_f() (0x0U)
#define pbdma_userd_r(i)\
(nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_target_vid_mem_f() (0x0U)
#define pbdma_userd_target_sys_mem_coh_f() (0x2U)
#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U)
#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U)
#define pbdma_userd_hi_r(i)\
(nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U)
#define pbdma_hce_ctrl_r(i)\
(nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U)
#define pbdma_intr_0_r(i)\
(nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U)
#define pbdma_intr_0_memreq_pending_f() (0x1U)
#define pbdma_intr_0_memack_timeout_pending_f() (0x2U)
#define pbdma_intr_0_memack_extra_pending_f() (0x4U)
#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U)
#define pbdma_intr_0_memdat_extra_pending_f() (0x10U)
#define pbdma_intr_0_memflush_pending_f() (0x20U)
#define pbdma_intr_0_memop_pending_f() (0x40U)
#define pbdma_intr_0_lbconnect_pending_f() (0x80U)
#define pbdma_intr_0_lbreq_pending_f() (0x100U)
#define pbdma_intr_0_lback_timeout_pending_f() (0x200U)
#define pbdma_intr_0_lback_extra_pending_f() (0x400U)
#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U)
#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U)
#define pbdma_intr_0_gpfifo_pending_f() (0x2000U)
#define pbdma_intr_0_gpptr_pending_f() (0x4000U)
#define pbdma_intr_0_gpentry_pending_f() (0x8000U)
#define pbdma_intr_0_gpcrc_pending_f() (0x10000U)
#define pbdma_intr_0_pbptr_pending_f() (0x20000U)
#define pbdma_intr_0_pbentry_pending_f() (0x40000U)
#define pbdma_intr_0_pbcrc_pending_f() (0x80000U)
#define pbdma_intr_0_xbarconnect_pending_f() (0x100000U)
#define pbdma_intr_0_method_pending_f() (0x200000U)
#define pbdma_intr_0_methodcrc_pending_f() (0x400000U)
#define pbdma_intr_0_device_pending_f() (0x800000U)
#define pbdma_intr_0_semaphore_pending_f() (0x2000000U)
#define pbdma_intr_0_acquire_pending_f() (0x4000000U)
#define pbdma_intr_0_pri_pending_f() (0x8000000U)
#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U)
#define pbdma_intr_0_pbseg_pending_f() (0x40000000U)
#define pbdma_intr_0_signature_pending_f() (0x80000000U)
#define pbdma_intr_1_r(i)\
(nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_en_0_r(i)\
(nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_en_0_lbreq_enabled_f() (0x100U)
#define pbdma_intr_en_1_r(i)\
(nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_r(i)\
(nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_lbreq_enabled_f() (0x100U)
#define pbdma_intr_stall_1_r(i)\
(nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U)
#define pbdma_udma_nop_r() (0x00000008U)
#define pbdma_syncpointa_r(i)\
(nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_syncpointa_payload_v(r) (((r) >> 0U) & 0xffffffffU)
#define pbdma_syncpointb_r(i)\
(nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_syncpointb_op_v(r) (((r) >> 0U) & 0x3U)
#define pbdma_syncpointb_op_wait_v() (0x00000000U)
#define pbdma_syncpointb_wait_switch_v(r) (((r) >> 4U) & 0x1U)
#define pbdma_syncpointb_wait_switch_en_v() (0x00000001U)
#define pbdma_syncpointb_syncpt_index_v(r) (((r) >> 8U) & 0xffU)
#define pbdma_runlist_timeslice_r(i)\
(nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_runlist_timeslice_timeout_128_f() (0x80U)
#define pbdma_runlist_timeslice_timescale_3_f() (0x3000U)
#define pbdma_runlist_timeslice_enable_true_f() (0x10000000U)
#endif

202
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,164 +59,44 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 perf_pmmsys_base_v(void)
{
return 0x001b0000U;
}
static inline u32 perf_pmmsys_extent_v(void)
{
return 0x001b0fffU;
}
static inline u32 perf_pmasys_control_r(void)
{
return 0x001b4000U;
}
static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
{
return 0x10U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
{
return (r >> 5U) & 0x1U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
{
return 0x20U;
}
static inline u32 perf_pmasys_mem_block_r(void)
{
return 0x001b4070U;
}
static inline u32 perf_pmasys_mem_block_base_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 perf_pmasys_mem_block_target_f(u32 v)
{
return (v & 0x3U) << 28U;
}
static inline u32 perf_pmasys_mem_block_target_v(u32 r)
{
return (r >> 28U) & 0x3U;
}
static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
{
return 0x00000000U;
}
static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
{
return 0x0U;
}
static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
{
return 0x00000002U;
}
static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
{
return 0x20000000U;
}
static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
{
return 0x00000003U;
}
static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 perf_pmasys_mem_block_valid_true_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_mem_block_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 perf_pmasys_mem_block_valid_false_v(void)
{
return 0x00000000U;
}
static inline u32 perf_pmasys_mem_block_valid_false_f(void)
{
return 0x0U;
}
static inline u32 perf_pmasys_outbase_r(void)
{
return 0x001b4074U;
}
static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
{
return (v & 0x7ffffffU) << 5U;
}
static inline u32 perf_pmasys_outbaseupper_r(void)
{
return 0x001b4078U;
}
static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 perf_pmasys_outsize_r(void)
{
return 0x001b407cU;
}
static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
{
return (v & 0x7ffffffU) << 5U;
}
static inline u32 perf_pmasys_mem_bytes_r(void)
{
return 0x001b4084U;
}
static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 perf_pmasys_mem_bump_r(void)
{
return 0x001b4088U;
}
static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 perf_pmasys_enginestatus_r(void)
{
return 0x001b40a4U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
{
return 0x10U;
}
#define perf_pmmsys_base_v() (0x001b0000U)
#define perf_pmmsys_extent_v() (0x001b0fffU)
#define perf_pmasys_control_r() (0x001b4000U)
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)
#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U)
#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U)
#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U)
#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U)
#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U)
#define perf_pmasys_mem_block_r() (0x001b4070U)
#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U)
#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U)
#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U)
#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U)
#define perf_pmasys_mem_block_target_lfb_f() (0x0U)
#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U)
#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U)
#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U)
#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U)
#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U)
#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U)
#define perf_pmasys_mem_block_valid_true_v() (0x00000001U)
#define perf_pmasys_mem_block_valid_true_f() (0x80000000U)
#define perf_pmasys_mem_block_valid_false_v() (0x00000000U)
#define perf_pmasys_mem_block_valid_false_f() (0x0U)
#define perf_pmasys_outbase_r() (0x001b4074U)
#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U)
#define perf_pmasys_outbaseupper_r() (0x001b4078U)
#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U)
#define perf_pmasys_outsize_r() (0x001b407cU)
#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U)
#define perf_pmasys_mem_bytes_r() (0x001b4084U)
#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U)
#define perf_pmasys_mem_bump_r() (0x001b4088U)
#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U)
#define perf_pmasys_enginestatus_r() (0x001b40a4U)
#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U)
#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U)
#endif

8
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,8 +59,6 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pram_data032_r(u32 i)
{
return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U));
}
#define pram_data032_r(i)\
(nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U)))
#endif

139
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,112 +59,33 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringmaster_command_r(void)
{
return 0x0012004cU;
}
static inline u32 pri_ringmaster_command_cmd_m(void)
{
return U32(0x3fU) << 0U;
}
static inline u32 pri_ringmaster_command_cmd_v(u32 r)
{
return (r >> 0U) & 0x3fU;
}
static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
{
return 0x00000000U;
}
static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
{
return 0x1U;
}
static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
{
return 0x2U;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
{
return 0x3U;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
{
return 0x0U;
}
static inline u32 pri_ringmaster_command_data_r(void)
{
return 0x00120048U;
}
static inline u32 pri_ringmaster_start_results_r(void)
{
return 0x00120050U;
}
static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
{
return 0x00000001U;
}
static inline u32 pri_ringmaster_intr_status0_r(void)
{
return 0x00120058U;
}
static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
{
return (r >> 8U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status1_r(void)
{
return 0x0012005cU;
}
static inline u32 pri_ringmaster_global_ctl_r(void)
{
return 0x00120060U;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
{
return 0x1U;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
{
return 0x0U;
}
static inline u32 pri_ringmaster_enum_fbp_r(void)
{
return 0x00120074U;
}
static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 pri_ringmaster_enum_gpc_r(void)
{
return 0x00120078U;
}
static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 pri_ringmaster_enum_ltc_r(void)
{
return 0x0012006cU;
}
static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
#define pri_ringmaster_command_r() (0x0012004cU)
#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U)
#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU)
#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U)
#define pri_ringmaster_command_cmd_start_ring_f() (0x1U)
#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U)
#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U)
#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U)
#define pri_ringmaster_command_data_r() (0x00120048U)
#define pri_ringmaster_start_results_r() (0x00120050U)
#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U)
#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U)
#define pri_ringmaster_intr_status0_r() (0x00120058U)
#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\
(((r) >> 0U) & 0x1U)
#define pri_ringmaster_intr_status0_disconnect_fault_v(r) (((r) >> 1U) & 0x1U)
#define pri_ringmaster_intr_status0_overflow_fault_v(r) (((r) >> 2U) & 0x1U)
#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\
(((r) >> 8U) & 0x1U)
#define pri_ringmaster_intr_status1_r() (0x0012005cU)
#define pri_ringmaster_global_ctl_r() (0x00120060U)
#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U)
#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U)
#define pri_ringmaster_enum_fbp_r() (0x00120074U)
#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU)
#define pri_ringmaster_enum_gpc_r() (0x00120078U)
#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU)
#define pri_ringmaster_enum_ltc_r() (0x0012006cU)
#define pri_ringmaster_enum_ltc_count_v(r) (((r) >> 0U) & 0x1fU)
#endif

28
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,24 +59,10 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
{
return nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
{
return 0x00128120U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
{
return 0x00128124U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
{
return 0x00128128U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
{
return 0x0012812cU;
}
#define pri_ringstation_gpc_master_config_r(i)\
(nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32((i), 4U)))
#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U)
#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U)
#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U)
#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU)
#endif

44
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,36 +59,14 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringstation_sys_master_config_r(u32 i)
{
return nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 pri_ringstation_sys_decode_config_r(void)
{
return 0x00122204U;
}
static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
{
return U32(0x7U) << 0U;
}
static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
{
return 0x1U;
}
static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
{
return 0x00122120U;
}
static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
{
return 0x00122124U;
}
static inline u32 pri_ringstation_sys_priv_error_info_r(void)
{
return 0x00122128U;
}
static inline u32 pri_ringstation_sys_priv_error_code_r(void)
{
return 0x0012212cU;
}
#define pri_ringstation_sys_master_config_r(i)\
(nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32((i), 4U)))
#define pri_ringstation_sys_decode_config_r() (0x00122204U)
#define pri_ringstation_sys_decode_config_ring_m() (U32(0x7U) << 0U)
#define pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()\
(0x1U)
#define pri_ringstation_sys_priv_error_adr_r() (0x00122120U)
#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U)
#define pri_ringstation_sys_priv_error_info_r() (0x00122128U)
#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU)
#endif

142
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,116 +59,32 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 proj_gpc_base_v(void)
{
return 0x00500000U;
}
static inline u32 proj_gpc_shared_base_v(void)
{
return 0x00418000U;
}
static inline u32 proj_gpc_stride_v(void)
{
return 0x00008000U;
}
static inline u32 proj_gpc_priv_stride_v(void)
{
return 0x00000800U;
}
static inline u32 proj_ltc_stride_v(void)
{
return 0x00002000U;
}
static inline u32 proj_lts_stride_v(void)
{
return 0x00000200U;
}
static inline u32 proj_fbpa_stride_v(void)
{
return 0x00001000U;
}
static inline u32 proj_ppc_in_gpc_base_v(void)
{
return 0x00003000U;
}
static inline u32 proj_ppc_in_gpc_shared_base_v(void)
{
return 0x00003e00U;
}
static inline u32 proj_ppc_in_gpc_stride_v(void)
{
return 0x00000200U;
}
static inline u32 proj_rop_base_v(void)
{
return 0x00410000U;
}
static inline u32 proj_rop_shared_base_v(void)
{
return 0x00408800U;
}
static inline u32 proj_rop_stride_v(void)
{
return 0x00000400U;
}
static inline u32 proj_tpc_in_gpc_base_v(void)
{
return 0x00004000U;
}
static inline u32 proj_tpc_in_gpc_stride_v(void)
{
return 0x00000800U;
}
static inline u32 proj_tpc_in_gpc_shared_base_v(void)
{
return 0x00001800U;
}
static inline u32 proj_host_num_engines_v(void)
{
return 0x00000002U;
}
static inline u32 proj_host_num_pbdma_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
{
return 0x00000002U;
}
static inline u32 proj_scal_litter_num_sm_per_tpc_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_fbps_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_fbpas_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_gpcs_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
{
return 0x00000002U;
}
static inline u32 proj_scal_litter_num_zcull_banks_v(void)
{
return 0x00000004U;
}
static inline u32 proj_scal_max_gpcs_v(void)
{
return 0x00000020U;
}
static inline u32 proj_scal_max_tpc_per_gpc_v(void)
{
return 0x00000008U;
}
#define proj_gpc_base_v() (0x00500000U)
#define proj_gpc_shared_base_v() (0x00418000U)
#define proj_gpc_stride_v() (0x00008000U)
#define proj_gpc_priv_stride_v() (0x00000800U)
#define proj_ltc_stride_v() (0x00002000U)
#define proj_lts_stride_v() (0x00000200U)
#define proj_fbpa_stride_v() (0x00001000U)
#define proj_ppc_in_gpc_base_v() (0x00003000U)
#define proj_ppc_in_gpc_shared_base_v() (0x00003e00U)
#define proj_ppc_in_gpc_stride_v() (0x00000200U)
#define proj_rop_base_v() (0x00410000U)
#define proj_rop_shared_base_v() (0x00408800U)
#define proj_rop_stride_v() (0x00000400U)
#define proj_tpc_in_gpc_base_v() (0x00004000U)
#define proj_tpc_in_gpc_stride_v() (0x00000800U)
#define proj_tpc_in_gpc_shared_base_v() (0x00001800U)
#define proj_host_num_engines_v() (0x00000002U)
#define proj_host_num_pbdma_v() (0x00000001U)
#define proj_scal_litter_num_tpc_per_gpc_v() (0x00000002U)
#define proj_scal_litter_num_sm_per_tpc_v() (0x00000001U)
#define proj_scal_litter_num_fbps_v() (0x00000001U)
#define proj_scal_litter_num_fbpas_v() (0x00000001U)
#define proj_scal_litter_num_gpcs_v() (0x00000001U)
#define proj_scal_litter_num_pes_per_gpc_v() (0x00000001U)
#define proj_scal_litter_num_tpcs_per_pes_v() (0x00000002U)
#define proj_scal_litter_num_zcull_banks_v() (0x00000004U)
#define proj_scal_max_gpcs_v() (0x00000020U)
#define proj_scal_max_tpc_per_gpc_v() (0x00000008U)
#endif

1079
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
View File

File diff suppressed because it is too large Load Diff

507
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,408 +59,105 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ram_in_ramfc_s(void)
{
return 4096U;
}
static inline u32 ram_in_ramfc_w(void)
{
return 0U;
}
static inline u32 ram_in_page_dir_base_target_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ram_in_page_dir_base_target_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 ram_in_page_dir_base_vol_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_vol_true_f(void)
{
return 0x4U;
}
static inline u32 ram_in_big_page_size_f(u32 v)
{
return (v & 0x1U) << 11U;
}
static inline u32 ram_in_big_page_size_m(void)
{
return U32(0x1U) << 11U;
}
static inline u32 ram_in_big_page_size_w(void)
{
return 128U;
}
static inline u32 ram_in_big_page_size_128kb_f(void)
{
return 0x0U;
}
static inline u32 ram_in_big_page_size_64kb_f(void)
{
return 0x800U;
}
static inline u32 ram_in_page_dir_base_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_page_dir_base_lo_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_hi_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 ram_in_page_dir_base_hi_w(void)
{
return 129U;
}
static inline u32 ram_in_adr_limit_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_adr_limit_lo_w(void)
{
return 130U;
}
static inline u32 ram_in_adr_limit_hi_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 ram_in_adr_limit_hi_w(void)
{
return 131U;
}
static inline u32 ram_in_engine_cs_w(void)
{
return 132U;
}
static inline u32 ram_in_engine_cs_wfi_v(void)
{
return 0x00000000U;
}
static inline u32 ram_in_engine_cs_wfi_f(void)
{
return 0x0U;
}
static inline u32 ram_in_engine_cs_fg_v(void)
{
return 0x00000001U;
}
static inline u32 ram_in_engine_cs_fg_f(void)
{
return 0x8U;
}
static inline u32 ram_in_gr_cs_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_cs_wfi_f(void)
{
return 0x0U;
}
static inline u32 ram_in_gr_wfi_target_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_wfi_mode_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_wfi_mode_physical_v(void)
{
return 0x00000000U;
}
static inline u32 ram_in_gr_wfi_mode_physical_f(void)
{
return 0x0U;
}
static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
{
return 0x00000001U;
}
static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
{
return 0x4U;
}
static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
{
return 133U;
}
static inline u32 ram_in_base_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 ram_in_alloc_size_v(void)
{
return 0x00001000U;
}
static inline u32 ram_fc_size_val_v(void)
{
return 0x00000200U;
}
static inline u32 ram_fc_gp_put_w(void)
{
return 0U;
}
static inline u32 ram_fc_userd_w(void)
{
return 2U;
}
static inline u32 ram_fc_userd_hi_w(void)
{
return 3U;
}
static inline u32 ram_fc_signature_w(void)
{
return 4U;
}
static inline u32 ram_fc_gp_get_w(void)
{
return 5U;
}
static inline u32 ram_fc_pb_get_w(void)
{
return 6U;
}
static inline u32 ram_fc_pb_get_hi_w(void)
{
return 7U;
}
static inline u32 ram_fc_pb_top_level_get_w(void)
{
return 8U;
}
static inline u32 ram_fc_pb_top_level_get_hi_w(void)
{
return 9U;
}
static inline u32 ram_fc_acquire_w(void)
{
return 12U;
}
static inline u32 ram_fc_semaphorea_w(void)
{
return 14U;
}
static inline u32 ram_fc_semaphoreb_w(void)
{
return 15U;
}
static inline u32 ram_fc_semaphorec_w(void)
{
return 16U;
}
static inline u32 ram_fc_semaphored_w(void)
{
return 17U;
}
static inline u32 ram_fc_gp_base_w(void)
{
return 18U;
}
static inline u32 ram_fc_gp_base_hi_w(void)
{
return 19U;
}
static inline u32 ram_fc_gp_fetch_w(void)
{
return 20U;
}
static inline u32 ram_fc_pb_fetch_w(void)
{
return 21U;
}
static inline u32 ram_fc_pb_fetch_hi_w(void)
{
return 22U;
}
static inline u32 ram_fc_pb_put_w(void)
{
return 23U;
}
static inline u32 ram_fc_pb_put_hi_w(void)
{
return 24U;
}
static inline u32 ram_fc_pb_header_w(void)
{
return 33U;
}
static inline u32 ram_fc_pb_count_w(void)
{
return 34U;
}
static inline u32 ram_fc_subdevice_w(void)
{
return 37U;
}
static inline u32 ram_fc_formats_w(void)
{
return 39U;
}
static inline u32 ram_fc_syncpointa_w(void)
{
return 41U;
}
static inline u32 ram_fc_syncpointb_w(void)
{
return 42U;
}
static inline u32 ram_fc_target_w(void)
{
return 43U;
}
static inline u32 ram_fc_hce_ctrl_w(void)
{
return 57U;
}
static inline u32 ram_fc_chid_w(void)
{
return 58U;
}
static inline u32 ram_fc_chid_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 ram_fc_chid_id_w(void)
{
return 0U;
}
static inline u32 ram_fc_runlist_timeslice_w(void)
{
return 62U;
}
static inline u32 ram_userd_base_shift_v(void)
{
return 0x00000009U;
}
static inline u32 ram_userd_chan_size_v(void)
{
return 0x00000200U;
}
static inline u32 ram_userd_put_w(void)
{
return 16U;
}
static inline u32 ram_userd_get_w(void)
{
return 17U;
}
static inline u32 ram_userd_ref_w(void)
{
return 18U;
}
static inline u32 ram_userd_put_hi_w(void)
{
return 19U;
}
static inline u32 ram_userd_top_level_get_w(void)
{
return 22U;
}
static inline u32 ram_userd_top_level_get_hi_w(void)
{
return 23U;
}
static inline u32 ram_userd_get_hi_w(void)
{
return 24U;
}
static inline u32 ram_userd_gp_get_w(void)
{
return 34U;
}
static inline u32 ram_userd_gp_put_w(void)
{
return 35U;
}
static inline u32 ram_userd_gp_top_level_get_w(void)
{
return 22U;
}
static inline u32 ram_userd_gp_top_level_get_hi_w(void)
{
return 23U;
}
static inline u32 ram_rl_entry_size_v(void)
{
return 0x00000008U;
}
static inline u32 ram_rl_entry_chid_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 ram_rl_entry_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 ram_rl_entry_type_f(u32 v)
{
return (v & 0x1U) << 13U;
}
static inline u32 ram_rl_entry_type_chid_f(void)
{
return 0x0U;
}
static inline u32 ram_rl_entry_type_tsg_f(void)
{
return 0x2000U;
}
static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
{
return (v & 0xfU) << 14U;
}
static inline u32 ram_rl_entry_timeslice_scale_v(u32 r)
{
return (r >> 14U) & 0xfU;
}
static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
{
return 0xc000U;
}
static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
{
return (v & 0xffU) << 18U;
}
static inline u32 ram_rl_entry_timeslice_timeout_v(u32 r)
{
return (r >> 18U) & 0xffU;
}
static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
{
return 0x2000000U;
}
static inline u32 ram_rl_entry_tsg_length_f(u32 v)
{
return (v & 0x3fU) << 26U;
}
#define ram_in_ramfc_s() (4096U)
#define ram_in_ramfc_w() (0U)
#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U)
#define ram_in_page_dir_base_target_w() (128U)
#define ram_in_page_dir_base_target_vid_mem_f() (0x0U)
#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U)
#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U)
#define ram_in_page_dir_base_vol_w() (128U)
#define ram_in_page_dir_base_vol_true_f() (0x4U)
#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U)
#define ram_in_big_page_size_m() (U32(0x1U) << 11U)
#define ram_in_big_page_size_w() (128U)
#define ram_in_big_page_size_128kb_f() (0x0U)
#define ram_in_big_page_size_64kb_f() (0x800U)
#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U)
#define ram_in_page_dir_base_lo_w() (128U)
#define ram_in_page_dir_base_hi_f(v) (((v)&0xffU) << 0U)
#define ram_in_page_dir_base_hi_w() (129U)
#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U)
#define ram_in_adr_limit_lo_w() (130U)
#define ram_in_adr_limit_hi_f(v) (((v)&0xffU) << 0U)
#define ram_in_adr_limit_hi_w() (131U)
#define ram_in_engine_cs_w() (132U)
#define ram_in_engine_cs_wfi_v() (0x00000000U)
#define ram_in_engine_cs_wfi_f() (0x0U)
#define ram_in_engine_cs_fg_v() (0x00000001U)
#define ram_in_engine_cs_fg_f() (0x8U)
#define ram_in_gr_cs_w() (132U)
#define ram_in_gr_cs_wfi_f() (0x0U)
#define ram_in_gr_wfi_target_w() (132U)
#define ram_in_gr_wfi_mode_w() (132U)
#define ram_in_gr_wfi_mode_physical_v() (0x00000000U)
#define ram_in_gr_wfi_mode_physical_f() (0x0U)
#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U)
#define ram_in_gr_wfi_mode_virtual_f() (0x4U)
#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U)
#define ram_in_gr_wfi_ptr_lo_w() (132U)
#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U)
#define ram_in_gr_wfi_ptr_hi_w() (133U)
#define ram_in_base_shift_v() (0x0000000cU)
#define ram_in_alloc_size_v() (0x00001000U)
#define ram_fc_size_val_v() (0x00000200U)
#define ram_fc_gp_put_w() (0U)
#define ram_fc_userd_w() (2U)
#define ram_fc_userd_hi_w() (3U)
#define ram_fc_signature_w() (4U)
#define ram_fc_gp_get_w() (5U)
#define ram_fc_pb_get_w() (6U)
#define ram_fc_pb_get_hi_w() (7U)
#define ram_fc_pb_top_level_get_w() (8U)
#define ram_fc_pb_top_level_get_hi_w() (9U)
#define ram_fc_acquire_w() (12U)
#define ram_fc_semaphorea_w() (14U)
#define ram_fc_semaphoreb_w() (15U)
#define ram_fc_semaphorec_w() (16U)
#define ram_fc_semaphored_w() (17U)
#define ram_fc_gp_base_w() (18U)
#define ram_fc_gp_base_hi_w() (19U)
#define ram_fc_gp_fetch_w() (20U)
#define ram_fc_pb_fetch_w() (21U)
#define ram_fc_pb_fetch_hi_w() (22U)
#define ram_fc_pb_put_w() (23U)
#define ram_fc_pb_put_hi_w() (24U)
#define ram_fc_pb_header_w() (33U)
#define ram_fc_pb_count_w() (34U)
#define ram_fc_subdevice_w() (37U)
#define ram_fc_formats_w() (39U)
#define ram_fc_syncpointa_w() (41U)
#define ram_fc_syncpointb_w() (42U)
#define ram_fc_target_w() (43U)
#define ram_fc_hce_ctrl_w() (57U)
#define ram_fc_chid_w() (58U)
#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U)
#define ram_fc_chid_id_w() (0U)
#define ram_fc_runlist_timeslice_w() (62U)
#define ram_userd_base_shift_v() (0x00000009U)
#define ram_userd_chan_size_v() (0x00000200U)
#define ram_userd_put_w() (16U)
#define ram_userd_get_w() (17U)
#define ram_userd_ref_w() (18U)
#define ram_userd_put_hi_w() (19U)
#define ram_userd_top_level_get_w() (22U)
#define ram_userd_top_level_get_hi_w() (23U)
#define ram_userd_get_hi_w() (24U)
#define ram_userd_gp_get_w() (34U)
#define ram_userd_gp_put_w() (35U)
#define ram_userd_gp_top_level_get_w() (22U)
#define ram_userd_gp_top_level_get_hi_w() (23U)
#define ram_rl_entry_size_v() (0x00000008U)
#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U)
#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U)
#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U)
#define ram_rl_entry_type_chid_f() (0x0U)
#define ram_rl_entry_type_tsg_f() (0x2000U)
#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U)
#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU)
#define ram_rl_entry_timeslice_scale_3_f() (0xc000U)
#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U)
#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU)
#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U)
#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U)
#endif

376
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,300 +59,82 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 therm_use_a_r(void)
{
return 0x00020798U;
}
static inline u32 therm_use_a_ext_therm_0_enable_f(void)
{
return 0x1U;
}
static inline u32 therm_use_a_ext_therm_1_enable_f(void)
{
return 0x2U;
}
static inline u32 therm_use_a_ext_therm_2_enable_f(void)
{
return 0x4U;
}
static inline u32 therm_evt_ext_therm_0_r(void)
{
return 0x00020700U;
}
static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
{
return (v & 0x3fU) << 8U;
}
static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
{
return 0x00000000U;
}
static inline u32 therm_evt_ext_therm_1_r(void)
{
return 0x00020704U;
}
static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
{
return (v & 0x3fU) << 8U;
}
static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
{
return 0x00000000U;
}
static inline u32 therm_evt_ext_therm_2_r(void)
{
return 0x00020708U;
}
static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
{
return (v & 0x3fU) << 8U;
}
static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
{
return 0x00000000U;
}
static inline u32 therm_weight_1_r(void)
{
return 0x00020024U;
}
static inline u32 therm_config1_r(void)
{
return 0x00020050U;
}
static inline u32 therm_config2_r(void)
{
return 0x00020130U;
}
static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 therm_config2_grad_enable_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 therm_gate_ctrl_r(u32 i)
{
return nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 therm_gate_ctrl_eng_clk_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
{
return 0x0U;
}
static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
{
return 0x1U;
}
static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
{
return 0x2U;
}
static inline u32 therm_gate_ctrl_blk_clk_m(void)
{
return U32(0x3U) << 2U;
}
static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
{
return 0x0U;
}
static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
{
return 0x4U;
}
static inline u32 therm_gate_ctrl_eng_pwr_m(void)
{
return U32(0x3U) << 4U;
}
static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
{
return 0x10U;
}
static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
{
return 0x00000002U;
}
static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
{
return 0x20U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
{
return (v & 0x1fU) << 8U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
{
return U32(0x1fU) << 8U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
{
return (v & 0x7U) << 13U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
{
return U32(0x7U) << 13U;
}
static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
{
return (v & 0xfU) << 16U;
}
static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
{
return U32(0xfU) << 16U;
}
static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
{
return (v & 0xfU) << 20U;
}
static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
{
return U32(0xfU) << 20U;
}
static inline u32 therm_fecs_idle_filter_r(void)
{
return 0x00020288U;
}
static inline u32 therm_fecs_idle_filter_value_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 therm_hubmmu_idle_filter_r(void)
{
return 0x0002028cU;
}
static inline u32 therm_hubmmu_idle_filter_value_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 therm_clk_slowdown_r(u32 i)
{
return nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
{
return (v & 0x3fU) << 16U;
}
static inline u32 therm_clk_slowdown_idle_factor_m(void)
{
return U32(0x3fU) << 16U;
}
static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
{
return (r >> 16U) & 0x3fU;
}
static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
{
return 0x0U;
}
static inline u32 therm_grad_stepping_table_r(u32 i)
{
return nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
{
return (v & 0x3fU) << 0U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
{
return U32(0x3fU) << 0U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
{
return 0x1U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
{
return 0x2U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
{
return 0x6U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
{
return 0xeU;
}
static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
{
return (v & 0x3fU) << 6U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
{
return U32(0x3fU) << 6U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
{
return (v & 0x3fU) << 12U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
{
return U32(0x3fU) << 12U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
{
return (v & 0x3fU) << 18U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
{
return U32(0x3fU) << 18U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
{
return (v & 0x3fU) << 24U;
}
static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
{
return U32(0x3fU) << 24U;
}
static inline u32 therm_grad_stepping0_r(void)
{
return 0x000202c0U;
}
static inline u32 therm_grad_stepping0_feature_s(void)
{
return 1U;
}
static inline u32 therm_grad_stepping0_feature_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 therm_grad_stepping0_feature_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 therm_grad_stepping0_feature_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 therm_grad_stepping0_feature_enable_f(void)
{
return 0x1U;
}
static inline u32 therm_grad_stepping1_r(void)
{
return 0x000202c4U;
}
static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
{
return (v & 0x1ffffU) << 0U;
}
static inline u32 therm_clk_timing_r(u32 i)
{
return nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 therm_clk_timing_grad_slowdown_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
{
return 0x10000U;
}
#define therm_use_a_r() (0x00020798U)
#define therm_use_a_ext_therm_0_enable_f() (0x1U)
#define therm_use_a_ext_therm_1_enable_f() (0x2U)
#define therm_use_a_ext_therm_2_enable_f() (0x4U)
#define therm_evt_ext_therm_0_r() (0x00020700U)
#define therm_evt_ext_therm_0_slow_factor_f(v) (((v)&0x3fU) << 8U)
#define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000000U)
#define therm_evt_ext_therm_1_r() (0x00020704U)
#define therm_evt_ext_therm_1_slow_factor_f(v) (((v)&0x3fU) << 8U)
#define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000000U)
#define therm_evt_ext_therm_2_r() (0x00020708U)
#define therm_evt_ext_therm_2_slow_factor_f(v) (((v)&0x3fU) << 8U)
#define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000000U)
#define therm_weight_1_r() (0x00020024U)
#define therm_config1_r() (0x00020050U)
#define therm_config2_r() (0x00020130U)
#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U)
#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U)
#define therm_gate_ctrl_r(i)\
(nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U)
#define therm_gate_ctrl_eng_clk_run_f() (0x0U)
#define therm_gate_ctrl_eng_clk_auto_f() (0x1U)
#define therm_gate_ctrl_eng_clk_stop_f() (0x2U)
#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U)
#define therm_gate_ctrl_blk_clk_run_f() (0x0U)
#define therm_gate_ctrl_blk_clk_auto_f() (0x4U)
#define therm_gate_ctrl_eng_pwr_m() (U32(0x3U) << 4U)
#define therm_gate_ctrl_eng_pwr_auto_f() (0x10U)
#define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U)
#define therm_gate_ctrl_eng_pwr_off_f() (0x20U)
#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U)
#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U)
#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U)
#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U)
#define therm_fecs_idle_filter_r() (0x00020288U)
#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U)
#define therm_hubmmu_idle_filter_r() (0x0002028cU)
#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U)
#define therm_clk_slowdown_r(i)\
(nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU)
#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U)
#define therm_grad_stepping_table_r(i)\
(nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU)
#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U)
#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U)
#define therm_grad_stepping0_r() (0x000202c0U)
#define therm_grad_stepping0_feature_s() (1U)
#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U)
#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U)
#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U)
#define therm_grad_stepping0_feature_enable_f() (0x1U)
#define therm_grad_stepping1_r() (0x000202c4U)
#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U)
#define therm_clk_timing_r(i)\
(nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U)
#endif

87
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,72 +59,21 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 timer_pri_timeout_r(void)
{
return 0x00009080U;
}
static inline u32 timer_pri_timeout_period_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 timer_pri_timeout_period_m(void)
{
return U32(0xffffffU) << 0U;
}
static inline u32 timer_pri_timeout_period_v(u32 r)
{
return (r >> 0U) & 0xffffffU;
}
static inline u32 timer_pri_timeout_en_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 timer_pri_timeout_en_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 timer_pri_timeout_en_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 timer_pri_timeout_en_en_enabled_f(void)
{
return 0x80000000U;
}
static inline u32 timer_pri_timeout_en_en_disabled_f(void)
{
return 0x0U;
}
static inline u32 timer_pri_timeout_save_0_r(void)
{
return 0x00009084U;
}
static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 timer_pri_timeout_save_0_addr_v(u32 r)
{
return (r >> 2U) & 0x3fffffU;
}
static inline u32 timer_pri_timeout_save_0_write_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 timer_pri_timeout_save_1_r(void)
{
return 0x00009088U;
}
static inline u32 timer_pri_timeout_fecs_errcode_r(void)
{
return 0x0000908cU;
}
static inline u32 timer_time_0_r(void)
{
return 0x00009400U;
}
static inline u32 timer_time_1_r(void)
{
return 0x00009410U;
}
#define timer_pri_timeout_r() (0x00009080U)
#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U)
#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U)
#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU)
#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U)
#define timer_pri_timeout_en_m() (U32(0x1U) << 31U)
#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U)
#define timer_pri_timeout_en_en_enabled_f() (0x80000000U)
#define timer_pri_timeout_en_en_disabled_f() (0x0U)
#define timer_pri_timeout_save_0_r() (0x00009084U)
#define timer_pri_timeout_save_0_fecs_tgt_v(r) (((r) >> 31U) & 0x1U)
#define timer_pri_timeout_save_0_addr_v(r) (((r) >> 2U) & 0x3fffffU)
#define timer_pri_timeout_save_0_write_v(r) (((r) >> 1U) & 0x1U)
#define timer_pri_timeout_save_1_r() (0x00009088U)
#define timer_pri_timeout_fecs_errcode_r() (0x0000908cU)
#define timer_time_0_r() (0x00009400U)
#define timer_time_1_r() (0x00009410U)
#endif

248
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,200 +59,54 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 top_num_gpcs_r(void)
{
return 0x00022430U;
}
static inline u32 top_num_gpcs_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_tpc_per_gpc_r(void)
{
return 0x00022434U;
}
static inline u32 top_tpc_per_gpc_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_num_fbps_r(void)
{
return 0x00022438U;
}
static inline u32 top_num_fbps_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_ltc_per_fbp_r(void)
{
return 0x00022450U;
}
static inline u32 top_ltc_per_fbp_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_slices_per_ltc_r(void)
{
return 0x0002245cU;
}
static inline u32 top_slices_per_ltc_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_num_ltcs_r(void)
{
return 0x00022454U;
}
static inline u32 top_device_info_r(u32 i)
{
return nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 top_device_info__size_1_v(void)
{
return 0x00000040U;
}
static inline u32 top_device_info_chain_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 top_device_info_chain_enable_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_chain_disable_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_engine_enum_v(u32 r)
{
return (r >> 26U) & 0xfU;
}
static inline u32 top_device_info_runlist_enum_v(u32 r)
{
return (r >> 21U) & 0xfU;
}
static inline u32 top_device_info_intr_enum_v(u32 r)
{
return (r >> 15U) & 0x1fU;
}
static inline u32 top_device_info_reset_enum_v(u32 r)
{
return (r >> 9U) & 0x1fU;
}
static inline u32 top_device_info_type_enum_v(u32 r)
{
return (r >> 2U) & 0x1fffffffU;
}
static inline u32 top_device_info_type_enum_graphics_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_type_enum_graphics_f(void)
{
return 0x0U;
}
static inline u32 top_device_info_type_enum_copy0_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_type_enum_copy0_f(void)
{
return 0x4U;
}
static inline u32 top_device_info_type_enum_copy1_v(void)
{
return 0x00000002U;
}
static inline u32 top_device_info_type_enum_copy1_f(void)
{
return 0x8U;
}
static inline u32 top_device_info_type_enum_copy2_v(void)
{
return 0x00000003U;
}
static inline u32 top_device_info_type_enum_copy2_f(void)
{
return 0xcU;
}
static inline u32 top_device_info_engine_v(u32 r)
{
return (r >> 5U) & 0x1U;
}
static inline u32 top_device_info_engine_valid_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_runlist_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 top_device_info_runlist_valid_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_intr_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 top_device_info_intr_valid_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_reset_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 top_device_info_reset_valid_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_entry_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 top_device_info_entry_not_valid_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_entry_enum_v(void)
{
return 0x00000002U;
}
static inline u32 top_device_info_entry_engine_type_v(void)
{
return 0x00000003U;
}
static inline u32 top_device_info_entry_data_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_data_type_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 top_device_info_data_type_enum2_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_data_pri_base_v(u32 r)
{
return (r >> 12U) & 0x7ffU;
}
static inline u32 top_device_info_data_pri_base_align_v(void)
{
return 0x0000000cU;
}
static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
{
return (r >> 3U) & 0x1fU;
}
static inline u32 top_device_info_data_fault_id_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 top_device_info_data_fault_id_valid_v(void)
{
return 0x00000001U;
}
#define top_num_gpcs_r() (0x00022430U)
#define top_num_gpcs_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_tpc_per_gpc_r() (0x00022434U)
#define top_tpc_per_gpc_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_num_fbps_r() (0x00022438U)
#define top_num_fbps_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_ltc_per_fbp_r() (0x00022450U)
#define top_ltc_per_fbp_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_slices_per_ltc_r() (0x0002245cU)
#define top_slices_per_ltc_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_num_ltcs_r() (0x00022454U)
#define top_device_info_r(i)\
(nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32((i), 4U)))
#define top_device_info__size_1_v() (0x00000040U)
#define top_device_info_chain_v(r) (((r) >> 31U) & 0x1U)
#define top_device_info_chain_enable_v() (0x00000001U)
#define top_device_info_chain_disable_v() (0x00000000U)
#define top_device_info_engine_enum_v(r) (((r) >> 26U) & 0xfU)
#define top_device_info_runlist_enum_v(r) (((r) >> 21U) & 0xfU)
#define top_device_info_intr_enum_v(r) (((r) >> 15U) & 0x1fU)
#define top_device_info_reset_enum_v(r) (((r) >> 9U) & 0x1fU)
#define top_device_info_type_enum_v(r) (((r) >> 2U) & 0x1fffffffU)
#define top_device_info_type_enum_graphics_v() (0x00000000U)
#define top_device_info_type_enum_graphics_f() (0x0U)
#define top_device_info_type_enum_copy0_v() (0x00000001U)
#define top_device_info_type_enum_copy0_f() (0x4U)
#define top_device_info_type_enum_copy1_v() (0x00000002U)
#define top_device_info_type_enum_copy1_f() (0x8U)
#define top_device_info_type_enum_copy2_v() (0x00000003U)
#define top_device_info_type_enum_copy2_f() (0xcU)
#define top_device_info_engine_v(r) (((r) >> 5U) & 0x1U)
#define top_device_info_engine_valid_v() (0x00000001U)
#define top_device_info_runlist_v(r) (((r) >> 4U) & 0x1U)
#define top_device_info_runlist_valid_v() (0x00000001U)
#define top_device_info_intr_v(r) (((r) >> 3U) & 0x1U)
#define top_device_info_intr_valid_v() (0x00000001U)
#define top_device_info_reset_v(r) (((r) >> 2U) & 0x1U)
#define top_device_info_reset_valid_v() (0x00000001U)
#define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U)
#define top_device_info_entry_not_valid_v() (0x00000000U)
#define top_device_info_entry_enum_v() (0x00000002U)
#define top_device_info_entry_engine_type_v() (0x00000003U)
#define top_device_info_entry_data_v() (0x00000001U)
#define top_device_info_data_type_v(r) (((r) >> 30U) & 0x1U)
#define top_device_info_data_type_enum2_v() (0x00000000U)
#define top_device_info_data_pri_base_v(r) (((r) >> 12U) & 0x7ffU)
#define top_device_info_data_pri_base_align_v() (0x0000000cU)
#define top_device_info_data_fault_id_enum_v(r) (((r) >> 3U) & 0x1fU)
#define top_device_info_data_fault_id_v(r) (((r) >> 2U) & 0x1U)
#define top_device_info_data_fault_id_valid_v() (0x00000001U)
#endif

560
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,448 +59,118 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 trim_sys_gpcpll_cfg_r(void)
{
return 0x00137000U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
{
return 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
{
return 0x00000000U;
}
static inline u32 trim_sys_gpcpll_cfg_sync_mode_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 trim_sys_gpcpll_cfg_sync_mode_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_sync_mode_enable_f(void)
{
return 0x4U;
}
static inline u32 trim_sys_gpcpll_cfg_sync_mode_disable_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void)
{
return 0x10U;
}
static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r)
{
return (r >> 17U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void)
{
return 0x20000U;
}
static inline u32 trim_sys_gpcpll_coeff_r(void)
{
return 0x00137004U;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
{
return U32(0xffU) << 0U;
}
static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
{
return U32(0xffU) << 8U;
}
static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
{
return (r >> 8U) & 0xffU;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
{
return (v & 0x3fU) << 16U;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
{
return U32(0x3fU) << 16U;
}
static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
{
return (r >> 16U) & 0x3fU;
}
static inline u32 trim_sys_sel_vco_r(void)
{
return 0x00137100U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
{
return 0x00000000U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void)
{
return 0x1U;
}
static inline u32 trim_sys_gpc2clk_out_r(void)
{
return 0x00137250U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void)
{
return 6U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
{
return (v & 0x3fU) << 0U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
{
return U32(0x3fU) << 0U;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
{
return (r >> 0U) & 0x3fU;
}
static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void)
{
return 0x3cU;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void)
{
return 6U;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v)
{
return (v & 0x3fU) << 8U;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
{
return U32(0x3fU) << 8U;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r)
{
return (r >> 8U) & 0x3fU;
}
static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
{
return 0x80000000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i)
{
return nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32(i, 512U));
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
{
return (v & 0x3fffU) << 0U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
{
return 0x10000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
{
return 0x100000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
{
return 0x1000000U;
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i)
{
return nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32(i, 512U));
}
static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r)
{
return (r >> 0U) & 0xfffffU;
}
static inline u32 trim_sys_gpcpll_cfg2_r(void)
{
return 0x0013700cU;
}
static inline u32 trim_sys_gpcpll_cfg2_sdm_din_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 trim_sys_gpcpll_cfg2_sdm_din_m(void)
{
return U32(0xffU) << 0U;
}
static inline u32 trim_sys_gpcpll_cfg2_sdm_din_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_m(void)
{
return U32(0xffU) << 8U;
}
static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_v(u32 r)
{
return (r >> 8U) & 0xffU;
}
static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
{
return U32(0xffU) << 24U;
}
static inline u32 trim_sys_gpcpll_cfg3_r(void)
{
return 0x00137018U;
}
static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_f(u32 v)
{
return (v & 0x1ffU) << 0U;
}
static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_m(void)
{
return U32(0x1ffU) << 0U;
}
static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
{
return (v & 0xffU) << 16U;
}
static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
{
return U32(0xffU) << 16U;
}
static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r)
{
return (r >> 24U) & 0x7fU;
}
static inline u32 trim_sys_gpcpll_dvfs0_r(void)
{
return 0x00137010U;
}
static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_f(u32 v)
{
return (v & 0x7fU) << 0U;
}
static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_m(void)
{
return U32(0x7fU) << 0U;
}
static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_v(u32 r)
{
return (r >> 0U) & 0x7fU;
}
static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_f(u32 v)
{
return (v & 0x7fU) << 8U;
}
static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_m(void)
{
return U32(0x7fU) << 8U;
}
static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_v(u32 r)
{
return (r >> 8U) & 0x7fU;
}
static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(u32 v)
{
return (v & 0x3fU) << 16U;
}
static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_m(void)
{
return U32(0x3fU) << 16U;
}
static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(u32 r)
{
return (r >> 16U) & 0x3fU;
}
static inline u32 trim_sys_gpcpll_dvfs0_mode_m(void)
{
return U32(0x1U) << 28U;
}
static inline u32 trim_sys_gpcpll_dvfs0_mode_dvfspll_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_gpcpll_dvfs1_r(void)
{
return 0x00137014U;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_f(u32 v)
{
return (v & 0x7fU) << 0U;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_m(void)
{
return U32(0x7fU) << 0U;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_v(u32 r)
{
return (r >> 0U) & 0x7fU;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_strb_m(void)
{
return U32(0x1U) << 7U;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(u32 v)
{
return (v & 0x7fU) << 8U;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_m(void)
{
return U32(0x7fU) << 8U;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(u32 r)
{
return (r >> 8U) & 0x7fU;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_sel_m(void)
{
return U32(0x1U) << 15U;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(u32 v)
{
return (v & 0xfffU) << 16U;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_m(void)
{
return U32(0xfffU) << 16U;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_v(u32 r)
{
return (r >> 16U) & 0xfffU;
}
static inline u32 trim_sys_gpcpll_dvfs1_en_sdm_m(void)
{
return U32(0x1U) << 28U;
}
static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_m(void)
{
return U32(0x1U) << 29U;
}
static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_cal_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 trim_sys_gpcpll_dvfs1_dfs_cal_done_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 trim_sys_gpcpll_dvfs2_r(void)
{
return 0x00137020U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
{
return 0x0013701cU;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
{
return U32(0x1U) << 22U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
{
return 0x400000U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
{
return 0x80000000U;
}
static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void)
{
return 0x0U;
}
static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void)
{
return 0x001328a0U;
}
static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r)
{
return (r >> 24U) & 0x1U;
}
static inline u32 trim_gpc_bcast_gpcpll_dvfs2_r(void)
{
return 0x00132820U;
}
static inline u32 trim_sys_bypassctrl_r(void)
{
return 0x00137340U;
}
static inline u32 trim_sys_bypassctrl_gpcpll_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 trim_sys_bypassctrl_gpcpll_bypassclk_f(void)
{
return 0x1U;
}
static inline u32 trim_sys_bypassctrl_gpcpll_vco_f(void)
{
return 0x0U;
}
#define trim_sys_gpcpll_cfg_r() (0x00137000U)
#define trim_sys_gpcpll_cfg_enable_m() (U32(0x1U) << 0U)
#define trim_sys_gpcpll_cfg_enable_v(r) (((r) >> 0U) & 0x1U)
#define trim_sys_gpcpll_cfg_enable_no_f() (0x0U)
#define trim_sys_gpcpll_cfg_enable_yes_f() (0x1U)
#define trim_sys_gpcpll_cfg_iddq_m() (U32(0x1U) << 1U)
#define trim_sys_gpcpll_cfg_iddq_v(r) (((r) >> 1U) & 0x1U)
#define trim_sys_gpcpll_cfg_iddq_power_on_v() (0x00000000U)
#define trim_sys_gpcpll_cfg_sync_mode_m() (U32(0x1U) << 2U)
#define trim_sys_gpcpll_cfg_sync_mode_v(r) (((r) >> 2U) & 0x1U)
#define trim_sys_gpcpll_cfg_sync_mode_enable_f() (0x4U)
#define trim_sys_gpcpll_cfg_sync_mode_disable_f() (0x0U)
#define trim_sys_gpcpll_cfg_enb_lckdet_m() (U32(0x1U) << 4U)
#define trim_sys_gpcpll_cfg_enb_lckdet_power_on_f() (0x0U)
#define trim_sys_gpcpll_cfg_enb_lckdet_power_off_f() (0x10U)
#define trim_sys_gpcpll_cfg_pll_lock_v(r) (((r) >> 17U) & 0x1U)
#define trim_sys_gpcpll_cfg_pll_lock_true_f() (0x20000U)
#define trim_sys_gpcpll_coeff_r() (0x00137004U)
#define trim_sys_gpcpll_coeff_mdiv_f(v) (((v)&0xffU) << 0U)
#define trim_sys_gpcpll_coeff_mdiv_m() (U32(0xffU) << 0U)
#define trim_sys_gpcpll_coeff_mdiv_v(r) (((r) >> 0U) & 0xffU)
#define trim_sys_gpcpll_coeff_ndiv_f(v) (((v)&0xffU) << 8U)
#define trim_sys_gpcpll_coeff_ndiv_m() (U32(0xffU) << 8U)
#define trim_sys_gpcpll_coeff_ndiv_v(r) (((r) >> 8U) & 0xffU)
#define trim_sys_gpcpll_coeff_pldiv_f(v) (((v)&0x3fU) << 16U)
#define trim_sys_gpcpll_coeff_pldiv_m() (U32(0x3fU) << 16U)
#define trim_sys_gpcpll_coeff_pldiv_v(r) (((r) >> 16U) & 0x3fU)
#define trim_sys_sel_vco_r() (0x00137100U)
#define trim_sys_sel_vco_gpc2clk_out_m() (U32(0x1U) << 0U)
#define trim_sys_sel_vco_gpc2clk_out_init_v() (0x00000000U)
#define trim_sys_sel_vco_gpc2clk_out_init_f() (0x0U)
#define trim_sys_sel_vco_gpc2clk_out_bypass_f() (0x0U)
#define trim_sys_sel_vco_gpc2clk_out_vco_f() (0x1U)
#define trim_sys_gpc2clk_out_r() (0x00137250U)
#define trim_sys_gpc2clk_out_bypdiv_s() (6U)
#define trim_sys_gpc2clk_out_bypdiv_f(v) (((v)&0x3fU) << 0U)
#define trim_sys_gpc2clk_out_bypdiv_m() (U32(0x3fU) << 0U)
#define trim_sys_gpc2clk_out_bypdiv_v(r) (((r) >> 0U) & 0x3fU)
#define trim_sys_gpc2clk_out_bypdiv_by31_f() (0x3cU)
#define trim_sys_gpc2clk_out_vcodiv_s() (6U)
#define trim_sys_gpc2clk_out_vcodiv_f(v) (((v)&0x3fU) << 8U)
#define trim_sys_gpc2clk_out_vcodiv_m() (U32(0x3fU) << 8U)
#define trim_sys_gpc2clk_out_vcodiv_v(r) (((r) >> 8U) & 0x3fU)
#define trim_sys_gpc2clk_out_vcodiv_by1_f() (0x0U)
#define trim_sys_gpc2clk_out_sdiv14_m() (U32(0x1U) << 31U)
#define trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() (0x80000000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_r(i)\
(nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32((i), 512U)))
#define trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(v) (((v)&0x3fffU) << 0U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U)
#define trim_gpc_clk_cntr_ncgpcclk_cnt_r(i)\
(nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32((i), 512U)))
#define trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(r) (((r) >> 0U) & 0xfffffU)
#define trim_sys_gpcpll_cfg2_r() (0x0013700cU)
#define trim_sys_gpcpll_cfg2_sdm_din_f(v) (((v)&0xffU) << 0U)
#define trim_sys_gpcpll_cfg2_sdm_din_m() (U32(0xffU) << 0U)
#define trim_sys_gpcpll_cfg2_sdm_din_v(r) (((r) >> 0U) & 0xffU)
#define trim_sys_gpcpll_cfg2_sdm_din_new_f(v) (((v)&0xffU) << 8U)
#define trim_sys_gpcpll_cfg2_sdm_din_new_m() (U32(0xffU) << 8U)
#define trim_sys_gpcpll_cfg2_sdm_din_new_v(r) (((r) >> 8U) & 0xffU)
#define trim_sys_gpcpll_cfg2_pll_stepa_f(v) (((v)&0xffU) << 24U)
#define trim_sys_gpcpll_cfg2_pll_stepa_m() (U32(0xffU) << 24U)
#define trim_sys_gpcpll_cfg3_r() (0x00137018U)
#define trim_sys_gpcpll_cfg3_vco_ctrl_f(v) (((v)&0x1ffU) << 0U)
#define trim_sys_gpcpll_cfg3_vco_ctrl_m() (U32(0x1ffU) << 0U)
#define trim_sys_gpcpll_cfg3_pll_stepb_f(v) (((v)&0xffU) << 16U)
#define trim_sys_gpcpll_cfg3_pll_stepb_m() (U32(0xffU) << 16U)
#define trim_sys_gpcpll_cfg3_dfs_testout_v(r) (((r) >> 24U) & 0x7fU)
#define trim_sys_gpcpll_dvfs0_r() (0x00137010U)
#define trim_sys_gpcpll_dvfs0_dfs_coeff_f(v) (((v)&0x7fU) << 0U)
#define trim_sys_gpcpll_dvfs0_dfs_coeff_m() (U32(0x7fU) << 0U)
#define trim_sys_gpcpll_dvfs0_dfs_coeff_v(r) (((r) >> 0U) & 0x7fU)
#define trim_sys_gpcpll_dvfs0_dfs_det_max_f(v) (((v)&0x7fU) << 8U)
#define trim_sys_gpcpll_dvfs0_dfs_det_max_m() (U32(0x7fU) << 8U)
#define trim_sys_gpcpll_dvfs0_dfs_det_max_v(r) (((r) >> 8U) & 0x7fU)
#define trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(v) (((v)&0x3fU) << 16U)
#define trim_sys_gpcpll_dvfs0_dfs_dc_offset_m() (U32(0x3fU) << 16U)
#define trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(r) (((r) >> 16U) & 0x3fU)
#define trim_sys_gpcpll_dvfs0_mode_m() (U32(0x1U) << 28U)
#define trim_sys_gpcpll_dvfs0_mode_dvfspll_f() (0x0U)
#define trim_sys_gpcpll_dvfs1_r() (0x00137014U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_det_f(v) (((v)&0x7fU) << 0U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_det_m() (U32(0x7fU) << 0U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_det_v(r) (((r) >> 0U) & 0x7fU)
#define trim_sys_gpcpll_dvfs1_dfs_ext_strb_m() (U32(0x1U) << 7U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(v) (((v)&0x7fU) << 8U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_cal_m() (U32(0x7fU) << 8U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(r) (((r) >> 8U) & 0x7fU)
#define trim_sys_gpcpll_dvfs1_dfs_ext_sel_m() (U32(0x1U) << 15U)
#define trim_sys_gpcpll_dvfs1_dfs_ctrl_f(v) (((v)&0xfffU) << 16U)
#define trim_sys_gpcpll_dvfs1_dfs_ctrl_m() (U32(0xfffU) << 16U)
#define trim_sys_gpcpll_dvfs1_dfs_ctrl_v(r) (((r) >> 16U) & 0xfffU)
#define trim_sys_gpcpll_dvfs1_en_sdm_m() (U32(0x1U) << 28U)
#define trim_sys_gpcpll_dvfs1_en_dfs_m() (U32(0x1U) << 29U)
#define trim_sys_gpcpll_dvfs1_en_dfs_cal_m() (U32(0x1U) << 30U)
#define trim_sys_gpcpll_dvfs1_dfs_cal_done_v(r) (((r) >> 31U) & 0x1U)
#define trim_sys_gpcpll_dvfs2_r() (0x00137020U)
#define trim_sys_gpcpll_ndiv_slowdown_r() (0x0013701cU)
#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m() (U32(0x1U) << 22U)
#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f() (0x400000U)
#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f() (0x0U)
#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m() (U32(0x1U) << 31U)
#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f() (0x80000000U)
#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f() (0x0U)
#define trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r() (0x001328a0U)
#define trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(r)\
(((r) >> 24U) & 0x1U)
#define trim_gpc_bcast_gpcpll_dvfs2_r() (0x00132820U)
#define trim_sys_bypassctrl_r() (0x00137340U)
#define trim_sys_bypassctrl_gpcpll_m() (U32(0x1U) << 0U)
#define trim_sys_bypassctrl_gpcpll_bypassclk_f() (0x1U)
#define trim_sys_bypassctrl_gpcpll_vco_f() (0x0U)
#endif

227
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,184 +59,49 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 bus_bar0_window_r(void)
{
return 0x00001700U;
}
static inline u32 bus_bar0_window_base_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 bus_bar0_window_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
{
return 0x2000000U;
}
static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
{
return 0x3000000U;
}
static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
{
return 0x00000010U;
}
static inline u32 bus_bar1_block_r(void)
{
return 0x00001704U;
}
static inline u32 bus_bar1_block_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 bus_bar1_block_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 bus_bar1_block_mode_virtual_f(void)
{
return 0x80000000U;
}
static inline u32 bus_bar2_block_r(void)
{
return 0x00001714U;
}
static inline u32 bus_bar2_block_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 bus_bar2_block_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 bus_bar2_block_mode_virtual_f(void)
{
return 0x80000000U;
}
static inline u32 bus_bar1_block_ptr_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 bus_bar2_block_ptr_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 bus_bind_status_r(void)
{
return 0x00001710U;
}
static inline u32 bus_bind_status_bar1_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 bus_bind_status_bar1_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar1_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
{
return 0x2U;
}
static inline u32 bus_bind_status_bar2_pending_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 bus_bind_status_bar2_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 bus_bind_status_bar2_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar2_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 bus_bind_status_bar2_pending_busy_f(void)
{
return 0x4U;
}
static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 bus_bind_status_bar2_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar2_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
{
return 0x8U;
}
static inline u32 bus_intr_0_r(void)
{
return 0x00001100U;
}
static inline u32 bus_intr_0_pri_squash_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 bus_intr_0_pri_fecserr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 bus_intr_0_pri_timeout_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 bus_intr_en_0_r(void)
{
return 0x00001140U;
}
static inline u32 bus_intr_en_0_pri_squash_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 bus_intr_en_0_pri_fecserr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 bus_intr_en_0_pri_timeout_m(void)
{
return U32(0x1U) << 3U;
}
#define bus_bar0_window_r() (0x00001700U)
#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U)
#define bus_bar0_window_target_vid_mem_f() (0x0U)
#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U)
#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U)
#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U)
#define bus_bar1_block_r() (0x00001704U)
#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define bus_bar1_block_target_vid_mem_f() (0x0U)
#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar1_block_mode_virtual_f() (0x80000000U)
#define bus_bar2_block_r() (0x00001714U)
#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define bus_bar2_block_target_vid_mem_f() (0x0U)
#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar2_block_mode_virtual_f() (0x80000000U)
#define bus_bar1_block_ptr_shift_v() (0x0000000cU)
#define bus_bar2_block_ptr_shift_v() (0x0000000cU)
#define bus_bind_status_r() (0x00001710U)
#define bus_bind_status_bar1_pending_v(r) (((r) >> 0U) & 0x1U)
#define bus_bind_status_bar1_pending_empty_f() (0x0U)
#define bus_bind_status_bar1_pending_busy_f() (0x1U)
#define bus_bind_status_bar1_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define bus_bind_status_bar1_outstanding_false_f() (0x0U)
#define bus_bind_status_bar1_outstanding_true_f() (0x2U)
#define bus_bind_status_bar2_pending_v(r) (((r) >> 2U) & 0x1U)
#define bus_bind_status_bar2_pending_empty_v() (0x00000000U)
#define bus_bind_status_bar2_pending_empty_f() (0x0U)
#define bus_bind_status_bar2_pending_busy_v() (0x00000001U)
#define bus_bind_status_bar2_pending_busy_f() (0x4U)
#define bus_bind_status_bar2_outstanding_v(r) (((r) >> 3U) & 0x1U)
#define bus_bind_status_bar2_outstanding_false_v() (0x00000000U)
#define bus_bind_status_bar2_outstanding_false_f() (0x0U)
#define bus_bind_status_bar2_outstanding_true_v() (0x00000001U)
#define bus_bind_status_bar2_outstanding_true_f() (0x8U)
#define bus_intr_0_r() (0x00001100U)
#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U)
#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U)
#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U)
#define bus_intr_en_0_r() (0x00001140U)
#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U)
#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U)
#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U)
#endif

144
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,116 +59,34 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ccsr_channel_inst_r(u32 i)
{
return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 ccsr_channel_inst__size_1_v(void)
{
return 0x00001000U;
}
static inline u32 ccsr_channel_inst_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 ccsr_channel_inst_bind_false_f(void)
{
return 0x0U;
}
static inline u32 ccsr_channel_inst_bind_true_f(void)
{
return 0x80000000U;
}
static inline u32 ccsr_channel_r(u32 i)
{
return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 ccsr_channel__size_1_v(void)
{
return 0x00001000U;
}
static inline u32 ccsr_channel_enable_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ccsr_channel_enable_in_use_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_enable_set_f(u32 v)
{
return (v & 0x1U) << 10U;
}
static inline u32 ccsr_channel_enable_set_true_f(void)
{
return 0x400U;
}
static inline u32 ccsr_channel_enable_clr_true_f(void)
{
return 0x800U;
}
static inline u32 ccsr_channel_status_v(u32 r)
{
return (r >> 24U) & 0xfU;
}
static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
{
return 0x00000002U;
}
static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
{
return 0x00000004U;
}
static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
{
return 0x0000000aU;
}
static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
{
return 0x0000000bU;
}
static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
{
return 0x0000000cU;
}
static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
{
return 0x0000000dU;
}
static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
{
return 0x0000000eU;
}
static inline u32 ccsr_channel_next_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 ccsr_channel_next_true_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
{
return 0x100U;
}
static inline u32 ccsr_channel_busy_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ccsr_channel_busy_true_v(void)
{
return 0x00000001U;
}
#define ccsr_channel_inst_r(i)\
(nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel_inst__size_1_v() (0x00001000U)
#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define ccsr_channel_inst_target_vid_mem_f() (0x0U)
#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U)
#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U)
#define ccsr_channel_inst_bind_false_f() (0x0U)
#define ccsr_channel_inst_bind_true_f() (0x80000000U)
#define ccsr_channel_r(i)\
(nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel__size_1_v() (0x00001000U)
#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U)
#define ccsr_channel_enable_in_use_v() (0x00000001U)
#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U)
#define ccsr_channel_enable_set_true_f() (0x400U)
#define ccsr_channel_enable_clr_true_f() (0x800U)
#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU)
#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U)
#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U)
#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU)
#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU)
#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU)
#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU)
#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU)
#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U)
#define ccsr_channel_next_true_v() (0x00000001U)
#define ccsr_channel_force_ctx_reload_true_f() (0x100U)
#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U)
#define ccsr_channel_busy_true_v() (0x00000001U)
#endif

38
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ce_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,32 +59,12 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ce_intr_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32(i, 128U));
}
static inline u32 ce_intr_status_blockpipe_pending_f(void)
{
return 0x1U;
}
static inline u32 ce_intr_status_blockpipe_reset_f(void)
{
return 0x1U;
}
static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
{
return 0x2U;
}
static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
{
return 0x2U;
}
static inline u32 ce_intr_status_launcherr_pending_f(void)
{
return 0x4U;
}
static inline u32 ce_intr_status_launcherr_reset_f(void)
{
return 0x4U;
}
#define ce_intr_status_r(i)\
(nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32((i), 128U)))
#define ce_intr_status_blockpipe_pending_f() (0x1U)
#define ce_intr_status_blockpipe_reset_f() (0x1U)
#define ce_intr_status_nonblockpipe_pending_f() (0x2U)
#define ce_intr_status_nonblockpipe_reset_f() (0x2U)
#define ce_intr_status_launcherr_pending_f() (0x4U)
#define ce_intr_status_launcherr_reset_f() (0x4U)
#endif

314
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,248 +59,72 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ctxsw_prog_fecs_header_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_gpccs_header_stride_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
{
return 0x00000008U;
}
static inline u32 ctxsw_prog_main_image_patch_count_o(void)
{
return 0x00000010U;
}
static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
{
return 0x00000014U;
}
static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
{
return 0x00000018U;
}
static inline u32 ctxsw_prog_main_image_zcull_o(void)
{
return 0x0000001cU;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
{
return 0x00000001U;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
{
return 0x00000002U;
}
static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
{
return 0x00000020U;
}
static inline u32 ctxsw_prog_main_image_pm_o(void)
{
return 0x00000028U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
{
return U32(0x7U) << 0U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
{
return U32(0x7U) << 3U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
{
return 0x8U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
{
return 0x0000002cU;
}
static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
{
return 0x000000f4U;
}
static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
{
return 0x000000d0U;
}
static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
{
return 0x000000d4U;
}
static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
{
return 0x000000d8U;
}
static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
{
return 0x000000dcU;
}
static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
{
return 0x000000f8U;
}
static inline u32 ctxsw_prog_main_image_magic_value_o(void)
{
return 0x000000fcU;
}
static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
{
return 0x600dc0deU;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
{
return 0x000000f4U;
}
static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
{
return (r >> 16U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
{
return 0x000000f8U;
}
static inline u32 ctxsw_prog_local_magic_value_o(void)
{
return 0x000000fcU;
}
static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
{
return 0xad0becabU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
{
return 0x000000ecU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
{
return 0x00000000U;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
{
return 0x00000002U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
{
return 0x000000a0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
{
return 2U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
{
return 0x2U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
{
return 0x000000a4U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
{
return 0x000000a8U;
}
static inline u32 ctxsw_prog_main_image_misc_options_o(void)
{
return 0x0000003cU;
}
static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
{
return 0x00000080U;
}
static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
{
return 0x00000068U;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
{
return 0x00000084U;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
{
return 0x2U;
}
#define ctxsw_prog_fecs_header_v() (0x00000100U)
#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U)
#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U)
#define ctxsw_prog_main_image_patch_count_o() (0x00000010U)
#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U)
#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U)
#define ctxsw_prog_main_image_zcull_o() (0x0000001cU)
#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U)
#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U)
#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U)
#define ctxsw_prog_main_image_pm_o() (0x00000028U)
#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U)
#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U)
#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U)
#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U)
#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U)
#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U)
#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU)
#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U)
#define ctxsw_prog_main_image_num_wfi_save_ops_o() (0x000000d0U)
#define ctxsw_prog_main_image_num_cta_save_ops_o() (0x000000d4U)
#define ctxsw_prog_main_image_num_gfxp_save_ops_o() (0x000000d8U)
#define ctxsw_prog_main_image_num_cilp_save_ops_o() (0x000000dcU)
#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U)
#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU)
#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU)
#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU)
#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U)
#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU)
#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U)
#define ctxsw_prog_local_magic_value_o() (0x000000fcU)
#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU)
#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU)
#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU)
#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U)
#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U)
#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\
(0x00000000U)
#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\
(0x00000002U)
#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\
(((v)&0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\
(((r) >> 0U) & 0x3U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U)
#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U)
#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U)
#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU)
#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U)
#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U)
#define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U)
#define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\
(((v)&0x3U) << 0U)
#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\
(0x1U)
#define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U)
#define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U)
#define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\
(((v)&0x3U) << 0U)
#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U)
#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U)
#endif

687
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,548 +59,145 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 falcon_falcon_irqsset_r(void)
{
return 0x00000000U;
}
static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
{
return 0x40U;
}
static inline u32 falcon_falcon_irqsclr_r(void)
{
return 0x00000004U;
}
static inline u32 falcon_falcon_irqstat_r(void)
{
return 0x00000008U;
}
static inline u32 falcon_falcon_irqstat_halt_true_f(void)
{
return 0x10U;
}
static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
{
return 0x20U;
}
static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
{
return 0x40U;
}
static inline u32 falcon_falcon_irqmode_r(void)
{
return 0x0000000cU;
}
static inline u32 falcon_falcon_irqmset_r(void)
{
return 0x00000010U;
}
static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqmclr_r(void)
{
return 0x00000014U;
}
static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_irqmask_r(void)
{
return 0x00000018U;
}
static inline u32 falcon_falcon_irqdest_r(void)
{
return 0x0000001cU;
}
static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
{
return (v & 0x1U) << 17U;
}
static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
{
return (v & 0x1U) << 18U;
}
static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
{
return (v & 0x1U) << 19U;
}
static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
{
return (v & 0x1U) << 20U;
}
static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
{
return (v & 0x1U) << 21U;
}
static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
{
return (v & 0x1U) << 22U;
}
static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
{
return (v & 0x1U) << 23U;
}
static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 falcon_falcon_curctx_r(void)
{
return 0x00000050U;
}
static inline u32 falcon_falcon_nxtctx_r(void)
{
return 0x00000054U;
}
static inline u32 falcon_falcon_mailbox0_r(void)
{
return 0x00000040U;
}
static inline u32 falcon_falcon_mailbox1_r(void)
{
return 0x00000044U;
}
static inline u32 falcon_falcon_itfen_r(void)
{
return 0x00000048U;
}
static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
{
return 0x1U;
}
static inline u32 falcon_falcon_idlestate_r(void)
{
return 0x0000004cU;
}
static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
{
return (r >> 1U) & 0x7fffU;
}
static inline u32 falcon_falcon_os_r(void)
{
return 0x00000080U;
}
static inline u32 falcon_falcon_engctl_r(void)
{
return 0x000000a4U;
}
static inline u32 falcon_falcon_cpuctl_r(void)
{
return 0x00000100U;
}
static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 falcon_falcon_cpuctl_stopped_m(void)
{
return U32(0x1U) << 5U;
}
static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
{
return (r >> 6U) & 0x1U;
}
static inline u32 falcon_falcon_cpuctl_alias_r(void)
{
return 0x00000130U;
}
static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_imemc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_imemc_offs_f(u32 v)
{
return (v & 0x3fU) << 2U;
}
static inline u32 falcon_falcon_imemc_blk_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 falcon_falcon_imemc_secure_f(u32 v)
{
return (v & 0x1U) << 28U;
}
static inline u32 falcon_falcon_imemd_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_imemt_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_sctl_r(void)
{
return 0x00000240U;
}
static inline u32 falcon_falcon_mmu_phys_sec_r(void)
{
return 0x00100ce4U;
}
static inline u32 falcon_falcon_bootvec_r(void)
{
return 0x00000104U;
}
static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 falcon_falcon_dmactl_r(void)
{
return 0x0000010cU;
}
static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_hwcfg_r(void)
{
return 0x00000108U;
}
static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
{
return (r >> 0U) & 0x1ffU;
}
static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
{
return (r >> 9U) & 0x1ffU;
}
static inline u32 falcon_falcon_dmatrfbase_r(void)
{
return 0x00000110U;
}
static inline u32 falcon_falcon_dmatrfbase1_r(void)
{
return 0x00000128U;
}
static inline u32 falcon_falcon_dmatrfmoffs_r(void)
{
return 0x00000114U;
}
static inline u32 falcon_falcon_dmatrfcmd_r(void)
{
return 0x00000118U;
}
static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
{
return (v & 0x7U) << 8U;
}
static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
{
return (v & 0x7U) << 12U;
}
static inline u32 falcon_falcon_dmatrffboffs_r(void)
{
return 0x0000011cU;
}
static inline u32 falcon_falcon_imctl_debug_r(void)
{
return 0x0000015cU;
}
static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v)
{
return (v & 0x7U) << 24U;
}
static inline u32 falcon_falcon_imstat_r(void)
{
return 0x00000144U;
}
static inline u32 falcon_falcon_traceidx_r(void)
{
return 0x00000148U;
}
static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 falcon_falcon_traceidx_idx_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 falcon_falcon_tracepc_r(void)
{
return 0x0000014cU;
}
static inline u32 falcon_falcon_tracepc_pc_v(u32 r)
{
return (r >> 0U) & 0xffffffU;
}
static inline u32 falcon_falcon_exterraddr_r(void)
{
return 0x00000168U;
}
static inline u32 falcon_falcon_exterrstat_r(void)
{
return 0x0000016cU;
}
static inline u32 falcon_falcon_exterrstat_valid_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
{
return 0x00000001U;
}
static inline u32 falcon_falcon_icd_cmd_r(void)
{
return 0x00000200U;
}
static inline u32 falcon_falcon_icd_cmd_opc_s(void)
{
return 4U;
}
static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 falcon_falcon_icd_cmd_opc_m(void)
{
return U32(0xfU) << 0U;
}
static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
{
return 0x8U;
}
static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
{
return 0xeU;
}
static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
{
return (v & 0x1fU) << 8U;
}
static inline u32 falcon_falcon_icd_rdata_r(void)
{
return 0x0000020cU;
}
static inline u32 falcon_falcon_dmemc_r(u32 i)
{
return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
{
return (v & 0x3fU) << 2U;
}
static inline u32 falcon_falcon_dmemc_offs_m(void)
{
return U32(0x3fU) << 2U;
}
static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_dmemc_blk_m(void)
{
return U32(0xffU) << 8U;
}
static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
{
return (v & 0x1U) << 25U;
}
static inline u32 falcon_falcon_dmemd_r(u32 i)
{
return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 falcon_falcon_debug1_r(void)
{
return 0x00000090U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
{
return 1U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
{
return 0x0U;
}
static inline u32 falcon_falcon_debuginfo_r(void)
{
return 0x00000094U;
}
#define falcon_falcon_irqsset_r() (0x00000000U)
#define falcon_falcon_irqsset_swgen0_set_f() (0x40U)
#define falcon_falcon_irqsclr_r() (0x00000004U)
#define falcon_falcon_irqstat_r() (0x00000008U)
#define falcon_falcon_irqstat_halt_true_f() (0x10U)
#define falcon_falcon_irqstat_exterr_true_f() (0x20U)
#define falcon_falcon_irqstat_swgen0_true_f() (0x40U)
#define falcon_falcon_irqmode_r() (0x0000000cU)
#define falcon_falcon_irqmset_r() (0x00000010U)
#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqmclr_r() (0x00000014U)
#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_irqmask_r() (0x00000018U)
#define falcon_falcon_irqdest_r() (0x0000001cU)
#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U)
#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U)
#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U)
#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U)
#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U)
#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U)
#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U)
#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U)
#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U)
#define falcon_falcon_curctx_r() (0x00000050U)
#define falcon_falcon_nxtctx_r() (0x00000054U)
#define falcon_falcon_mailbox0_r() (0x00000040U)
#define falcon_falcon_mailbox1_r() (0x00000044U)
#define falcon_falcon_itfen_r() (0x00000048U)
#define falcon_falcon_itfen_ctxen_enable_f() (0x1U)
#define falcon_falcon_idlestate_r() (0x0000004cU)
#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U)
#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU)
#define falcon_falcon_os_r() (0x00000080U)
#define falcon_falcon_engctl_r() (0x000000a4U)
#define falcon_falcon_cpuctl_r() (0x00000100U)
#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define falcon_falcon_cpuctl_alias_r() (0x00000130U)
#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U)
#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U)
#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U)
#define falcon_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemt_r(i)\
(nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_sctl_r() (0x00000240U)
#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define falcon_falcon_bootvec_r() (0x00000104U)
#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U)
#define falcon_falcon_dmactl_r() (0x0000010cU)
#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_hwcfg_r() (0x00000108U)
#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
#define falcon_falcon_dmatrfbase_r() (0x00000110U)
#define falcon_falcon_dmatrfbase1_r() (0x00000128U)
#define falcon_falcon_dmatrfmoffs_r() (0x00000114U)
#define falcon_falcon_dmatrfcmd_r() (0x00000118U)
#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U)
#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U)
#define falcon_falcon_dmatrffboffs_r() (0x0000011cU)
#define falcon_falcon_imctl_debug_r() (0x0000015cU)
#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U)
#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U)
#define falcon_falcon_imstat_r() (0x00000144U)
#define falcon_falcon_traceidx_r() (0x00000148U)
#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU)
#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U)
#define falcon_falcon_tracepc_r() (0x0000014cU)
#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU)
#define falcon_falcon_exterraddr_r() (0x0010a168U)
#define falcon_falcon_exterrstat_r() (0x0010a16cU)
#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U)
#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U)
#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U)
#define falcon_falcon_icd_cmd_r() (0x00000200U)
#define falcon_falcon_icd_cmd_opc_s() (4U)
#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U)
#define falcon_falcon_icd_rdata_r() (0x0000020cU)
#define falcon_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U)
#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U)
#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U)
#define falcon_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_debug1_r() (0x00000090U)
#define falcon_falcon_debug1_ctxsw_mode_s() (1U)
#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U)
#define falcon_falcon_debuginfo_r() (0x00000094U)
#endif

632
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,508 +59,130 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fb_fbhub_num_active_ltcs_r(void)
{
return 0x00100800U;
}
static inline u32 fb_mmu_ctrl_r(void)
{
return 0x00100c80U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 fb_priv_mmu_phy_secure_r(void)
{
return 0x00100ce4U;
}
static inline u32 fb_mmu_invalidate_pdb_r(void)
{
return 0x00100cb8U;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_invalidate_r(void)
{
return 0x00100cbcU;
}
static inline u32 fb_mmu_invalidate_all_va_true_f(void)
{
return 0x1U;
}
static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
{
return 1U;
}
static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
{
return 0x4U;
}
static inline u32 fb_mmu_invalidate_replay_s(void)
{
return 3U;
}
static inline u32 fb_mmu_invalidate_replay_f(u32 v)
{
return (v & 0x7U) << 3U;
}
static inline u32 fb_mmu_invalidate_replay_m(void)
{
return U32(0x7U) << 3U;
}
static inline u32 fb_mmu_invalidate_replay_v(u32 r)
{
return (r >> 3U) & 0x7U;
}
static inline u32 fb_mmu_invalidate_replay_none_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_replay_start_f(void)
{
return 0x8U;
}
static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
{
return 0x10U;
}
static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
{
return 0x18U;
}
static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
{
return 0x20U;
}
static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
{
return 0x20U;
}
static inline u32 fb_mmu_invalidate_sys_membar_s(void)
{
return 1U;
}
static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 fb_mmu_invalidate_sys_membar_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
{
return (r >> 6U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
{
return 0x40U;
}
static inline u32 fb_mmu_invalidate_ack_s(void)
{
return 2U;
}
static inline u32 fb_mmu_invalidate_ack_f(u32 v)
{
return (v & 0x3U) << 7U;
}
static inline u32 fb_mmu_invalidate_ack_m(void)
{
return U32(0x3U) << 7U;
}
static inline u32 fb_mmu_invalidate_ack_v(u32 r)
{
return (r >> 7U) & 0x3U;
}
static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
{
return 0x100U;
}
static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
{
return 0x80U;
}
static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
{
return 6U;
}
static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
{
return (v & 0x3fU) << 9U;
}
static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
{
return U32(0x3fU) << 9U;
}
static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
{
return (r >> 9U) & 0x3fU;
}
static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
{
return 5U;
}
static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
{
return (v & 0x1fU) << 15U;
}
static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
{
return U32(0x1fU) << 15U;
}
static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
{
return (r >> 15U) & 0x1fU;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
{
return 1U;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
{
return (v & 0x1U) << 20U;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
{
return U32(0x1U) << 20U;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
{
return (r >> 20U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
{
return 0x100000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
{
return 3U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
{
return (v & 0x7U) << 24U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
{
return U32(0x7U) << 24U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
{
return (r >> 24U) & 0x7U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
{
return 0x1000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
{
return 0x2000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
{
return 0x3000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
{
return 0x4000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
{
return 0x5000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
{
return 0x6000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
{
return 0x7000000U;
}
static inline u32 fb_mmu_invalidate_trigger_s(void)
{
return 1U;
}
static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 fb_mmu_invalidate_trigger_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_trigger_true_f(void)
{
return 0x80000000U;
}
static inline u32 fb_mmu_debug_wr_r(void)
{
return 0x00100cc8U;
}
static inline u32 fb_mmu_debug_wr_aperture_s(void)
{
return 2U;
}
static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 fb_mmu_debug_wr_aperture_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 fb_mmu_debug_wr_vol_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_wr_vol_true_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_debug_wr_vol_true_f(void)
{
return 0x4U;
}
static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
{
return 0x0000000cU;
}
static inline u32 fb_mmu_debug_rd_r(void)
{
return 0x00100cccU;
}
static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 fb_mmu_debug_rd_vol_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
{
return 0x0000000cU;
}
static inline u32 fb_mmu_debug_ctrl_r(void)
{
return 0x00100cc4U;
}
static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 fb_mmu_debug_ctrl_debug_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
{
return 0x10000U;
}
static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_priv_level_mask_r(void)
{
return 0x00100cdcU;
}
static inline u32 fb_mmu_priv_level_mask_write_violation_m(void)
{
return U32(0x1U) << 7U;
}
static inline u32 fb_niso_flush_sysmem_addr_r(void)
{
return 0x00100c10U;
}
static inline u32 fb_mmu_local_memory_range_r(void)
{
return 0x00100ce0U;
}
static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r)
{
return (r >> 4U) & 0x3fU;
}
static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 fb_fbpa_fbio_delay_r(void)
{
return 0x009a065cU;
}
static inline u32 fb_fbpa_fbio_delay_src_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 fb_fbpa_fbio_delay_src_m(void)
{
return U32(0xfU) << 0U;
}
static inline u32 fb_fbpa_fbio_delay_src_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 fb_fbpa_fbio_delay_src_max_v(void)
{
return 0x00000002U;
}
static inline u32 fb_fbpa_fbio_delay_priv_f(u32 v)
{
return (v & 0xfU) << 4U;
}
static inline u32 fb_fbpa_fbio_delay_priv_m(void)
{
return U32(0xfU) << 4U;
}
static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r)
{
return (r >> 4U) & 0xfU;
}
static inline u32 fb_fbpa_fbio_delay_priv_max_v(void)
{
return 0x00000002U;
}
static inline u32 fb_fbpa_fbio_cmd_delay_r(void)
{
return 0x009a08e0U;
}
static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void)
{
return U32(0xfU) << 0U;
}
static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_max_v(void)
{
return 0x00000001U;
}
static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_f(u32 v)
{
return (v & 0xfU) << 4U;
}
static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void)
{
return U32(0xfU) << 4U;
}
static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r)
{
return (r >> 4U) & 0xfU;
}
static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_max_v(void)
{
return 0x00000001U;
}
static inline u32 fb_niso_scrub_status_r(void)
{
return 0x00100b20U;
}
static inline u32 fb_niso_scrub_status_flag_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 fb_fbpa_fbio_iref_byte_rx_ctrl_r(void)
{
return 0x009a0eb0U;
}
#define fb_fbhub_num_active_ltcs_r() (0x00100800U)
#define fb_mmu_ctrl_r() (0x00100c80U)
#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U)
#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U)
#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU)
#define fb_priv_mmu_phy_secure_r() (0x00100ce4U)
#define fb_mmu_invalidate_pdb_r() (0x00100cb8U)
#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U)
#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U)
#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_invalidate_r() (0x00100cbcU)
#define fb_mmu_invalidate_all_va_true_f() (0x1U)
#define fb_mmu_invalidate_all_pdb_true_f() (0x2U)
#define fb_mmu_invalidate_hubtlb_only_s() (1U)
#define fb_mmu_invalidate_hubtlb_only_f(v) (((v)&0x1U) << 2U)
#define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U)
#define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U)
#define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U)
#define fb_mmu_invalidate_replay_s() (3U)
#define fb_mmu_invalidate_replay_f(v) (((v)&0x7U) << 3U)
#define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U)
#define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U)
#define fb_mmu_invalidate_replay_none_f() (0x0U)
#define fb_mmu_invalidate_replay_start_f() (0x8U)
#define fb_mmu_invalidate_replay_start_ack_all_f() (0x10U)
#define fb_mmu_invalidate_replay_cancel_targeted_f() (0x18U)
#define fb_mmu_invalidate_replay_cancel_global_f() (0x20U)
#define fb_mmu_invalidate_replay_cancel_f() (0x20U)
#define fb_mmu_invalidate_sys_membar_s() (1U)
#define fb_mmu_invalidate_sys_membar_f(v) (((v)&0x1U) << 6U)
#define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U)
#define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U)
#define fb_mmu_invalidate_sys_membar_true_f() (0x40U)
#define fb_mmu_invalidate_ack_s() (2U)
#define fb_mmu_invalidate_ack_f(v) (((v)&0x3U) << 7U)
#define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U)
#define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U)
#define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U)
#define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U)
#define fb_mmu_invalidate_ack_ack_globally_f() (0x80U)
#define fb_mmu_invalidate_cancel_client_id_s() (6U)
#define fb_mmu_invalidate_cancel_client_id_f(v) (((v)&0x3fU) << 9U)
#define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U)
#define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU)
#define fb_mmu_invalidate_cancel_gpc_id_s() (5U)
#define fb_mmu_invalidate_cancel_gpc_id_f(v) (((v)&0x1fU) << 15U)
#define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U)
#define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU)
#define fb_mmu_invalidate_cancel_client_type_s() (1U)
#define fb_mmu_invalidate_cancel_client_type_f(v) (((v)&0x1U) << 20U)
#define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U)
#define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U)
#define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U)
#define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U)
#define fb_mmu_invalidate_cancel_cache_level_s() (3U)
#define fb_mmu_invalidate_cancel_cache_level_f(v) (((v)&0x7U) << 24U)
#define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U)
#define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U)
#define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U)
#define fb_mmu_invalidate_cancel_cache_level_pte_only_f() (0x1000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f() (0x2000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f() (0x3000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f() (0x4000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f() (0x5000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U)
#define fb_mmu_invalidate_trigger_s() (1U)
#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U)
#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U)
#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_invalidate_trigger_true_f() (0x80000000U)
#define fb_mmu_debug_wr_r() (0x00100cc8U)
#define fb_mmu_debug_wr_aperture_s() (2U)
#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_wr_vol_false_f() (0x0U)
#define fb_mmu_debug_wr_vol_true_v() (0x00000001U)
#define fb_mmu_debug_wr_vol_true_f() (0x4U)
#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_rd_r() (0x00100cccU)
#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_rd_vol_false_f() (0x0U)
#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_ctrl_r() (0x00100cc4U)
#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U)
#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U)
#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U)
#define fb_mmu_debug_ctrl_debug_enabled_f() (0x10000U)
#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U)
#define fb_mmu_debug_ctrl_debug_disabled_f() (0x0U)
#define fb_mmu_priv_level_mask_r() (0x00100cdcU)
#define fb_mmu_priv_level_mask_write_violation_m() (U32(0x1U) << 7U)
#define fb_niso_flush_sysmem_addr_r() (0x00100c10U)
#define fb_mmu_local_memory_range_r() (0x00100ce0U)
#define fb_mmu_local_memory_range_lower_scale_v(r) (((r) >> 0U) & 0xfU)
#define fb_mmu_local_memory_range_lower_mag_v(r) (((r) >> 4U) & 0x3fU)
#define fb_mmu_local_memory_range_ecc_mode_v(r) (((r) >> 30U) & 0x1U)
#define fb_fbpa_fbio_delay_r() (0x009a065cU)
#define fb_fbpa_fbio_delay_src_f(v) (((v)&0xfU) << 0U)
#define fb_fbpa_fbio_delay_src_m() (U32(0xfU) << 0U)
#define fb_fbpa_fbio_delay_src_v(r) (((r) >> 0U) & 0xfU)
#define fb_fbpa_fbio_delay_src_max_v() (0x00000002U)
#define fb_fbpa_fbio_delay_priv_f(v) (((v)&0xfU) << 4U)
#define fb_fbpa_fbio_delay_priv_m() (U32(0xfU) << 4U)
#define fb_fbpa_fbio_delay_priv_v(r) (((r) >> 4U) & 0xfU)
#define fb_fbpa_fbio_delay_priv_max_v() (0x00000002U)
#define fb_fbpa_fbio_cmd_delay_r() (0x009a08e0U)
#define fb_fbpa_fbio_cmd_delay_cmd_src_f(v) (((v)&0xfU) << 0U)
#define fb_fbpa_fbio_cmd_delay_cmd_src_m() (U32(0xfU) << 0U)
#define fb_fbpa_fbio_cmd_delay_cmd_src_v(r) (((r) >> 0U) & 0xfU)
#define fb_fbpa_fbio_cmd_delay_cmd_src_max_v() (0x00000001U)
#define fb_fbpa_fbio_cmd_delay_cmd_priv_f(v) (((v)&0xfU) << 4U)
#define fb_fbpa_fbio_cmd_delay_cmd_priv_m() (U32(0xfU) << 4U)
#define fb_fbpa_fbio_cmd_delay_cmd_priv_v(r) (((r) >> 4U) & 0xfU)
#define fb_fbpa_fbio_cmd_delay_cmd_priv_max_v() (0x00000001U)
#define fb_niso_scrub_status_r() (0x00100b20U)
#define fb_niso_scrub_status_flag_v(r) (((r) >> 0U) & 0x1U)
#define fb_fbpa_fbio_iref_byte_rx_ctrl_r() (0x009a0eb0U)
#endif

12
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fbpa_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,12 +59,6 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fbpa_cstatus_r(void)
{
return 0x009a020cU;
}
static inline u32 fbpa_cstatus_ramamount_v(u32 r)
{
return (r >> 0U) & 0x1ffffU;
}
#define fbpa_cstatus_r() (0x009a020cU)
#define fbpa_cstatus_ramamount_v(r) (((r) >> 0U) & 0x1ffffU)
#endif

826
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,648 +59,184 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fifo_bar1_base_r(void)
{
return 0x00002254U;
}
static inline u32 fifo_bar1_base_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 fifo_bar1_base_valid_false_f(void)
{
return 0x0U;
}
static inline u32 fifo_bar1_base_valid_true_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_runlist_base_r(void)
{
return 0x00002270U;
}
static inline u32 fifo_runlist_base_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 fifo_runlist_base_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 fifo_runlist_r(void)
{
return 0x00002274U;
}
static inline u32 fifo_runlist_engine_f(u32 v)
{
return (v & 0xfU) << 20U;
}
static inline u32 fifo_eng_runlist_base_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_eng_runlist_base__size_1_v(void)
{
return 0x00000007U;
}
static inline u32 fifo_eng_runlist_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_eng_runlist__size_1_v(void)
{
return 0x00000007U;
}
static inline u32 fifo_eng_runlist_length_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 fifo_eng_runlist_length_max_v(void)
{
return 0x0000ffffU;
}
static inline u32 fifo_eng_runlist_pending_true_f(void)
{
return 0x100000U;
}
static inline u32 fifo_pb_timeslice_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_pb_timeslice_timeout_16_f(void)
{
return 0x10U;
}
static inline u32 fifo_pb_timeslice_timescale_0_f(void)
{
return 0x0U;
}
static inline u32 fifo_pb_timeslice_enable_true_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_pbdma_map_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_intr_0_r(void)
{
return 0x00002100U;
}
static inline u32 fifo_intr_0_bind_error_pending_f(void)
{
return 0x1U;
}
static inline u32 fifo_intr_0_bind_error_reset_f(void)
{
return 0x1U;
}
static inline u32 fifo_intr_0_sched_error_pending_f(void)
{
return 0x100U;
}
static inline u32 fifo_intr_0_sched_error_reset_f(void)
{
return 0x100U;
}
static inline u32 fifo_intr_0_chsw_error_pending_f(void)
{
return 0x10000U;
}
static inline u32 fifo_intr_0_chsw_error_reset_f(void)
{
return 0x10000U;
}
static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
{
return 0x800000U;
}
static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
{
return 0x800000U;
}
static inline u32 fifo_intr_0_lb_error_pending_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_intr_0_lb_error_reset_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
{
return 0x2000000U;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
{
return 0x8000000U;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
{
return 0x8000000U;
}
static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
{
return 0x20000000U;
}
static inline u32 fifo_intr_0_runlist_event_pending_f(void)
{
return 0x40000000U;
}
static inline u32 fifo_intr_0_channel_intr_pending_f(void)
{
return 0x80000000U;
}
static inline u32 fifo_intr_en_0_r(void)
{
return 0x00002140U;
}
static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
{
return (v & 0x1U) << 8U;
}
static inline u32 fifo_intr_en_0_sched_error_m(void)
{
return U32(0x1U) << 8U;
}
static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
{
return (v & 0x1U) << 28U;
}
static inline u32 fifo_intr_en_0_mmu_fault_m(void)
{
return U32(0x1U) << 28U;
}
static inline u32 fifo_intr_en_1_r(void)
{
return 0x00002528U;
}
static inline u32 fifo_intr_bind_error_r(void)
{
return 0x0000252cU;
}
static inline u32 fifo_intr_sched_error_r(void)
{
return 0x0000254cU;
}
static inline u32 fifo_intr_sched_error_code_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
{
return 0x0000000aU;
}
static inline u32 fifo_intr_chsw_error_r(void)
{
return 0x0000256cU;
}
static inline u32 fifo_intr_mmu_fault_id_r(void)
{
return 0x0000259cU;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
{
return 0x0U;
}
static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
{
return (r >> 0U) & 0xfffffffU;
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
{
return nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
{
return (r >> 20U) & 0x1U;
}
static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
{
return (r >> 8U) & 0x7fU;
}
static inline u32 fifo_intr_pbdma_id_r(void)
{
return 0x000025a0U;
}
static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
{
return (r >> (0U + i*1U)) & 0x1U;
}
static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
{
return 0x00000004U;
}
static inline u32 fifo_intr_runlist_r(void)
{
return 0x00002a00U;
}
static inline u32 fifo_fb_timeout_r(void)
{
return 0x00002a04U;
}
static inline u32 fifo_fb_timeout_period_m(void)
{
return U32(0x3fffffffU) << 0U;
}
static inline u32 fifo_fb_timeout_period_max_f(void)
{
return 0x3fffffffU;
}
static inline u32 fifo_error_sched_disable_r(void)
{
return 0x0000262cU;
}
static inline u32 fifo_sched_disable_r(void)
{
return 0x00002630U;
}
static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 fifo_sched_disable_runlist_m(u32 i)
{
return U32(0x1U) << (0U + i*1U);
}
static inline u32 fifo_sched_disable_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_preempt_r(void)
{
return 0x00002634U;
}
static inline u32 fifo_preempt_pending_true_f(void)
{
return 0x100000U;
}
static inline u32 fifo_preempt_type_channel_f(void)
{
return 0x0U;
}
static inline u32 fifo_preempt_type_tsg_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_preempt_chid_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 fifo_preempt_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 fifo_trigger_mmu_fault_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
{
return (v & 0x1fU) << 0U;
}
static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
{
return (v & 0x1U) << 8U;
}
static inline u32 fifo_engine_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_engine_status__size_1_v(void)
{
return 0x00000009U;
}
static inline u32 fifo_engine_status_id_v(u32 r)
{
return (r >> 0U) & 0xfffU;
}
static inline u32 fifo_engine_status_id_type_v(u32 r)
{
return (r >> 12U) & 0x1U;
}
static inline u32 fifo_engine_status_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctx_status_v(u32 r)
{
return (r >> 13U) & 0x7U;
}
static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_ctx_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
{
return 0x00000005U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
{
return 0x00000006U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
{
return 0x00000007U;
}
static inline u32 fifo_engine_status_next_id_v(u32 r)
{
return (r >> 16U) & 0xfffU;
}
static inline u32 fifo_engine_status_next_id_type_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 fifo_engine_status_next_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_next_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_faulted_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 fifo_engine_status_faulted_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_engine_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 fifo_engine_status_engine_idle_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_engine_busy_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctxsw_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
{
return 0x8000U;
}
static inline u32 fifo_pbdma_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_pbdma_status__size_1_v(void)
{
return 0x00000004U;
}
static inline u32 fifo_pbdma_status_id_v(u32 r)
{
return (r >> 0U) & 0xfffU;
}
static inline u32 fifo_pbdma_status_id_type_v(u32 r)
{
return (r >> 12U) & 0x1U;
}
static inline u32 fifo_pbdma_status_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
{
return (r >> 13U) & 0x7U;
}
static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
{
return 0x00000005U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
{
return 0x00000006U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
{
return 0x00000007U;
}
static inline u32 fifo_pbdma_status_next_id_v(u32 r)
{
return (r >> 16U) & 0xfffU;
}
static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chsw_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_lo_r(void)
{
return 0x00002a70U;
}
static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_hi_r(void)
{
return 0x00002a74U;
}
static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_size_r(void)
{
return 0x00002a78U;
}
static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
{
return (v & 0x3fffU) << 0U;
}
static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
{
return 0x00001200U;
}
static inline u32 fifo_replay_fault_buffer_get_r(void)
{
return 0x00002a7cU;
}
static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
{
return (v & 0x3fffU) << 0U;
}
static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_put_r(void)
{
return 0x00002a80U;
}
static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
{
return (v & 0x3fffU) << 0U;
}
static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_info_r(void)
{
return 0x00002a84U;
}
static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v)
{
return (v & 0x1U) << 28U;
}
static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void)
{
return 0x00000001U;
}
#define fifo_bar1_base_r() (0x00002254U)
#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU)
#define fifo_bar1_base_valid_false_f() (0x0U)
#define fifo_bar1_base_valid_true_f() (0x10000000U)
#define fifo_runlist_base_r() (0x00002270U)
#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define fifo_runlist_base_target_vid_mem_f() (0x0U)
#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U)
#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U)
#define fifo_runlist_r() (0x00002274U)
#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U)
#define fifo_eng_runlist_base_r(i)\
(nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist_base__size_1_v() (0x00000007U)
#define fifo_eng_runlist_r(i)\
(nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist__size_1_v() (0x00000007U)
#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U)
#define fifo_eng_runlist_length_max_v() (0x0000ffffU)
#define fifo_eng_runlist_pending_true_f() (0x100000U)
#define fifo_pb_timeslice_r(i)\
(nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_pb_timeslice_timeout_16_f() (0x10U)
#define fifo_pb_timeslice_timescale_0_f() (0x0U)
#define fifo_pb_timeslice_enable_true_f() (0x10000000U)
#define fifo_pbdma_map_r(i)\
(nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_intr_0_r() (0x00002100U)
#define fifo_intr_0_bind_error_pending_f() (0x1U)
#define fifo_intr_0_bind_error_reset_f() (0x1U)
#define fifo_intr_0_sched_error_pending_f() (0x100U)
#define fifo_intr_0_sched_error_reset_f() (0x100U)
#define fifo_intr_0_chsw_error_pending_f() (0x10000U)
#define fifo_intr_0_chsw_error_reset_f() (0x10000U)
#define fifo_intr_0_fb_flush_timeout_pending_f() (0x800000U)
#define fifo_intr_0_fb_flush_timeout_reset_f() (0x800000U)
#define fifo_intr_0_lb_error_pending_f() (0x1000000U)
#define fifo_intr_0_lb_error_reset_f() (0x1000000U)
#define fifo_intr_0_replayable_fault_error_pending_f() (0x2000000U)
#define fifo_intr_0_dropped_mmu_fault_pending_f() (0x8000000U)
#define fifo_intr_0_dropped_mmu_fault_reset_f() (0x8000000U)
#define fifo_intr_0_mmu_fault_pending_f() (0x10000000U)
#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U)
#define fifo_intr_0_runlist_event_pending_f() (0x40000000U)
#define fifo_intr_0_channel_intr_pending_f() (0x80000000U)
#define fifo_intr_en_0_r() (0x00002140U)
#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U)
#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U)
#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U)
#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U)
#define fifo_intr_en_1_r() (0x00002528U)
#define fifo_intr_bind_error_r() (0x0000252cU)
#define fifo_intr_sched_error_r() (0x0000254cU)
#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U)
#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU)
#define fifo_intr_chsw_error_r() (0x0000256cU)
#define fifo_intr_mmu_fault_id_r() (0x0000259cU)
#define fifo_intr_mmu_fault_eng_id_graphics_v() (0x00000000U)
#define fifo_intr_mmu_fault_eng_id_graphics_f() (0x0U)
#define fifo_intr_mmu_fault_inst_r(i)\
(nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_inst_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define fifo_intr_mmu_fault_inst_ptr_align_shift_v() (0x0000000cU)
#define fifo_intr_mmu_fault_lo_r(i)\
(nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_hi_r(i)\
(nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_info_r(i)\
(nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_info_type_v(r) (((r) >> 0U) & 0x1fU)
#define fifo_intr_mmu_fault_info_client_type_v(r) (((r) >> 20U) & 0x1U)
#define fifo_intr_mmu_fault_info_client_type_gpc_v() (0x00000000U)
#define fifo_intr_mmu_fault_info_client_type_hub_v() (0x00000001U)
#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU)
#define fifo_intr_pbdma_id_r() (0x000025a0U)
#define fifo_intr_pbdma_id_status_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define fifo_intr_pbdma_id_status_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U)
#define fifo_intr_pbdma_id_status__size_1_v() (0x00000004U)
#define fifo_intr_runlist_r() (0x00002a00U)
#define fifo_fb_timeout_r() (0x00002a04U)
#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U)
#define fifo_fb_timeout_period_max_f() (0x3fffffffU)
#define fifo_error_sched_disable_r() (0x0000262cU)
#define fifo_sched_disable_r() (0x00002630U)
#define fifo_sched_disable_runlist_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define fifo_sched_disable_runlist_m(i)\
(U32(0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_true_v() (0x00000001U)
#define fifo_preempt_r() (0x00002634U)
#define fifo_preempt_pending_true_f() (0x100000U)
#define fifo_preempt_type_channel_f() (0x0U)
#define fifo_preempt_type_tsg_f() (0x1000000U)
#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U)
#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U)
#define fifo_trigger_mmu_fault_r(i)\
(nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U)
#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U)
#define fifo_engine_status_r(i)\
(nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_engine_status__size_1_v() (0x00000009U)
#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU)
#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U)
#define fifo_engine_status_id_type_chid_v() (0x00000000U)
#define fifo_engine_status_id_type_tsgid_v() (0x00000001U)
#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U)
#define fifo_engine_status_ctx_status_invalid_v() (0x00000000U)
#define fifo_engine_status_ctx_status_valid_v() (0x00000001U)
#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U)
#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U)
#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U)
#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU)
#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U)
#define fifo_engine_status_next_id_type_chid_v() (0x00000000U)
#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U)
#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U)
#define fifo_engine_status_faulted_true_v() (0x00000001U)
#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U)
#define fifo_engine_status_engine_idle_v() (0x00000000U)
#define fifo_engine_status_engine_busy_v() (0x00000001U)
#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U)
#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U)
#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U)
#define fifo_pbdma_status_r(i)\
(nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_pbdma_status__size_1_v() (0x00000004U)
#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU)
#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U)
#define fifo_pbdma_status_id_type_chid_v() (0x00000000U)
#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U)
#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U)
#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U)
#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U)
#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U)
#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U)
#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU)
#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U)
#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U)
#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U)
#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U)
#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U)
#define fifo_replay_fault_buffer_lo_r() (0x00002a70U)
#define fifo_replay_fault_buffer_lo_enable_v(r) (((r) >> 0U) & 0x1U)
#define fifo_replay_fault_buffer_lo_enable_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_lo_enable_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_lo_base_f(v) (((v)&0xfffffU) << 12U)
#define fifo_replay_fault_buffer_lo_base_reset_v() (0x00000000U)
#define fifo_replay_fault_buffer_hi_r() (0x00002a74U)
#define fifo_replay_fault_buffer_hi_base_f(v) (((v)&0xffU) << 0U)
#define fifo_replay_fault_buffer_hi_base_reset_v() (0x00000000U)
#define fifo_replay_fault_buffer_size_r() (0x00002a78U)
#define fifo_replay_fault_buffer_size_hw_f(v) (((v)&0x3fffU) << 0U)
#define fifo_replay_fault_buffer_size_hw_entries_v() (0x00001200U)
#define fifo_replay_fault_buffer_get_r() (0x00002a7cU)
#define fifo_replay_fault_buffer_get_offset_hw_f(v) (((v)&0x3fffU) << 0U)
#define fifo_replay_fault_buffer_get_offset_hw_init_v() (0x00000000U)
#define fifo_replay_fault_buffer_put_r() (0x00002a80U)
#define fifo_replay_fault_buffer_put_offset_hw_f(v) (((v)&0x3fffU) << 0U)
#define fifo_replay_fault_buffer_put_offset_hw_init_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_r() (0x00002a84U)
#define fifo_replay_fault_buffer_info_overflow_f(v) (((v)&0x1U) << 0U)
#define fifo_replay_fault_buffer_info_overflow_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_overflow_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_overflow_clear_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_write_nack_f(v) (((v)&0x1U) << 24U)
#define fifo_replay_fault_buffer_info_write_nack_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_write_nack_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_write_nack_clear_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(v)\
(((v)&0x1U) << 28U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v()\
(0x00000000U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v()\
(0x00000001U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v()\
(0x00000001U)
#endif

162
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_flush_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,132 +59,36 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 flush_l2_system_invalidate_r(void)
{
return 0x00070004U;
}
static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_flush_dirty_r(void)
{
return 0x00070010U;
}
static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_clean_comptags_r(void)
{
return 0x0007000cU;
}
static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_fb_flush_r(void)
{
return 0x00070000U;
}
static inline u32 flush_fb_flush_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_fb_flush_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_fb_flush_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_fb_flush_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_fb_flush_outstanding_true_v(void)
{
return 0x00000001U;
}
#define flush_l2_system_invalidate_r() (0x00070004U)
#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U)
#define flush_l2_system_invalidate_pending_busy_f() (0x1U)
#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U)
#define flush_l2_flush_dirty_r() (0x00070010U)
#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U)
#define flush_l2_flush_dirty_pending_empty_f() (0x0U)
#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U)
#define flush_l2_flush_dirty_pending_busy_f() (0x1U)
#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U)
#define flush_l2_flush_dirty_outstanding_false_f() (0x0U)
#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U)
#define flush_l2_clean_comptags_r() (0x0007000cU)
#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U)
#define flush_l2_clean_comptags_pending_empty_f() (0x0U)
#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U)
#define flush_l2_clean_comptags_pending_busy_f() (0x1U)
#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U)
#define flush_l2_clean_comptags_outstanding_false_f() (0x0U)
#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U)
#define flush_fb_flush_r() (0x00070000U)
#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_fb_flush_pending_busy_v() (0x00000001U)
#define flush_fb_flush_pending_busy_f() (0x1U)
#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_fb_flush_outstanding_true_v() (0x00000001U)
#endif

276
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,220 +59,62 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fuse_status_opt_gpc_r(void)
{
return 0x00021c1cU;
}
static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
{
return 0x00021944U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
{
return 0x00021948U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
{
return 0x1U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
{
return 0x0U;
}
static inline u32 fuse_status_opt_fbio_r(void)
{
return 0x00021c14U;
}
static inline u32 fuse_status_opt_fbio_data_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 fuse_status_opt_fbio_data_m(void)
{
return U32(0xffffU) << 0U;
}
static inline u32 fuse_status_opt_fbio_data_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
{
return nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fuse_status_opt_fbp_r(void)
{
return 0x00021d38U;
}
static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
{
return (r >> (0U + i*1U)) & 0x1U;
}
static inline u32 fuse_vin_cal_fuse_rev_r(void)
{
return 0x0002164cU;
}
static inline u32 fuse_vin_cal_fuse_rev_data_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 fuse_vin_cal_gpc0_r(void)
{
return 0x00021650U;
}
static inline u32 fuse_vin_cal_gpc0_icpt_int_data_s(void)
{
return 12U;
}
static inline u32 fuse_vin_cal_gpc0_icpt_int_data_v(u32 r)
{
return (r >> 16U) & 0xfffU;
}
static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_s(void)
{
return 2U;
}
static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_v(u32 r)
{
return (r >> 14U) & 0x3U;
}
static inline u32 fuse_vin_cal_gpc0_slope_int_data_s(void)
{
return 4U;
}
static inline u32 fuse_vin_cal_gpc0_slope_int_data_v(u32 r)
{
return (r >> 10U) & 0xfU;
}
static inline u32 fuse_vin_cal_gpc0_slope_frac_data_s(void)
{
return 10U;
}
static inline u32 fuse_vin_cal_gpc0_slope_frac_data_v(u32 r)
{
return (r >> 0U) & 0x3ffU;
}
static inline u32 fuse_vin_cal_gpc1_delta_r(void)
{
return 0x00021654U;
}
static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_s(void)
{
return 8U;
}
static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_v(u32 r)
{
return (r >> 14U) & 0xffU;
}
static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_s(void)
{
return 2U;
}
static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_v(u32 r)
{
return (r >> 12U) & 0x3U;
}
static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_s(void)
{
return 1U;
}
static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_v(u32 r)
{
return (r >> 22U) & 0x1U;
}
static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_s(void)
{
return 1U;
}
static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_v(u32 r)
{
return (r >> 10U) & 0x1U;
}
static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_s(void)
{
return 10U;
}
static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_v(u32 r)
{
return (r >> 0U) & 0x3ffU;
}
static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_s(void)
{
return 1U;
}
static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_v(u32 r)
{
return (r >> 11U) & 0x1U;
}
static inline u32 fuse_vin_cal_gpc2_delta_r(void)
{
return 0x00021658U;
}
static inline u32 fuse_vin_cal_gpc3_delta_r(void)
{
return 0x0002165cU;
}
static inline u32 fuse_vin_cal_gpc4_delta_r(void)
{
return 0x00021660U;
}
static inline u32 fuse_vin_cal_gpc5_delta_r(void)
{
return 0x00021664U;
}
static inline u32 fuse_vin_cal_shared_delta_r(void)
{
return 0x00021668U;
}
static inline u32 fuse_vin_cal_sram_delta_r(void)
{
return 0x0002166cU;
}
static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_s(void)
{
return 9U;
}
static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_v(u32 r)
{
return (r >> 13U) & 0x1ffU;
}
static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_s(void)
{
return 1U;
}
static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_v(u32 r)
{
return (r >> 12U) & 0x1U;
}
#define fuse_status_opt_gpc_r() (0x00021c1cU)
#define fuse_status_opt_tpc_gpc_r(i)\
(nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_tpc_gpc_r(i)\
(nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U)
#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0x3U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0x3U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0x3U)
#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U)
#define fuse_status_opt_fbio_r() (0x00021c14U)
#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U)
#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U)
#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU)
#define fuse_status_opt_rop_l2_fbp_r(i)\
(nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_status_opt_fbp_r() (0x00021d38U)
#define fuse_status_opt_fbp_idx_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U)
#define fuse_vin_cal_fuse_rev_r() (0x0002164cU)
#define fuse_vin_cal_fuse_rev_data_v(r) (((r) >> 0U) & 0x3U)
#define fuse_vin_cal_gpc0_r() (0x00021650U)
#define fuse_vin_cal_gpc0_icpt_int_data_s() (12U)
#define fuse_vin_cal_gpc0_icpt_int_data_v(r) (((r) >> 16U) & 0xfffU)
#define fuse_vin_cal_gpc0_icpt_frac_data_s() (2U)
#define fuse_vin_cal_gpc0_icpt_frac_data_v(r) (((r) >> 14U) & 0x3U)
#define fuse_vin_cal_gpc0_slope_int_data_s() (4U)
#define fuse_vin_cal_gpc0_slope_int_data_v(r) (((r) >> 10U) & 0xfU)
#define fuse_vin_cal_gpc0_slope_frac_data_s() (10U)
#define fuse_vin_cal_gpc0_slope_frac_data_v(r) (((r) >> 0U) & 0x3ffU)
#define fuse_vin_cal_gpc1_delta_r() (0x00021654U)
#define fuse_vin_cal_gpc1_delta_icpt_int_data_s() (8U)
#define fuse_vin_cal_gpc1_delta_icpt_int_data_v(r) (((r) >> 14U) & 0xffU)
#define fuse_vin_cal_gpc1_delta_icpt_frac_data_s() (2U)
#define fuse_vin_cal_gpc1_delta_icpt_frac_data_v(r) (((r) >> 12U) & 0x3U)
#define fuse_vin_cal_gpc1_delta_icpt_sign_data_s() (1U)
#define fuse_vin_cal_gpc1_delta_icpt_sign_data_v(r) (((r) >> 22U) & 0x1U)
#define fuse_vin_cal_gpc1_delta_slope_int_data_s() (1U)
#define fuse_vin_cal_gpc1_delta_slope_int_data_v(r) (((r) >> 10U) & 0x1U)
#define fuse_vin_cal_gpc1_delta_slope_frac_data_s() (10U)
#define fuse_vin_cal_gpc1_delta_slope_frac_data_v(r) (((r) >> 0U) & 0x3ffU)
#define fuse_vin_cal_gpc1_delta_slope_sign_data_s() (1U)
#define fuse_vin_cal_gpc1_delta_slope_sign_data_v(r) (((r) >> 11U) & 0x1U)
#define fuse_vin_cal_gpc2_delta_r() (0x00021658U)
#define fuse_vin_cal_gpc3_delta_r() (0x0002165cU)
#define fuse_vin_cal_gpc4_delta_r() (0x00021660U)
#define fuse_vin_cal_gpc5_delta_r() (0x00021664U)
#define fuse_vin_cal_shared_delta_r() (0x00021668U)
#define fuse_vin_cal_sram_delta_r() (0x0002166cU)
#define fuse_vin_cal_sram_delta_icpt_int_data_s() (9U)
#define fuse_vin_cal_sram_delta_icpt_int_data_v(r) (((r) >> 13U) & 0x1ffU)
#define fuse_vin_cal_sram_delta_icpt_frac_data_s() (1U)
#define fuse_vin_cal_sram_delta_icpt_frac_data_v(r) (((r) >> 12U) & 0x1U)
#endif

342
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,276 +59,72 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 gmmu_new_pde_is_pte_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pde_is_pte_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pde_aperture_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pde_aperture_invalid_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
{
return 0x2U;
}
static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
{
return 0x4U;
}
static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
{
return 0x6U;
}
static inline u32 gmmu_new_pde_address_sys_f(u32 v)
{
return (v & 0xffffffU) << 8U;
}
static inline u32 gmmu_new_pde_address_sys_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pde_vol_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pde_vol_true_f(void)
{
return 0x8U;
}
static inline u32 gmmu_new_pde_vol_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pde_address_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 gmmu_new_pde__size_v(void)
{
return 0x00000008U;
}
static inline u32 gmmu_new_dual_pde_is_pte_w(void)
{
return 0U;
}
static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
{
return 0U;
}
static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
{
return 0x2U;
}
static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
{
return 0x4U;
}
static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
{
return 0x6U;
}
static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
{
return 0U;
}
static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
{
return 2U;
}
static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
{
return 0x2U;
}
static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
{
return 0x4U;
}
static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
{
return 0x6U;
}
static inline u32 gmmu_new_dual_pde_vol_small_w(void)
{
return 2U;
}
static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
{
return 0x8U;
}
static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_dual_pde_vol_big_w(void)
{
return 0U;
}
static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
{
return 0x8U;
}
static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
{
return (v & 0xffffffU) << 8U;
}
static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
{
return 2U;
}
static inline u32 gmmu_new_dual_pde_address_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
{
return 0x00000008U;
}
static inline u32 gmmu_new_dual_pde__size_v(void)
{
return 0x00000010U;
}
static inline u32 gmmu_new_pte__size_v(void)
{
return 0x00000008U;
}
static inline u32 gmmu_new_pte_valid_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_valid_true_f(void)
{
return 0x1U;
}
static inline u32 gmmu_new_pte_valid_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pte_privilege_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_privilege_true_f(void)
{
return 0x20U;
}
static inline u32 gmmu_new_pte_privilege_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pte_address_sys_f(u32 v)
{
return (v & 0xffffffU) << 8U;
}
static inline u32 gmmu_new_pte_address_sys_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_address_vid_f(u32 v)
{
return (v & 0xffffffU) << 8U;
}
static inline u32 gmmu_new_pte_address_vid_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_vol_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_vol_true_f(void)
{
return 0x8U;
}
static inline u32 gmmu_new_pte_vol_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pte_aperture_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
{
return 0x4U;
}
static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
{
return 0x6U;
}
static inline u32 gmmu_new_pte_read_only_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_read_only_true_f(void)
{
return 0x40U;
}
static inline u32 gmmu_new_pte_comptagline_f(u32 v)
{
return (v & 0x3ffffU) << 4U;
}
static inline u32 gmmu_new_pte_comptagline_w(void)
{
return 1U;
}
static inline u32 gmmu_new_pte_kind_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 gmmu_new_pte_kind_w(void)
{
return 1U;
}
static inline u32 gmmu_new_pte_address_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 gmmu_pte_kind_f(u32 v)
{
return (v & 0xffU) << 4U;
}
static inline u32 gmmu_pte_kind_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_kind_invalid_v(void)
{
return 0x000000ffU;
}
static inline u32 gmmu_pte_kind_pitch_v(void)
{
return 0x00000000U;
}
#define gmmu_new_pde_is_pte_w() (0U)
#define gmmu_new_pde_is_pte_false_f() (0x0U)
#define gmmu_new_pde_aperture_w() (0U)
#define gmmu_new_pde_aperture_invalid_f() (0x0U)
#define gmmu_new_pde_aperture_video_memory_f() (0x2U)
#define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U)
#define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_pde_address_sys_f(v) (((v)&0xffffffU) << 8U)
#define gmmu_new_pde_address_sys_w() (0U)
#define gmmu_new_pde_vol_w() (0U)
#define gmmu_new_pde_vol_true_f() (0x8U)
#define gmmu_new_pde_vol_false_f() (0x0U)
#define gmmu_new_pde_address_shift_v() (0x0000000cU)
#define gmmu_new_pde__size_v() (0x00000008U)
#define gmmu_new_dual_pde_is_pte_w() (0U)
#define gmmu_new_dual_pde_is_pte_false_f() (0x0U)
#define gmmu_new_dual_pde_aperture_big_w() (0U)
#define gmmu_new_dual_pde_aperture_big_invalid_f() (0x0U)
#define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U)
#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U)
#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_dual_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U)
#define gmmu_new_dual_pde_address_big_sys_w() (0U)
#define gmmu_new_dual_pde_aperture_small_w() (2U)
#define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U)
#define gmmu_new_dual_pde_aperture_small_video_memory_f() (0x2U)
#define gmmu_new_dual_pde_aperture_small_sys_mem_coh_f() (0x4U)
#define gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_dual_pde_vol_small_w() (2U)
#define gmmu_new_dual_pde_vol_small_true_f() (0x8U)
#define gmmu_new_dual_pde_vol_small_false_f() (0x0U)
#define gmmu_new_dual_pde_vol_big_w() (0U)
#define gmmu_new_dual_pde_vol_big_true_f() (0x8U)
#define gmmu_new_dual_pde_vol_big_false_f() (0x0U)
#define gmmu_new_dual_pde_address_small_sys_f(v) (((v)&0xffffffU) << 8U)
#define gmmu_new_dual_pde_address_small_sys_w() (2U)
#define gmmu_new_dual_pde_address_shift_v() (0x0000000cU)
#define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U)
#define gmmu_new_dual_pde__size_v() (0x00000010U)
#define gmmu_new_pte__size_v() (0x00000008U)
#define gmmu_new_pte_valid_w() (0U)
#define gmmu_new_pte_valid_true_f() (0x1U)
#define gmmu_new_pte_valid_false_f() (0x0U)
#define gmmu_new_pte_privilege_w() (0U)
#define gmmu_new_pte_privilege_true_f() (0x20U)
#define gmmu_new_pte_privilege_false_f() (0x0U)
#define gmmu_new_pte_address_sys_f(v) (((v)&0xffffffU) << 8U)
#define gmmu_new_pte_address_sys_w() (0U)
#define gmmu_new_pte_address_vid_f(v) (((v)&0xffffffU) << 8U)
#define gmmu_new_pte_address_vid_w() (0U)
#define gmmu_new_pte_vol_w() (0U)
#define gmmu_new_pte_vol_true_f() (0x8U)
#define gmmu_new_pte_vol_false_f() (0x0U)
#define gmmu_new_pte_aperture_w() (0U)
#define gmmu_new_pte_aperture_video_memory_f() (0x0U)
#define gmmu_new_pte_aperture_sys_mem_coh_f() (0x4U)
#define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_pte_read_only_w() (0U)
#define gmmu_new_pte_read_only_true_f() (0x40U)
#define gmmu_new_pte_comptagline_f(v) (((v)&0x3ffffU) << 4U)
#define gmmu_new_pte_comptagline_w() (1U)
#define gmmu_new_pte_kind_f(v) (((v)&0xffU) << 24U)
#define gmmu_new_pte_kind_w() (1U)
#define gmmu_new_pte_address_shift_v() (0x0000000cU)
#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U)
#define gmmu_pte_kind_w() (1U)
#define gmmu_pte_kind_invalid_v() (0x000000ffU)
#define gmmu_pte_kind_pitch_v() (0x00000000U)
#endif

5223
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
View File

File diff suppressed because it is too large Load Diff

653
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ltc_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,504 +59,155 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
{
return 0x0014046cU;
}
static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
{
return 0x00140518U;
}
static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
{
return 0x0017e318U;
}
static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
{
return U32(0x1U) << 15U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
{
return 0x00140494U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
{
return (r >> 16U) & 0x3U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
{
return 0x00000000U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
{
return 0x00000002U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
{
return 0x0017e26cU;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
{
return 0x2U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
{
return 0x4U;
}
static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
{
return 0x0014046cU;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
{
return 0x0017e270U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
{
return (v & 0x3ffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
{
return 0x0017e274U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
{
return (v & 0x3ffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
{
return 0x0003ffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
{
return 0x0017e278U;
}
static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
{
return 0x0000000bU;
}
static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
{
return (r >> 0U) & 0x3ffffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
{
return 0x0017e27cU;
}
static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
{
return 0x0017e000U;
}
static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
{
return 0x0017e280U;
}
static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
{
return (r >> 24U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
{
return (r >> 28U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
{
return 0x0017e3f4U;
}
static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
{
return 0x0017e2acU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
{
return (v & 0x1fU) << 16U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
{
return 0x0017e338U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
{
return nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
{
return 0x00000004U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
{
return 0x0017e34cU;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
{
return 32U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
{
return (r >> 0U) & 0xffffffffU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
{
return 0x0017e2b0U;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
{
return 0x0017e214U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
{
return 0x00140214U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
{
return 0x00142214U;
}
static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_intr_r(void)
{
return 0x0017e20cU;
}
static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
{
return 0x100U;
}
static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
{
return 0x200U;
}
static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
{
return U32(0x1U) << 20U;
}
static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
{
return 0x1000000U;
}
static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
{
return 0x2000000U;
}
static inline u32 ltc_ltc0_lts0_intr_r(void)
{
return 0x0014040cU;
}
static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
{
return 0x0014051cU;
}
static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
{
return U32(0xffU) << 0U;
}
static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
{
return U32(0xffU) << 16U;
}
static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
{
return 0x0017e2a0U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
{
return (r >> 8U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
{
return 0x00000003U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
{
return 0x300U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
{
return (r >> 29U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
{
return 0x20000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
{
return 0x40000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
{
return 0x0017e2a4U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
{
return (r >> 8U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
{
return 0x00000003U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
{
return 0x300U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
{
return 0x10000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
{
return (r >> 29U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
{
return 0x20000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
{
return 0x40000000U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
{
return 0x001402a0U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
{
return 0x001402a4U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
{
return 0x001422a0U;
}
static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
{
return 0x001422a4U;
}
static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
{
return 0x0014058cU;
}
static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
{
return (r >> 16U) & 0x1fU;
}
#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x0014046cU)
#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00140518U)
#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017e318U)
#define ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m() (U32(0x1U) << 15U)
#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00140494U)
#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U)
#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e26cU)
#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U)
#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U)
#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU)
#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U)
#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x3ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x3ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU)
#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U)
#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU)
#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU)
#define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU)
#define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U)
#define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U)
#define ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(r)\
(((r) >> 0U) & 0xffffU)
#define ltc_ltcs_ltss_cbc_param_cache_line_size_v(r) (((r) >> 24U) & 0xfU)
#define ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU)
#define ltc_ltcs_ltss_cbc_param2_r() (0x0017e3f4U)
#define ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(r)\
(((r) >> 0U) & 0xffffU)
#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU)
#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\
(((v)&0x1fU) << 16U)
#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
(nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U)))
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\
(((v)&0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\
(U32(0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\
(((r) >> 0U) & 0xffffffffU)
#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e2b0U)
#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U)
#define ltc_ltcs_ltss_g_elpg_r() (0x0017e214U)
#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U)
#define ltc_ltc0_ltss_g_elpg_r() (0x00140214U)
#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U)
#define ltc_ltc1_ltss_g_elpg_r() (0x00142214U)
#define ltc_ltc1_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc1_ltss_g_elpg_flush_pending_v() (0x00000001U)
#define ltc_ltc1_ltss_g_elpg_flush_pending_f() (0x1U)
#define ltc_ltcs_ltss_intr_r() (0x0017e20cU)
#define ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() (0x100U)
#define ltc_ltcs_ltss_intr_ecc_ded_error_pending_f() (0x200U)
#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U)
#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m() (U32(0x1U) << 30U)
#define ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() (0x1000000U)
#define ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f() (0x2000000U)
#define ltc_ltc0_lts0_intr_r() (0x0014040cU)
#define ltc_ltc0_lts0_dstg_ecc_report_r() (0x0014051cU)
#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_m() (U32(0xffU) << 0U)
#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(r) (((r) >> 0U) & 0xffU)
#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_m() (U32(0xffU) << 16U)
#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(r) (((r) >> 16U) & 0xffU)
#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\
(((r) >> 8U) & 0xfU)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\
(0x00000003U)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\
(((r) >> 28U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\
(0x10000000U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\
(((r) >> 29U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\
(0x20000000U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\
(((r) >> 30U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\
(0x40000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e2a4U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\
(((r) >> 8U) & 0xfU)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\
(((r) >> 16U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\
(((r) >> 28U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\
(((r) >> 29U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\
(0x20000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\
(((r) >> 30U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U)
#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x001402a0U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x001402a4U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U)
#define ltc_ltc1_ltss_tstg_cmgmt0_r() (0x001422a0U)
#define ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U)
#define ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U)
#define ltc_ltc1_ltss_tstg_cmgmt1_r() (0x001422a4U)
#define ltc_ltc1_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U)
#define ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f() (0x1U)
#define ltc_ltc0_lts0_tstg_info_1_r() (0x0014058cU)
#define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r) (((r) >> 0U) & 0xffffU)
#define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r) (((r) >> 16U) & 0x1fU)
#endif

247
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_mc_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,196 +59,57 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 mc_boot_0_r(void)
{
return 0x00000000U;
}
static inline u32 mc_boot_0_architecture_v(u32 r)
{
return (r >> 24U) & 0x1fU;
}
static inline u32 mc_boot_0_implementation_v(u32 r)
{
return (r >> 20U) & 0xfU;
}
static inline u32 mc_boot_0_major_revision_v(u32 r)
{
return (r >> 4U) & 0xfU;
}
static inline u32 mc_boot_0_minor_revision_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 mc_intr_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 mc_intr_pfifo_pending_f(void)
{
return 0x100U;
}
static inline u32 mc_intr_replayable_fault_pending_f(void)
{
return 0x200U;
}
static inline u32 mc_intr_pgraph_pending_f(void)
{
return 0x1000U;
}
static inline u32 mc_intr_pmu_pending_f(void)
{
return 0x1000000U;
}
static inline u32 mc_intr_ltc_pending_f(void)
{
return 0x2000000U;
}
static inline u32 mc_intr_priv_ring_pending_f(void)
{
return 0x40000000U;
}
static inline u32 mc_intr_pbus_pending_f(void)
{
return 0x10000000U;
}
static inline u32 mc_intr_en_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 mc_intr_en_set_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 mc_intr_en_clear_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 mc_enable_r(void)
{
return 0x00000200U;
}
static inline u32 mc_enable_xbar_enabled_f(void)
{
return 0x4U;
}
static inline u32 mc_enable_l2_enabled_f(void)
{
return 0x8U;
}
static inline u32 mc_enable_pmedia_s(void)
{
return 1U;
}
static inline u32 mc_enable_pmedia_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 mc_enable_pmedia_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 mc_enable_pmedia_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 mc_enable_priv_ring_enabled_f(void)
{
return 0x20U;
}
static inline u32 mc_enable_ce0_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 mc_enable_pfifo_enabled_f(void)
{
return 0x100U;
}
static inline u32 mc_enable_pgraph_enabled_f(void)
{
return 0x1000U;
}
static inline u32 mc_enable_pwr_v(u32 r)
{
return (r >> 13U) & 0x1U;
}
static inline u32 mc_enable_pwr_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 mc_enable_pwr_enabled_f(void)
{
return 0x2000U;
}
static inline u32 mc_enable_pfb_enabled_f(void)
{
return 0x100000U;
}
static inline u32 mc_enable_ce2_m(void)
{
return U32(0x1U) << 21U;
}
static inline u32 mc_enable_ce2_enabled_f(void)
{
return 0x200000U;
}
static inline u32 mc_enable_blg_enabled_f(void)
{
return 0x8000000U;
}
static inline u32 mc_enable_perfmon_enabled_f(void)
{
return 0x10000000U;
}
static inline u32 mc_enable_hub_enabled_f(void)
{
return 0x20000000U;
}
static inline u32 mc_intr_ltc_r(void)
{
return 0x000001c0U;
}
static inline u32 mc_enable_pb_r(void)
{
return 0x00000204U;
}
static inline u32 mc_enable_pb_0_s(void)
{
return 1U;
}
static inline u32 mc_enable_pb_0_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 mc_enable_pb_0_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 mc_enable_pb_0_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 mc_enable_pb_0_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 mc_elpg_enable_r(void)
{
return 0x0000020cU;
}
static inline u32 mc_elpg_enable_xbar_enabled_f(void)
{
return 0x4U;
}
static inline u32 mc_elpg_enable_pfb_enabled_f(void)
{
return 0x100000U;
}
static inline u32 mc_elpg_enable_hub_enabled_f(void)
{
return 0x20000000U;
}
#define mc_boot_0_r() (0x00000000U)
#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU)
#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU)
#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU)
#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU)
#define mc_intr_r(i)\
(nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32((i), 4U)))
#define mc_intr_pfifo_pending_f() (0x100U)
#define mc_intr_replayable_fault_pending_f() (0x200U)
#define mc_intr_pgraph_pending_f() (0x1000U)
#define mc_intr_pmu_pending_f() (0x1000000U)
#define mc_intr_ltc_pending_f() (0x2000000U)
#define mc_intr_priv_ring_pending_f() (0x40000000U)
#define mc_intr_pbus_pending_f() (0x10000000U)
#define mc_intr_en_r(i)\
(nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32((i), 4U)))
#define mc_intr_en_set_r(i)\
(nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32((i), 4U)))
#define mc_intr_en_clear_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U)))
#define mc_enable_r() (0x00000200U)
#define mc_enable_xbar_enabled_f() (0x4U)
#define mc_enable_l2_enabled_f() (0x8U)
#define mc_enable_pmedia_s() (1U)
#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U)
#define mc_enable_pmedia_m() (U32(0x1U) << 4U)
#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U)
#define mc_enable_priv_ring_enabled_f() (0x20U)
#define mc_enable_ce0_m() (U32(0x1U) << 6U)
#define mc_enable_pfifo_enabled_f() (0x100U)
#define mc_enable_pgraph_enabled_f() (0x1000U)
#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U)
#define mc_enable_pwr_disabled_v() (0x00000000U)
#define mc_enable_pwr_enabled_f() (0x2000U)
#define mc_enable_pfb_enabled_f() (0x100000U)
#define mc_enable_ce2_m() (U32(0x1U) << 21U)
#define mc_enable_ce2_enabled_f() (0x200000U)
#define mc_enable_blg_enabled_f() (0x8000000U)
#define mc_enable_perfmon_enabled_f() (0x10000000U)
#define mc_enable_hub_enabled_f() (0x20000000U)
#define mc_intr_ltc_r() (0x000001c0U)
#define mc_enable_pb_r() (0x00000204U)
#define mc_enable_pb_0_s() (1U)
#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U)
#define mc_enable_pb_0_m() (U32(0x1U) << 0U)
#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U)
#define mc_enable_pb_0_enabled_v() (0x00000001U)
#define mc_enable_pb_sel_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define mc_elpg_enable_r() (0x0000020cU)
#define mc_elpg_enable_xbar_enabled_f() (0x4U)
#define mc_elpg_enable_pfb_enabled_f() (0x100000U)
#define mc_elpg_enable_hub_enabled_f() (0x20000000U)
#endif

635
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,480 +59,161 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pbdma_gp_entry1_r(void)
{
return 0x10000004U;
}
static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 pbdma_gp_entry1_length_f(u32 v)
{
return (v & 0x1fffffU) << 10U;
}
static inline u32 pbdma_gp_entry1_length_v(u32 r)
{
return (r >> 10U) & 0x1fffffU;
}
static inline u32 pbdma_gp_base_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_base__size_1_v(void)
{
return 0x00000004U;
}
static inline u32 pbdma_gp_base_offset_f(u32 v)
{
return (v & 0x1fffffffU) << 3U;
}
static inline u32 pbdma_gp_base_rsvd_s(void)
{
return 3U;
}
static inline u32 pbdma_gp_base_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
{
return (v & 0x1fU) << 16U;
}
static inline u32 pbdma_gp_fetch_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_get_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_put_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_pb_fetch_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_pb_fetch_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_get_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_get_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_put_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_put_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_formats_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_formats_gp_fermi0_f(void)
{
return 0x0U;
}
static inline u32 pbdma_formats_pb_fermi1_f(void)
{
return 0x100U;
}
static inline u32 pbdma_formats_mp_fermi0_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_pb_header_priv_user_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_method_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_subchannel_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_level_main_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_first_true_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_pb_header_type_inc_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_pb_header_type_non_inc_f(void)
{
return 0x60000000U;
}
static inline u32 pbdma_hdr_shadow_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_shadow_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_shadow_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_subdevice_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_subdevice_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 pbdma_subdevice_status_active_f(void)
{
return 0x10000000U;
}
static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_method0_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method0_fifo_size_v(void)
{
return 0x00000004U;
}
static inline u32 pbdma_method0_addr_f(u32 v)
{
return (v & 0xfffU) << 2U;
}
static inline u32 pbdma_method0_addr_v(u32 r)
{
return (r >> 2U) & 0xfffU;
}
static inline u32 pbdma_method0_subch_v(u32 r)
{
return (r >> 16U) & 0x7U;
}
static inline u32 pbdma_method0_first_true_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_method0_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_method1_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method2_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method3_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_data0_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_target_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_target_engine_sw_f(void)
{
return 0x1fU;
}
static inline u32 pbdma_acquire_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_acquire_retry_man_2_f(void)
{
return 0x2U;
}
static inline u32 pbdma_acquire_retry_exp_2_f(void)
{
return 0x100U;
}
static inline u32 pbdma_acquire_timeout_exp_max_f(void)
{
return 0x7800U;
}
static inline u32 pbdma_acquire_timeout_man_max_f(void)
{
return 0x7fff8000U;
}
static inline u32 pbdma_acquire_timeout_en_disable_f(void)
{
return 0x0U;
}
static inline u32 pbdma_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_channel_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_signature_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_signature_hw_valid_f(void)
{
return 0xfaceU;
}
static inline u32 pbdma_signature_sw_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_userd_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_userd_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 pbdma_userd_addr_f(u32 v)
{
return (v & 0x7fffffU) << 9U;
}
static inline u32 pbdma_userd_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_userd_hi_addr_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 pbdma_config_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_config_auth_level_privileged_f(void)
{
return 0x100U;
}
static inline u32 pbdma_hce_ctrl_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
{
return 0x20U;
}
static inline u32 pbdma_intr_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_0_memreq_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pbdma_intr_0_memreq_pending_f(void)
{
return 0x1U;
}
static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
{
return 0x2U;
}
static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
{
return 0x4U;
}
static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
{
return 0x8U;
}
static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
{
return 0x10U;
}
static inline u32 pbdma_intr_0_memflush_pending_f(void)
{
return 0x20U;
}
static inline u32 pbdma_intr_0_memop_pending_f(void)
{
return 0x40U;
}
static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
{
return 0x80U;
}
static inline u32 pbdma_intr_0_lbreq_pending_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
{
return 0x200U;
}
static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
{
return 0x400U;
}
static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
{
return 0x800U;
}
static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
{
return 0x1000U;
}
static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
{
return 0x2000U;
}
static inline u32 pbdma_intr_0_gpptr_pending_f(void)
{
return 0x4000U;
}
static inline u32 pbdma_intr_0_gpentry_pending_f(void)
{
return 0x8000U;
}
static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
{
return 0x10000U;
}
static inline u32 pbdma_intr_0_pbptr_pending_f(void)
{
return 0x20000U;
}
static inline u32 pbdma_intr_0_pbentry_pending_f(void)
{
return 0x40000U;
}
static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
{
return 0x80000U;
}
static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
{
return 0x100000U;
}
static inline u32 pbdma_intr_0_method_pending_f(void)
{
return 0x200000U;
}
static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_intr_0_device_pending_f(void)
{
return 0x800000U;
}
static inline u32 pbdma_intr_0_semaphore_pending_f(void)
{
return 0x2000000U;
}
static inline u32 pbdma_intr_0_acquire_pending_f(void)
{
return 0x4000000U;
}
static inline u32 pbdma_intr_0_pri_pending_f(void)
{
return 0x8000000U;
}
static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_intr_0_pbseg_pending_f(void)
{
return 0x40000000U;
}
static inline u32 pbdma_intr_0_signature_pending_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_intr_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_en_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_en_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_stall_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
{
return 0x1U;
}
static inline u32 pbdma_udma_nop_r(void)
{
return 0x00000008U;
}
static inline u32 pbdma_runlist_timeslice_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
{
return 0x80U;
}
static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
{
return 0x3000U;
}
static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
{
return 0x10000000U;
}
#define pbdma_gp_entry1_r() (0x10000004U)
#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU)
#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U)
#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU)
#define pbdma_gp_base_r(i)\
(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base__size_1_v() (0x00000004U)
#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U)
#define pbdma_gp_base_rsvd_s() (3U)
#define pbdma_gp_base_hi_r(i)\
(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U)
#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U)
#define pbdma_gp_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_get_r(i)\
(nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_put_r(i)\
(nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_pb_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_pb_fetch_hi_r(i)\
(nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_get_r(i)\
(nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_get_hi_r(i)\
(nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_put_r(i)\
(nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_put_hi_r(i)\
(nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_formats_r(i)\
(nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_formats_gp_fermi0_f() (0x0U)
#define pbdma_formats_pb_fermi1_f() (0x100U)
#define pbdma_formats_mp_fermi0_f() (0x0U)
#define pbdma_pb_header_r(i)\
(nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_pb_header_priv_user_f() (0x0U)
#define pbdma_pb_header_method_zero_f() (0x0U)
#define pbdma_pb_header_subchannel_zero_f() (0x0U)
#define pbdma_pb_header_level_main_f() (0x0U)
#define pbdma_pb_header_first_true_f() (0x400000U)
#define pbdma_pb_header_type_inc_f() (0x20000000U)
#define pbdma_pb_header_type_non_inc_f() (0x60000000U)
#define pbdma_hdr_shadow_r(i)\
(nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_shadow_0_r(i)\
(nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_shadow_1_r(i)\
(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_r(i)\
(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U)
#define pbdma_subdevice_status_active_f() (0x10000000U)
#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U)
#define pbdma_method0_r(i)\
(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method0_fifo_size_v() (0x00000004U)
#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U)
#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU)
#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U)
#define pbdma_method0_first_true_f() (0x400000U)
#define pbdma_method0_valid_true_f() (0x80000000U)
#define pbdma_method1_r(i)\
(nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method2_r(i)\
(nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method3_r(i)\
(nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_data0_r(i)\
(nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_target_r(i)\
(nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_target_engine_sw_f() (0x1fU)
#define pbdma_acquire_r(i)\
(nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_acquire_retry_man_2_f() (0x2U)
#define pbdma_acquire_retry_exp_2_f() (0x100U)
#define pbdma_acquire_timeout_exp_max_f() (0x7800U)
#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U)
#define pbdma_acquire_timeout_en_disable_f() (0x0U)
#define pbdma_status_r(i)\
(nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_channel_r(i)\
(nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_signature_r(i)\
(nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_signature_hw_valid_f() (0xfaceU)
#define pbdma_signature_sw_zero_f() (0x0U)
#define pbdma_userd_r(i)\
(nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_target_vid_mem_f() (0x0U)
#define pbdma_userd_target_sys_mem_coh_f() (0x2U)
#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U)
#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U)
#define pbdma_userd_hi_r(i)\
(nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U)
#define pbdma_config_r(i)\
(nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_config_auth_level_privileged_f() (0x100U)
#define pbdma_hce_ctrl_r(i)\
(nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U)
#define pbdma_intr_0_r(i)\
(nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U)
#define pbdma_intr_0_memreq_pending_f() (0x1U)
#define pbdma_intr_0_memack_timeout_pending_f() (0x2U)
#define pbdma_intr_0_memack_extra_pending_f() (0x4U)
#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U)
#define pbdma_intr_0_memdat_extra_pending_f() (0x10U)
#define pbdma_intr_0_memflush_pending_f() (0x20U)
#define pbdma_intr_0_memop_pending_f() (0x40U)
#define pbdma_intr_0_lbconnect_pending_f() (0x80U)
#define pbdma_intr_0_lbreq_pending_f() (0x100U)
#define pbdma_intr_0_lback_timeout_pending_f() (0x200U)
#define pbdma_intr_0_lback_extra_pending_f() (0x400U)
#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U)
#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U)
#define pbdma_intr_0_gpfifo_pending_f() (0x2000U)
#define pbdma_intr_0_gpptr_pending_f() (0x4000U)
#define pbdma_intr_0_gpentry_pending_f() (0x8000U)
#define pbdma_intr_0_gpcrc_pending_f() (0x10000U)
#define pbdma_intr_0_pbptr_pending_f() (0x20000U)
#define pbdma_intr_0_pbentry_pending_f() (0x40000U)
#define pbdma_intr_0_pbcrc_pending_f() (0x80000U)
#define pbdma_intr_0_xbarconnect_pending_f() (0x100000U)
#define pbdma_intr_0_method_pending_f() (0x200000U)
#define pbdma_intr_0_methodcrc_pending_f() (0x400000U)
#define pbdma_intr_0_device_pending_f() (0x800000U)
#define pbdma_intr_0_semaphore_pending_f() (0x2000000U)
#define pbdma_intr_0_acquire_pending_f() (0x4000000U)
#define pbdma_intr_0_pri_pending_f() (0x8000000U)
#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U)
#define pbdma_intr_0_pbseg_pending_f() (0x40000000U)
#define pbdma_intr_0_signature_pending_f() (0x80000000U)
#define pbdma_intr_1_r(i)\
(nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_en_0_r(i)\
(nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_en_0_lbreq_enabled_f() (0x100U)
#define pbdma_intr_en_1_r(i)\
(nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_r(i)\
(nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_lbreq_enabled_f() (0x100U)
#define pbdma_intr_stall_1_r(i)\
(nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U)
#define pbdma_udma_nop_r() (0x00000008U)
#define pbdma_runlist_timeslice_r(i)\
(nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_runlist_timeslice_timeout_128_f() (0x80U)
#define pbdma_runlist_timeslice_timescale_3_f() (0x3000U)
#define pbdma_runlist_timeslice_enable_true_f() (0x10000000U)
#endif

202
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,164 +59,44 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 perf_pmmsys_base_v(void)
{
return 0x001b0000U;
}
static inline u32 perf_pmmsys_extent_v(void)
{
return 0x001b0fffU;
}
static inline u32 perf_pmasys_control_r(void)
{
return 0x001b4000U;
}
static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
{
return 0x10U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
{
return (r >> 5U) & 0x1U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
{
return 0x20U;
}
static inline u32 perf_pmasys_mem_block_r(void)
{
return 0x001b4070U;
}
static inline u32 perf_pmasys_mem_block_base_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 perf_pmasys_mem_block_target_f(u32 v)
{
return (v & 0x3U) << 28U;
}
static inline u32 perf_pmasys_mem_block_target_v(u32 r)
{
return (r >> 28U) & 0x3U;
}
static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
{
return 0x00000000U;
}
static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
{
return 0x0U;
}
static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
{
return 0x00000002U;
}
static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
{
return 0x20000000U;
}
static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
{
return 0x00000003U;
}
static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 perf_pmasys_mem_block_valid_true_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_mem_block_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 perf_pmasys_mem_block_valid_false_v(void)
{
return 0x00000000U;
}
static inline u32 perf_pmasys_mem_block_valid_false_f(void)
{
return 0x0U;
}
static inline u32 perf_pmasys_outbase_r(void)
{
return 0x001b4074U;
}
static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
{
return (v & 0x7ffffffU) << 5U;
}
static inline u32 perf_pmasys_outbaseupper_r(void)
{
return 0x001b4078U;
}
static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 perf_pmasys_outsize_r(void)
{
return 0x001b407cU;
}
static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
{
return (v & 0x7ffffffU) << 5U;
}
static inline u32 perf_pmasys_mem_bytes_r(void)
{
return 0x001b4084U;
}
static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 perf_pmasys_mem_bump_r(void)
{
return 0x001b4088U;
}
static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 perf_pmasys_enginestatus_r(void)
{
return 0x001b40a4U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
{
return 0x10U;
}
#define perf_pmmsys_base_v() (0x001b0000U)
#define perf_pmmsys_extent_v() (0x001b0fffU)
#define perf_pmasys_control_r() (0x001b4000U)
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)
#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U)
#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U)
#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U)
#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U)
#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U)
#define perf_pmasys_mem_block_r() (0x001b4070U)
#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U)
#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U)
#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U)
#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U)
#define perf_pmasys_mem_block_target_lfb_f() (0x0U)
#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U)
#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U)
#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U)
#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U)
#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U)
#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U)
#define perf_pmasys_mem_block_valid_true_v() (0x00000001U)
#define perf_pmasys_mem_block_valid_true_f() (0x80000000U)
#define perf_pmasys_mem_block_valid_false_v() (0x00000000U)
#define perf_pmasys_mem_block_valid_false_f() (0x0U)
#define perf_pmasys_outbase_r() (0x001b4074U)
#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U)
#define perf_pmasys_outbaseupper_r() (0x001b4078U)
#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U)
#define perf_pmasys_outsize_r() (0x001b407cU)
#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U)
#define perf_pmasys_mem_bytes_r() (0x001b4084U)
#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U)
#define perf_pmasys_mem_bump_r() (0x001b4088U)
#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U)
#define perf_pmasys_enginestatus_r() (0x001b40a4U)
#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U)
#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U)
#endif

12
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pnvdec_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,12 +59,6 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pnvdec_falcon_irqsset_r(void)
{
return 0x00084000U;
}
static inline u32 pnvdec_falcon_irqsclr_r(void)
{
return 0x00084004U;
}
#define pnvdec_falcon_irqsset_r() (0x00084000U)
#define pnvdec_falcon_irqsclr_r() (0x00084004U)
#endif

8
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,8 +59,6 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pram_data032_r(u32 i)
{
return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U));
}
#define pram_data032_r(i)\
(nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U)))
#endif

117
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,96 +59,27 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringmaster_command_r(void)
{
return 0x0012004cU;
}
static inline u32 pri_ringmaster_command_cmd_m(void)
{
return U32(0x3fU) << 0U;
}
static inline u32 pri_ringmaster_command_cmd_v(u32 r)
{
return (r >> 0U) & 0x3fU;
}
static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
{
return 0x00000000U;
}
static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
{
return 0x1U;
}
static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
{
return 0x2U;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
{
return 0x3U;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
{
return 0x0U;
}
static inline u32 pri_ringmaster_command_data_r(void)
{
return 0x00120048U;
}
static inline u32 pri_ringmaster_start_results_r(void)
{
return 0x00120050U;
}
static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
{
return 0x00000001U;
}
static inline u32 pri_ringmaster_intr_status0_r(void)
{
return 0x00120058U;
}
static inline u32 pri_ringmaster_intr_status1_r(void)
{
return 0x0012005cU;
}
static inline u32 pri_ringmaster_global_ctl_r(void)
{
return 0x00120060U;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
{
return 0x1U;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
{
return 0x0U;
}
static inline u32 pri_ringmaster_enum_fbp_r(void)
{
return 0x00120074U;
}
static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 pri_ringmaster_enum_gpc_r(void)
{
return 0x00120078U;
}
static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 pri_ringmaster_enum_ltc_r(void)
{
return 0x0012006cU;
}
static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
#define pri_ringmaster_command_r() (0x0012004cU)
#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U)
#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU)
#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U)
#define pri_ringmaster_command_cmd_start_ring_f() (0x1U)
#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U)
#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U)
#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U)
#define pri_ringmaster_command_data_r() (0x00120048U)
#define pri_ringmaster_start_results_r() (0x00120050U)
#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U)
#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U)
#define pri_ringmaster_intr_status0_r() (0x00120058U)
#define pri_ringmaster_intr_status1_r() (0x0012005cU)
#define pri_ringmaster_global_ctl_r() (0x00120060U)
#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U)
#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U)
#define pri_ringmaster_enum_fbp_r() (0x00120074U)
#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU)
#define pri_ringmaster_enum_gpc_r() (0x00120078U)
#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU)
#define pri_ringmaster_enum_ltc_r() (0x0012006cU)
#define pri_ringmaster_enum_ltc_count_v(r) (((r) >> 0U) & 0x1fU)
#endif

28
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,24 +59,10 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
{
return nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
{
return 0x00128120U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
{
return 0x00128124U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
{
return 0x00128128U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
{
return 0x0012812cU;
}
#define pri_ringstation_gpc_master_config_r(i)\
(nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32((i), 4U)))
#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U)
#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U)
#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U)
#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU)
#endif

44
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,36 +59,14 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringstation_sys_master_config_r(u32 i)
{
return nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 pri_ringstation_sys_decode_config_r(void)
{
return 0x00122204U;
}
static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
{
return U32(0x7U) << 0U;
}
static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
{
return 0x1U;
}
static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
{
return 0x00122120U;
}
static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
{
return 0x00122124U;
}
static inline u32 pri_ringstation_sys_priv_error_info_r(void)
{
return 0x00122128U;
}
static inline u32 pri_ringstation_sys_priv_error_code_r(void)
{
return 0x0012212cU;
}
#define pri_ringstation_sys_master_config_r(i)\
(nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32((i), 4U)))
#define pri_ringstation_sys_decode_config_r() (0x00122204U)
#define pri_ringstation_sys_decode_config_ring_m() (U32(0x7U) << 0U)
#define pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()\
(0x1U)
#define pri_ringstation_sys_priv_error_adr_r() (0x00122120U)
#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U)
#define pri_ringstation_sys_priv_error_info_r() (0x00122128U)
#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU)
#endif

152
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_proj_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,124 +59,34 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 proj_gpc_base_v(void)
{
return 0x00500000U;
}
static inline u32 proj_gpc_shared_base_v(void)
{
return 0x00418000U;
}
static inline u32 proj_gpc_stride_v(void)
{
return 0x00008000U;
}
static inline u32 proj_gpc_priv_stride_v(void)
{
return 0x00000800U;
}
static inline u32 proj_ltc_stride_v(void)
{
return 0x00002000U;
}
static inline u32 proj_lts_stride_v(void)
{
return 0x00000200U;
}
static inline u32 proj_fbpa_base_v(void)
{
return 0x00900000U;
}
static inline u32 proj_fbpa_shared_base_v(void)
{
return 0x009a0000U;
}
static inline u32 proj_fbpa_stride_v(void)
{
return 0x00004000U;
}
static inline u32 proj_ppc_in_gpc_base_v(void)
{
return 0x00003000U;
}
static inline u32 proj_ppc_in_gpc_shared_base_v(void)
{
return 0x00003e00U;
}
static inline u32 proj_ppc_in_gpc_stride_v(void)
{
return 0x00000200U;
}
static inline u32 proj_rop_base_v(void)
{
return 0x00410000U;
}
static inline u32 proj_rop_shared_base_v(void)
{
return 0x00408800U;
}
static inline u32 proj_rop_stride_v(void)
{
return 0x00000400U;
}
static inline u32 proj_tpc_in_gpc_base_v(void)
{
return 0x00004000U;
}
static inline u32 proj_tpc_in_gpc_stride_v(void)
{
return 0x00000800U;
}
static inline u32 proj_tpc_in_gpc_shared_base_v(void)
{
return 0x00001800U;
}
static inline u32 proj_host_num_engines_v(void)
{
return 0x00000009U;
}
static inline u32 proj_host_num_pbdma_v(void)
{
return 0x00000004U;
}
static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
{
return 0x00000005U;
}
static inline u32 proj_scal_litter_num_sm_per_tpc_v(void)
{
return 0x00000001U;
}
static inline u32 proj_scal_litter_num_fbps_v(void)
{
return 0x00000006U;
}
static inline u32 proj_scal_litter_num_fbpas_v(void)
{
return 0x00000006U;
}
static inline u32 proj_scal_litter_num_gpcs_v(void)
{
return 0x00000006U;
}
static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
{
return 0x00000003U;
}
static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
{
return 0x00000002U;
}
static inline u32 proj_scal_litter_num_zcull_banks_v(void)
{
return 0x00000004U;
}
static inline u32 proj_scal_max_gpcs_v(void)
{
return 0x00000020U;
}
static inline u32 proj_scal_max_tpc_per_gpc_v(void)
{
return 0x00000008U;
}
#define proj_gpc_base_v() (0x00500000U)
#define proj_gpc_shared_base_v() (0x00418000U)
#define proj_gpc_stride_v() (0x00008000U)
#define proj_gpc_priv_stride_v() (0x00000800U)
#define proj_ltc_stride_v() (0x00002000U)
#define proj_lts_stride_v() (0x00000200U)
#define proj_fbpa_base_v() (0x00900000U)
#define proj_fbpa_shared_base_v() (0x009a0000U)
#define proj_fbpa_stride_v() (0x00004000U)
#define proj_ppc_in_gpc_base_v() (0x00003000U)
#define proj_ppc_in_gpc_shared_base_v() (0x00003e00U)
#define proj_ppc_in_gpc_stride_v() (0x00000200U)
#define proj_rop_base_v() (0x00410000U)
#define proj_rop_shared_base_v() (0x00408800U)
#define proj_rop_stride_v() (0x00000400U)
#define proj_tpc_in_gpc_base_v() (0x00004000U)
#define proj_tpc_in_gpc_stride_v() (0x00000800U)
#define proj_tpc_in_gpc_shared_base_v() (0x00001800U)
#define proj_host_num_engines_v() (0x00000009U)
#define proj_host_num_pbdma_v() (0x00000004U)
#define proj_scal_litter_num_tpc_per_gpc_v() (0x00000005U)
#define proj_scal_litter_num_sm_per_tpc_v() (0x00000001U)
#define proj_scal_litter_num_fbps_v() (0x00000006U)
#define proj_scal_litter_num_fbpas_v() (0x00000006U)
#define proj_scal_litter_num_gpcs_v() (0x00000006U)
#define proj_scal_litter_num_pes_per_gpc_v() (0x00000003U)
#define proj_scal_litter_num_tpcs_per_pes_v() (0x00000002U)
#define proj_scal_litter_num_zcull_banks_v() (0x00000004U)
#define proj_scal_max_gpcs_v() (0x00000020U)
#define proj_scal_max_tpc_per_gpc_v() (0x00000008U)
#endif

703
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_psec_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,560 +59,149 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 psec_falcon_irqsset_r(void)
{
return 0x00087000U;
}
static inline u32 psec_falcon_irqsset_swgen0_set_f(void)
{
return 0x40U;
}
static inline u32 psec_falcon_irqsclr_r(void)
{
return 0x00087004U;
}
static inline u32 psec_falcon_irqstat_r(void)
{
return 0x00087008U;
}
static inline u32 psec_falcon_irqstat_halt_true_f(void)
{
return 0x10U;
}
static inline u32 psec_falcon_irqstat_exterr_true_f(void)
{
return 0x20U;
}
static inline u32 psec_falcon_irqstat_swgen0_true_f(void)
{
return 0x40U;
}
static inline u32 psec_falcon_irqmode_r(void)
{
return 0x0008700cU;
}
static inline u32 psec_falcon_irqmset_r(void)
{
return 0x00087010U;
}
static inline u32 psec_falcon_irqmset_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 psec_falcon_irqmset_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 psec_falcon_irqmset_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 psec_falcon_irqmset_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 psec_falcon_irqmset_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 psec_falcon_irqmset_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 psec_falcon_irqmset_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 psec_falcon_irqmset_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 psec_falcon_irqmclr_r(void)
{
return 0x00087014U;
}
static inline u32 psec_falcon_irqmclr_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 psec_falcon_irqmclr_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 psec_falcon_irqmclr_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 psec_falcon_irqmclr_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 psec_falcon_irqmclr_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 psec_falcon_irqmclr_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 psec_falcon_irqmclr_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 psec_falcon_irqmclr_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 psec_falcon_irqmclr_ext_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 psec_falcon_irqmask_r(void)
{
return 0x00087018U;
}
static inline u32 psec_falcon_irqdest_r(void)
{
return 0x0008701cU;
}
static inline u32 psec_falcon_irqdest_host_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 psec_falcon_irqdest_host_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 psec_falcon_irqdest_host_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 psec_falcon_irqdest_host_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 psec_falcon_irqdest_host_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 psec_falcon_irqdest_host_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 psec_falcon_irqdest_host_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 psec_falcon_irqdest_host_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 psec_falcon_irqdest_host_ext_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 psec_falcon_irqdest_target_gptmr_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 psec_falcon_irqdest_target_wdtmr_f(u32 v)
{
return (v & 0x1U) << 17U;
}
static inline u32 psec_falcon_irqdest_target_mthd_f(u32 v)
{
return (v & 0x1U) << 18U;
}
static inline u32 psec_falcon_irqdest_target_ctxsw_f(u32 v)
{
return (v & 0x1U) << 19U;
}
static inline u32 psec_falcon_irqdest_target_halt_f(u32 v)
{
return (v & 0x1U) << 20U;
}
static inline u32 psec_falcon_irqdest_target_exterr_f(u32 v)
{
return (v & 0x1U) << 21U;
}
static inline u32 psec_falcon_irqdest_target_swgen0_f(u32 v)
{
return (v & 0x1U) << 22U;
}
static inline u32 psec_falcon_irqdest_target_swgen1_f(u32 v)
{
return (v & 0x1U) << 23U;
}
static inline u32 psec_falcon_irqdest_target_ext_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 psec_falcon_curctx_r(void)
{
return 0x00087050U;
}
static inline u32 psec_falcon_nxtctx_r(void)
{
return 0x00087054U;
}
static inline u32 psec_falcon_mailbox0_r(void)
{
return 0x00087040U;
}
static inline u32 psec_falcon_mailbox1_r(void)
{
return 0x00087044U;
}
static inline u32 psec_falcon_itfen_r(void)
{
return 0x00087048U;
}
static inline u32 psec_falcon_itfen_ctxen_enable_f(void)
{
return 0x1U;
}
static inline u32 psec_falcon_idlestate_r(void)
{
return 0x0008704cU;
}
static inline u32 psec_falcon_idlestate_falcon_busy_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 psec_falcon_idlestate_ext_busy_v(u32 r)
{
return (r >> 1U) & 0x7fffU;
}
static inline u32 psec_falcon_os_r(void)
{
return 0x00087080U;
}
static inline u32 psec_falcon_engctl_r(void)
{
return 0x000870a4U;
}
static inline u32 psec_falcon_cpuctl_r(void)
{
return 0x00087100U;
}
static inline u32 psec_falcon_cpuctl_startcpu_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 psec_falcon_cpuctl_halt_intr_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 psec_falcon_cpuctl_halt_intr_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 psec_falcon_cpuctl_halt_intr_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
{
return (r >> 6U) & 0x1U;
}
static inline u32 psec_falcon_cpuctl_alias_r(void)
{
return 0x00087130U;
}
static inline u32 psec_falcon_cpuctl_alias_startcpu_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 psec_falcon_imemc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00087180U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 psec_falcon_imemc_offs_f(u32 v)
{
return (v & 0x3fU) << 2U;
}
static inline u32 psec_falcon_imemc_blk_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 psec_falcon_imemc_aincw_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 psec_falcon_imemd_r(u32 i)
{
return nvgpu_safe_add_u32(0x00087184U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 psec_falcon_imemt_r(u32 i)
{
return nvgpu_safe_add_u32(0x00087188U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 psec_falcon_sctl_r(void)
{
return 0x00087240U;
}
static inline u32 psec_falcon_mmu_phys_sec_r(void)
{
return 0x00100ce4U;
}
static inline u32 psec_falcon_bootvec_r(void)
{
return 0x00087104U;
}
static inline u32 psec_falcon_bootvec_vec_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 psec_falcon_dmactl_r(void)
{
return 0x0008710cU;
}
static inline u32 psec_falcon_dmactl_dmem_scrubbing_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 psec_falcon_dmactl_imem_scrubbing_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 psec_falcon_dmactl_require_ctx_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 psec_falcon_hwcfg_r(void)
{
return 0x00087108U;
}
static inline u32 psec_falcon_hwcfg_imem_size_v(u32 r)
{
return (r >> 0U) & 0x1ffU;
}
static inline u32 psec_falcon_hwcfg_dmem_size_v(u32 r)
{
return (r >> 9U) & 0x1ffU;
}
static inline u32 psec_falcon_dmatrfbase_r(void)
{
return 0x00087110U;
}
static inline u32 psec_falcon_dmatrfbase1_r(void)
{
return 0x00087128U;
}
static inline u32 psec_falcon_dmatrfmoffs_r(void)
{
return 0x00087114U;
}
static inline u32 psec_falcon_dmatrfcmd_r(void)
{
return 0x00087118U;
}
static inline u32 psec_falcon_dmatrfcmd_imem_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 psec_falcon_dmatrfcmd_write_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 psec_falcon_dmatrfcmd_size_f(u32 v)
{
return (v & 0x7U) << 8U;
}
static inline u32 psec_falcon_dmatrfcmd_ctxdma_f(u32 v)
{
return (v & 0x7U) << 12U;
}
static inline u32 psec_falcon_dmatrffboffs_r(void)
{
return 0x0008711cU;
}
static inline u32 psec_falcon_exterraddr_r(void)
{
return 0x00087168U;
}
static inline u32 psec_falcon_exterrstat_r(void)
{
return 0x0008716cU;
}
static inline u32 psec_falcon_exterrstat_valid_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 psec_falcon_exterrstat_valid_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 psec_falcon_exterrstat_valid_true_v(void)
{
return 0x00000001U;
}
static inline u32 psec_sec2_falcon_icd_cmd_r(void)
{
return 0x00087200U;
}
static inline u32 psec_sec2_falcon_icd_cmd_opc_s(void)
{
return 4U;
}
static inline u32 psec_sec2_falcon_icd_cmd_opc_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 psec_sec2_falcon_icd_cmd_opc_m(void)
{
return U32(0xfU) << 0U;
}
static inline u32 psec_sec2_falcon_icd_cmd_opc_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 psec_sec2_falcon_icd_cmd_opc_rreg_f(void)
{
return 0x8U;
}
static inline u32 psec_sec2_falcon_icd_cmd_opc_rstat_f(void)
{
return 0xeU;
}
static inline u32 psec_sec2_falcon_icd_cmd_idx_f(u32 v)
{
return (v & 0x1fU) << 8U;
}
static inline u32 psec_sec2_falcon_icd_rdata_r(void)
{
return 0x0008720cU;
}
static inline u32 psec_falcon_dmemc_r(u32 i)
{
return nvgpu_safe_add_u32(0x000871c0U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 psec_falcon_dmemc_offs_f(u32 v)
{
return (v & 0x3fU) << 2U;
}
static inline u32 psec_falcon_dmemc_offs_m(void)
{
return U32(0x3fU) << 2U;
}
static inline u32 psec_falcon_dmemc_blk_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 psec_falcon_dmemc_blk_m(void)
{
return U32(0xffU) << 8U;
}
static inline u32 psec_falcon_dmemc_aincw_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 psec_falcon_dmemc_aincr_f(u32 v)
{
return (v & 0x1U) << 25U;
}
static inline u32 psec_falcon_dmemd_r(u32 i)
{
return nvgpu_safe_add_u32(0x000871c4U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 psec_falcon_debug1_r(void)
{
return 0x00087090U;
}
static inline u32 psec_falcon_debug1_ctxsw_mode_s(void)
{
return 1U;
}
static inline u32 psec_falcon_debug1_ctxsw_mode_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 psec_falcon_debug1_ctxsw_mode_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 psec_falcon_debug1_ctxsw_mode_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 psec_falcon_debug1_ctxsw_mode_init_f(void)
{
return 0x0U;
}
static inline u32 psec_fbif_transcfg_r(u32 i)
{
return nvgpu_safe_add_u32(0x00087600U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 psec_fbif_transcfg_target_local_fb_f(void)
{
return 0x0U;
}
static inline u32 psec_fbif_transcfg_target_coherent_sysmem_f(void)
{
return 0x1U;
}
static inline u32 psec_fbif_transcfg_target_noncoherent_sysmem_f(void)
{
return 0x2U;
}
static inline u32 psec_fbif_transcfg_mem_type_s(void)
{
return 1U;
}
static inline u32 psec_fbif_transcfg_mem_type_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 psec_fbif_transcfg_mem_type_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 psec_fbif_transcfg_mem_type_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 psec_fbif_transcfg_mem_type_virtual_f(void)
{
return 0x0U;
}
static inline u32 psec_fbif_transcfg_mem_type_physical_f(void)
{
return 0x4U;
}
static inline u32 psec_falcon_engine_r(void)
{
return 0x000873c0U;
}
static inline u32 psec_falcon_engine_reset_true_f(void)
{
return 0x1U;
}
static inline u32 psec_falcon_engine_reset_false_f(void)
{
return 0x0U;
}
static inline u32 psec_fbif_ctl_r(void)
{
return 0x00087624U;
}
static inline u32 psec_fbif_ctl_allow_phys_no_ctx_init_f(void)
{
return 0x0U;
}
static inline u32 psec_fbif_ctl_allow_phys_no_ctx_disallow_f(void)
{
return 0x0U;
}
static inline u32 psec_fbif_ctl_allow_phys_no_ctx_allow_f(void)
{
return 0x80U;
}
#define psec_falcon_irqsset_r() (0x00087000U)
#define psec_falcon_irqsset_swgen0_set_f() (0x40U)
#define psec_falcon_irqsclr_r() (0x00087004U)
#define psec_falcon_irqstat_r() (0x00087008U)
#define psec_falcon_irqstat_halt_true_f() (0x10U)
#define psec_falcon_irqstat_exterr_true_f() (0x20U)
#define psec_falcon_irqstat_swgen0_true_f() (0x40U)
#define psec_falcon_irqmode_r() (0x0008700cU)
#define psec_falcon_irqmset_r() (0x00087010U)
#define psec_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U)
#define psec_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U)
#define psec_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U)
#define psec_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U)
#define psec_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U)
#define psec_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U)
#define psec_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U)
#define psec_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U)
#define psec_falcon_irqmclr_r() (0x00087014U)
#define psec_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U)
#define psec_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U)
#define psec_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U)
#define psec_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U)
#define psec_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U)
#define psec_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U)
#define psec_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U)
#define psec_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U)
#define psec_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U)
#define psec_falcon_irqmask_r() (0x00087018U)
#define psec_falcon_irqdest_r() (0x0008701cU)
#define psec_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U)
#define psec_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U)
#define psec_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U)
#define psec_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U)
#define psec_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U)
#define psec_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U)
#define psec_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U)
#define psec_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U)
#define psec_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U)
#define psec_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U)
#define psec_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U)
#define psec_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U)
#define psec_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U)
#define psec_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U)
#define psec_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U)
#define psec_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U)
#define psec_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U)
#define psec_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U)
#define psec_falcon_curctx_r() (0x00087050U)
#define psec_falcon_nxtctx_r() (0x00087054U)
#define psec_falcon_mailbox0_r() (0x00087040U)
#define psec_falcon_mailbox1_r() (0x00087044U)
#define psec_falcon_itfen_r() (0x00087048U)
#define psec_falcon_itfen_ctxen_enable_f() (0x1U)
#define psec_falcon_idlestate_r() (0x0008704cU)
#define psec_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U)
#define psec_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU)
#define psec_falcon_os_r() (0x00087080U)
#define psec_falcon_engctl_r() (0x000870a4U)
#define psec_falcon_cpuctl_r() (0x00087100U)
#define psec_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U)
#define psec_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U)
#define psec_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define psec_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define psec_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U)
#define psec_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define psec_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define psec_falcon_cpuctl_alias_r() (0x00087130U)
#define psec_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U)
#define psec_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00087180U, nvgpu_safe_mult_u32((i), 16U)))
#define psec_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U)
#define psec_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U)
#define psec_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U)
#define psec_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00087184U, nvgpu_safe_mult_u32((i), 16U)))
#define psec_falcon_imemt_r(i)\
(nvgpu_safe_add_u32(0x00087188U, nvgpu_safe_mult_u32((i), 16U)))
#define psec_falcon_sctl_r() (0x00087240U)
#define psec_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define psec_falcon_bootvec_r() (0x00087104U)
#define psec_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U)
#define psec_falcon_dmactl_r() (0x0008710cU)
#define psec_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define psec_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define psec_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U)
#define psec_falcon_hwcfg_r() (0x00087108U)
#define psec_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define psec_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
#define psec_falcon_dmatrfbase_r() (0x00087110U)
#define psec_falcon_dmatrfbase1_r() (0x00087128U)
#define psec_falcon_dmatrfmoffs_r() (0x00087114U)
#define psec_falcon_dmatrfcmd_r() (0x00087118U)
#define psec_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U)
#define psec_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U)
#define psec_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U)
#define psec_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U)
#define psec_falcon_dmatrffboffs_r() (0x0008711cU)
#define psec_falcon_exterraddr_r() (0x00087168U)
#define psec_falcon_exterrstat_r() (0x0008716cU)
#define psec_falcon_exterrstat_valid_m() (U32(0x1U) << 31U)
#define psec_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U)
#define psec_falcon_exterrstat_valid_true_v() (0x00000001U)
#define psec_sec2_falcon_icd_cmd_r() (0x00087200U)
#define psec_sec2_falcon_icd_cmd_opc_s() (4U)
#define psec_sec2_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U)
#define psec_sec2_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define psec_sec2_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define psec_sec2_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define psec_sec2_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define psec_sec2_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U)
#define psec_sec2_falcon_icd_rdata_r() (0x0008720cU)
#define psec_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000871c0U, nvgpu_safe_mult_u32((i), 8U)))
#define psec_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U)
#define psec_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define psec_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U)
#define psec_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define psec_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U)
#define psec_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U)
#define psec_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000871c4U, nvgpu_safe_mult_u32((i), 8U)))
#define psec_falcon_debug1_r() (0x00087090U)
#define psec_falcon_debug1_ctxsw_mode_s() (1U)
#define psec_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U)
#define psec_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define psec_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define psec_falcon_debug1_ctxsw_mode_init_f() (0x0U)
#define psec_fbif_transcfg_r(i)\
(nvgpu_safe_add_u32(0x00087600U, nvgpu_safe_mult_u32((i), 4U)))
#define psec_fbif_transcfg_target_local_fb_f() (0x0U)
#define psec_fbif_transcfg_target_coherent_sysmem_f() (0x1U)
#define psec_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U)
#define psec_fbif_transcfg_mem_type_s() (1U)
#define psec_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U)
#define psec_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U)
#define psec_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U)
#define psec_fbif_transcfg_mem_type_virtual_f() (0x0U)
#define psec_fbif_transcfg_mem_type_physical_f() (0x4U)
#define psec_falcon_engine_r() (0x000873c0U)
#define psec_falcon_engine_reset_true_f() (0x1U)
#define psec_falcon_engine_reset_false_f() (0x0U)
#define psec_fbif_ctl_r() (0x00087624U)
#define psec_fbif_ctl_allow_phys_no_ctx_init_f() (0x0U)
#define psec_fbif_ctl_allow_phys_no_ctx_disallow_f() (0x0U)
#define psec_fbif_ctl_allow_phys_no_ctx_allow_f() (0x80U)
#endif

1104
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
View File

File diff suppressed because it is too large Load Diff

567
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ram_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,456 +59,117 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ram_in_ramfc_s(void)
{
return 4096U;
}
static inline u32 ram_in_ramfc_w(void)
{
return 0U;
}
static inline u32 ram_in_page_dir_base_target_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ram_in_page_dir_base_target_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 ram_in_page_dir_base_vol_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_vol_true_f(void)
{
return 0x4U;
}
static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
{
return 0x10U;
}
static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
{
return U32(0x1U) << 5U;
}
static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
{
return 0x20U;
}
static inline u32 ram_in_use_ver2_pt_format_f(u32 v)
{
return (v & 0x1U) << 10U;
}
static inline u32 ram_in_use_ver2_pt_format_m(void)
{
return U32(0x1U) << 10U;
}
static inline u32 ram_in_use_ver2_pt_format_w(void)
{
return 128U;
}
static inline u32 ram_in_use_ver2_pt_format_true_f(void)
{
return 0x400U;
}
static inline u32 ram_in_use_ver2_pt_format_false_f(void)
{
return 0x0U;
}
static inline u32 ram_in_big_page_size_f(u32 v)
{
return (v & 0x1U) << 11U;
}
static inline u32 ram_in_big_page_size_m(void)
{
return U32(0x1U) << 11U;
}
static inline u32 ram_in_big_page_size_w(void)
{
return 128U;
}
static inline u32 ram_in_big_page_size_128kb_f(void)
{
return 0x0U;
}
static inline u32 ram_in_big_page_size_64kb_f(void)
{
return 0x800U;
}
static inline u32 ram_in_page_dir_base_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_page_dir_base_lo_w(void)
{
return 128U;
}
static inline u32 ram_in_page_dir_base_hi_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 ram_in_page_dir_base_hi_w(void)
{
return 129U;
}
static inline u32 ram_in_adr_limit_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_adr_limit_lo_w(void)
{
return 130U;
}
static inline u32 ram_in_adr_limit_hi_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 ram_in_adr_limit_hi_w(void)
{
return 131U;
}
static inline u32 ram_in_engine_cs_w(void)
{
return 132U;
}
static inline u32 ram_in_engine_cs_wfi_v(void)
{
return 0x00000000U;
}
static inline u32 ram_in_engine_cs_wfi_f(void)
{
return 0x0U;
}
static inline u32 ram_in_engine_cs_fg_v(void)
{
return 0x00000001U;
}
static inline u32 ram_in_engine_cs_fg_f(void)
{
return 0x8U;
}
static inline u32 ram_in_gr_cs_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_cs_wfi_f(void)
{
return 0x0U;
}
static inline u32 ram_in_gr_wfi_target_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_wfi_mode_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_wfi_mode_physical_v(void)
{
return 0x00000000U;
}
static inline u32 ram_in_gr_wfi_mode_physical_f(void)
{
return 0x0U;
}
static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
{
return 0x00000001U;
}
static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
{
return 0x4U;
}
static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
{
return 132U;
}
static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
{
return 133U;
}
static inline u32 ram_in_base_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 ram_in_alloc_size_v(void)
{
return 0x00001000U;
}
static inline u32 ram_fc_size_val_v(void)
{
return 0x00000200U;
}
static inline u32 ram_fc_gp_put_w(void)
{
return 0U;
}
static inline u32 ram_fc_userd_w(void)
{
return 2U;
}
static inline u32 ram_fc_userd_hi_w(void)
{
return 3U;
}
static inline u32 ram_fc_signature_w(void)
{
return 4U;
}
static inline u32 ram_fc_gp_get_w(void)
{
return 5U;
}
static inline u32 ram_fc_pb_get_w(void)
{
return 6U;
}
static inline u32 ram_fc_pb_get_hi_w(void)
{
return 7U;
}
static inline u32 ram_fc_pb_top_level_get_w(void)
{
return 8U;
}
static inline u32 ram_fc_pb_top_level_get_hi_w(void)
{
return 9U;
}
static inline u32 ram_fc_acquire_w(void)
{
return 12U;
}
static inline u32 ram_fc_semaphorea_w(void)
{
return 14U;
}
static inline u32 ram_fc_semaphoreb_w(void)
{
return 15U;
}
static inline u32 ram_fc_semaphorec_w(void)
{
return 16U;
}
static inline u32 ram_fc_semaphored_w(void)
{
return 17U;
}
static inline u32 ram_fc_gp_base_w(void)
{
return 18U;
}
static inline u32 ram_fc_gp_base_hi_w(void)
{
return 19U;
}
static inline u32 ram_fc_gp_fetch_w(void)
{
return 20U;
}
static inline u32 ram_fc_pb_fetch_w(void)
{
return 21U;
}
static inline u32 ram_fc_pb_fetch_hi_w(void)
{
return 22U;
}
static inline u32 ram_fc_pb_put_w(void)
{
return 23U;
}
static inline u32 ram_fc_pb_put_hi_w(void)
{
return 24U;
}
static inline u32 ram_fc_pb_header_w(void)
{
return 33U;
}
static inline u32 ram_fc_pb_count_w(void)
{
return 34U;
}
static inline u32 ram_fc_subdevice_w(void)
{
return 37U;
}
static inline u32 ram_fc_formats_w(void)
{
return 39U;
}
static inline u32 ram_fc_target_w(void)
{
return 43U;
}
static inline u32 ram_fc_hce_ctrl_w(void)
{
return 57U;
}
static inline u32 ram_fc_chid_w(void)
{
return 58U;
}
static inline u32 ram_fc_chid_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 ram_fc_chid_id_w(void)
{
return 0U;
}
static inline u32 ram_fc_config_w(void)
{
return 61U;
}
static inline u32 ram_fc_runlist_timeslice_w(void)
{
return 62U;
}
static inline u32 ram_userd_base_shift_v(void)
{
return 0x00000009U;
}
static inline u32 ram_userd_chan_size_v(void)
{
return 0x00000200U;
}
static inline u32 ram_userd_put_w(void)
{
return 16U;
}
static inline u32 ram_userd_get_w(void)
{
return 17U;
}
static inline u32 ram_userd_ref_w(void)
{
return 18U;
}
static inline u32 ram_userd_put_hi_w(void)
{
return 19U;
}
static inline u32 ram_userd_top_level_get_w(void)
{
return 22U;
}
static inline u32 ram_userd_top_level_get_hi_w(void)
{
return 23U;
}
static inline u32 ram_userd_get_hi_w(void)
{
return 24U;
}
static inline u32 ram_userd_gp_get_w(void)
{
return 34U;
}
static inline u32 ram_userd_gp_put_w(void)
{
return 35U;
}
static inline u32 ram_userd_gp_top_level_get_w(void)
{
return 22U;
}
static inline u32 ram_userd_gp_top_level_get_hi_w(void)
{
return 23U;
}
static inline u32 ram_rl_entry_size_v(void)
{
return 0x00000008U;
}
static inline u32 ram_rl_entry_chid_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 ram_rl_entry_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 ram_rl_entry_type_f(u32 v)
{
return (v & 0x1U) << 13U;
}
static inline u32 ram_rl_entry_type_chid_f(void)
{
return 0x0U;
}
static inline u32 ram_rl_entry_type_tsg_f(void)
{
return 0x2000U;
}
static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
{
return (v & 0xfU) << 14U;
}
static inline u32 ram_rl_entry_timeslice_scale_v(u32 r)
{
return (r >> 14U) & 0xfU;
}
static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
{
return 0xc000U;
}
static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
{
return (v & 0xffU) << 18U;
}
static inline u32 ram_rl_entry_timeslice_timeout_v(u32 r)
{
return (r >> 18U) & 0xffU;
}
static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
{
return 0x2000000U;
}
static inline u32 ram_rl_entry_tsg_length_f(u32 v)
{
return (v & 0x3fU) << 26U;
}
#define ram_in_ramfc_s() (4096U)
#define ram_in_ramfc_w() (0U)
#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U)
#define ram_in_page_dir_base_target_w() (128U)
#define ram_in_page_dir_base_target_vid_mem_f() (0x0U)
#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U)
#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U)
#define ram_in_page_dir_base_vol_w() (128U)
#define ram_in_page_dir_base_vol_true_f() (0x4U)
#define ram_in_page_dir_base_fault_replay_tex_f(v) (((v)&0x1U) << 4U)
#define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U)
#define ram_in_page_dir_base_fault_replay_tex_w() (128U)
#define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U)
#define ram_in_page_dir_base_fault_replay_gcc_f(v) (((v)&0x1U) << 5U)
#define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U)
#define ram_in_page_dir_base_fault_replay_gcc_w() (128U)
#define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U)
#define ram_in_use_ver2_pt_format_f(v) (((v)&0x1U) << 10U)
#define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U)
#define ram_in_use_ver2_pt_format_w() (128U)
#define ram_in_use_ver2_pt_format_true_f() (0x400U)
#define ram_in_use_ver2_pt_format_false_f() (0x0U)
#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U)
#define ram_in_big_page_size_m() (U32(0x1U) << 11U)
#define ram_in_big_page_size_w() (128U)
#define ram_in_big_page_size_128kb_f() (0x0U)
#define ram_in_big_page_size_64kb_f() (0x800U)
#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U)
#define ram_in_page_dir_base_lo_w() (128U)
#define ram_in_page_dir_base_hi_f(v) (((v)&0xffffffffU) << 0U)
#define ram_in_page_dir_base_hi_w() (129U)
#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U)
#define ram_in_adr_limit_lo_w() (130U)
#define ram_in_adr_limit_hi_f(v) (((v)&0xffffffffU) << 0U)
#define ram_in_adr_limit_hi_w() (131U)
#define ram_in_engine_cs_w() (132U)
#define ram_in_engine_cs_wfi_v() (0x00000000U)
#define ram_in_engine_cs_wfi_f() (0x0U)
#define ram_in_engine_cs_fg_v() (0x00000001U)
#define ram_in_engine_cs_fg_f() (0x8U)
#define ram_in_gr_cs_w() (132U)
#define ram_in_gr_cs_wfi_f() (0x0U)
#define ram_in_gr_wfi_target_w() (132U)
#define ram_in_gr_wfi_mode_w() (132U)
#define ram_in_gr_wfi_mode_physical_v() (0x00000000U)
#define ram_in_gr_wfi_mode_physical_f() (0x0U)
#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U)
#define ram_in_gr_wfi_mode_virtual_f() (0x4U)
#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U)
#define ram_in_gr_wfi_ptr_lo_w() (132U)
#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U)
#define ram_in_gr_wfi_ptr_hi_w() (133U)
#define ram_in_base_shift_v() (0x0000000cU)
#define ram_in_alloc_size_v() (0x00001000U)
#define ram_fc_size_val_v() (0x00000200U)
#define ram_fc_gp_put_w() (0U)
#define ram_fc_userd_w() (2U)
#define ram_fc_userd_hi_w() (3U)
#define ram_fc_signature_w() (4U)
#define ram_fc_gp_get_w() (5U)
#define ram_fc_pb_get_w() (6U)
#define ram_fc_pb_get_hi_w() (7U)
#define ram_fc_pb_top_level_get_w() (8U)
#define ram_fc_pb_top_level_get_hi_w() (9U)
#define ram_fc_acquire_w() (12U)
#define ram_fc_semaphorea_w() (14U)
#define ram_fc_semaphoreb_w() (15U)
#define ram_fc_semaphorec_w() (16U)
#define ram_fc_semaphored_w() (17U)
#define ram_fc_gp_base_w() (18U)
#define ram_fc_gp_base_hi_w() (19U)
#define ram_fc_gp_fetch_w() (20U)
#define ram_fc_pb_fetch_w() (21U)
#define ram_fc_pb_fetch_hi_w() (22U)
#define ram_fc_pb_put_w() (23U)
#define ram_fc_pb_put_hi_w() (24U)
#define ram_fc_pb_header_w() (33U)
#define ram_fc_pb_count_w() (34U)
#define ram_fc_subdevice_w() (37U)
#define ram_fc_formats_w() (39U)
#define ram_fc_target_w() (43U)
#define ram_fc_hce_ctrl_w() (57U)
#define ram_fc_chid_w() (58U)
#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U)
#define ram_fc_chid_id_w() (0U)
#define ram_fc_config_w() (61U)
#define ram_fc_runlist_timeslice_w() (62U)
#define ram_userd_base_shift_v() (0x00000009U)
#define ram_userd_chan_size_v() (0x00000200U)
#define ram_userd_put_w() (16U)
#define ram_userd_get_w() (17U)
#define ram_userd_ref_w() (18U)
#define ram_userd_put_hi_w() (19U)
#define ram_userd_top_level_get_w() (22U)
#define ram_userd_top_level_get_hi_w() (23U)
#define ram_userd_get_hi_w() (24U)
#define ram_userd_gp_get_w() (34U)
#define ram_userd_gp_put_w() (35U)
#define ram_userd_gp_top_level_get_w() (22U)
#define ram_userd_gp_top_level_get_hi_w() (23U)
#define ram_rl_entry_size_v() (0x00000008U)
#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U)
#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U)
#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U)
#define ram_rl_entry_type_chid_f() (0x0U)
#define ram_rl_entry_type_tsg_f() (0x2000U)
#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U)
#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU)
#define ram_rl_entry_timeslice_scale_3_f() (0xc000U)
#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U)
#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU)
#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U)
#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U)
#endif

103
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_therm_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,84 +59,25 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 therm_gate_ctrl_r(u32 i)
{
return nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 therm_gate_ctrl_eng_clk_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
{
return 0x0U;
}
static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
{
return 0x1U;
}
static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
{
return 0x2U;
}
static inline u32 therm_gate_ctrl_blk_clk_m(void)
{
return U32(0x3U) << 2U;
}
static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
{
return 0x0U;
}
static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
{
return 0x4U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
{
return (v & 0x1fU) << 8U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
{
return U32(0x1fU) << 8U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
{
return (v & 0x7U) << 13U;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
{
return U32(0x7U) << 13U;
}
static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
{
return (v & 0xfU) << 16U;
}
static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
{
return U32(0xfU) << 16U;
}
static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
{
return (v & 0xfU) << 20U;
}
static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
{
return U32(0xfU) << 20U;
}
static inline u32 therm_fecs_idle_filter_r(void)
{
return 0x00020288U;
}
static inline u32 therm_fecs_idle_filter_value_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 therm_hubmmu_idle_filter_r(void)
{
return 0x0002028cU;
}
static inline u32 therm_hubmmu_idle_filter_value_m(void)
{
return U32(0xffffffffU) << 0U;
}
#define therm_gate_ctrl_r(i)\
(nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U)
#define therm_gate_ctrl_eng_clk_run_f() (0x0U)
#define therm_gate_ctrl_eng_clk_auto_f() (0x1U)
#define therm_gate_ctrl_eng_clk_stop_f() (0x2U)
#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U)
#define therm_gate_ctrl_blk_clk_run_f() (0x0U)
#define therm_gate_ctrl_blk_clk_auto_f() (0x4U)
#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U)
#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U)
#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U)
#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U)
#define therm_fecs_idle_filter_r() (0x00020288U)
#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U)
#define therm_hubmmu_idle_filter_r() (0x0002028cU)
#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U)
#endif

72
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_timer_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,60 +59,18 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 timer_pri_timeout_r(void)
{
return 0x00009080U;
}
static inline u32 timer_pri_timeout_period_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 timer_pri_timeout_period_m(void)
{
return U32(0xffffffU) << 0U;
}
static inline u32 timer_pri_timeout_period_v(u32 r)
{
return (r >> 0U) & 0xffffffU;
}
static inline u32 timer_pri_timeout_en_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 timer_pri_timeout_en_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 timer_pri_timeout_en_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 timer_pri_timeout_en_en_enabled_f(void)
{
return 0x80000000U;
}
static inline u32 timer_pri_timeout_en_en_disabled_f(void)
{
return 0x0U;
}
static inline u32 timer_pri_timeout_save_0_r(void)
{
return 0x00009084U;
}
static inline u32 timer_pri_timeout_save_1_r(void)
{
return 0x00009088U;
}
static inline u32 timer_pri_timeout_fecs_errcode_r(void)
{
return 0x0000908cU;
}
static inline u32 timer_time_0_r(void)
{
return 0x00009400U;
}
static inline u32 timer_time_1_r(void)
{
return 0x00009410U;
}
#define timer_pri_timeout_r() (0x00009080U)
#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U)
#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U)
#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU)
#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U)
#define timer_pri_timeout_en_m() (U32(0x1U) << 31U)
#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U)
#define timer_pri_timeout_en_en_enabled_f() (0x80000000U)
#define timer_pri_timeout_en_en_disabled_f() (0x0U)
#define timer_pri_timeout_save_0_r() (0x00009084U)
#define timer_pri_timeout_save_1_r() (0x00009088U)
#define timer_pri_timeout_fecs_errcode_r() (0x0000908cU)
#define timer_time_0_r() (0x00009400U)
#define timer_time_1_r() (0x00009410U)
#endif

273
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,220 +59,59 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 top_num_gpcs_r(void)
{
return 0x00022430U;
}
static inline u32 top_num_gpcs_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_tpc_per_gpc_r(void)
{
return 0x00022434U;
}
static inline u32 top_tpc_per_gpc_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_num_fbps_r(void)
{
return 0x00022438U;
}
static inline u32 top_num_fbps_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_num_fbpas_r(void)
{
return 0x0002243cU;
}
static inline u32 top_num_fbpas_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_ltc_per_fbp_r(void)
{
return 0x00022450U;
}
static inline u32 top_ltc_per_fbp_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_slices_per_ltc_r(void)
{
return 0x0002245cU;
}
static inline u32 top_slices_per_ltc_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_num_ltcs_r(void)
{
return 0x00022454U;
}
static inline u32 top_device_info_r(u32 i)
{
return nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 top_device_info__size_1_v(void)
{
return 0x00000040U;
}
static inline u32 top_device_info_chain_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 top_device_info_chain_enable_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_chain_disable_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_engine_enum_v(u32 r)
{
return (r >> 26U) & 0xfU;
}
static inline u32 top_device_info_runlist_enum_v(u32 r)
{
return (r >> 21U) & 0xfU;
}
static inline u32 top_device_info_intr_enum_v(u32 r)
{
return (r >> 15U) & 0x1fU;
}
static inline u32 top_device_info_reset_enum_v(u32 r)
{
return (r >> 9U) & 0x1fU;
}
static inline u32 top_device_info_type_enum_v(u32 r)
{
return (r >> 2U) & 0x1fffffffU;
}
static inline u32 top_device_info_type_enum_graphics_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_type_enum_graphics_f(void)
{
return 0x0U;
}
static inline u32 top_device_info_type_enum_copy0_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_type_enum_copy0_f(void)
{
return 0x4U;
}
static inline u32 top_device_info_type_enum_copy2_v(void)
{
return 0x00000003U;
}
static inline u32 top_device_info_type_enum_copy2_f(void)
{
return 0xcU;
}
static inline u32 top_device_info_type_enum_lce_v(void)
{
return 0x00000013U;
}
static inline u32 top_device_info_type_enum_lce_f(void)
{
return 0x4cU;
}
static inline u32 top_device_info_engine_v(u32 r)
{
return (r >> 5U) & 0x1U;
}
static inline u32 top_device_info_engine_valid_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_runlist_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 top_device_info_runlist_valid_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_intr_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 top_device_info_intr_valid_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_reset_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 top_device_info_reset_valid_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_entry_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 top_device_info_entry_not_valid_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_entry_enum_v(void)
{
return 0x00000002U;
}
static inline u32 top_device_info_entry_engine_type_v(void)
{
return 0x00000003U;
}
static inline u32 top_device_info_entry_data_v(void)
{
return 0x00000001U;
}
static inline u32 top_device_info_data_type_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 top_device_info_data_type_enum2_v(void)
{
return 0x00000000U;
}
static inline u32 top_device_info_data_inst_id_v(u32 r)
{
return (r >> 26U) & 0xfU;
}
static inline u32 top_device_info_data_pri_base_v(u32 r)
{
return (r >> 12U) & 0xfffU;
}
static inline u32 top_device_info_data_pri_base_align_v(void)
{
return 0x0000000cU;
}
static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
{
return (r >> 3U) & 0x1fU;
}
static inline u32 top_device_info_data_fault_id_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 top_device_info_data_fault_id_valid_v(void)
{
return 0x00000001U;
}
static inline u32 top_scratch1_r(void)
{
return 0x0002240cU;
}
static inline u32 top_scratch1_devinit_completed_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
#define top_num_gpcs_r() (0x00022430U)
#define top_num_gpcs_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_tpc_per_gpc_r() (0x00022434U)
#define top_tpc_per_gpc_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_num_fbps_r() (0x00022438U)
#define top_num_fbps_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_num_fbpas_r() (0x0002243cU)
#define top_num_fbpas_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_ltc_per_fbp_r() (0x00022450U)
#define top_ltc_per_fbp_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_slices_per_ltc_r() (0x0002245cU)
#define top_slices_per_ltc_value_v(r) (((r) >> 0U) & 0x1fU)
#define top_num_ltcs_r() (0x00022454U)
#define top_device_info_r(i)\
(nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32((i), 4U)))
#define top_device_info__size_1_v() (0x00000040U)
#define top_device_info_chain_v(r) (((r) >> 31U) & 0x1U)
#define top_device_info_chain_enable_v() (0x00000001U)
#define top_device_info_chain_disable_v() (0x00000000U)
#define top_device_info_engine_enum_v(r) (((r) >> 26U) & 0xfU)
#define top_device_info_runlist_enum_v(r) (((r) >> 21U) & 0xfU)
#define top_device_info_intr_enum_v(r) (((r) >> 15U) & 0x1fU)
#define top_device_info_reset_enum_v(r) (((r) >> 9U) & 0x1fU)
#define top_device_info_type_enum_v(r) (((r) >> 2U) & 0x1fffffffU)
#define top_device_info_type_enum_graphics_v() (0x00000000U)
#define top_device_info_type_enum_graphics_f() (0x0U)
#define top_device_info_type_enum_copy0_v() (0x00000001U)
#define top_device_info_type_enum_copy0_f() (0x4U)
#define top_device_info_type_enum_copy2_v() (0x00000003U)
#define top_device_info_type_enum_copy2_f() (0xcU)
#define top_device_info_type_enum_lce_v() (0x00000013U)
#define top_device_info_type_enum_lce_f() (0x4cU)
#define top_device_info_engine_v(r) (((r) >> 5U) & 0x1U)
#define top_device_info_engine_valid_v() (0x00000001U)
#define top_device_info_runlist_v(r) (((r) >> 4U) & 0x1U)
#define top_device_info_runlist_valid_v() (0x00000001U)
#define top_device_info_intr_v(r) (((r) >> 3U) & 0x1U)
#define top_device_info_intr_valid_v() (0x00000001U)
#define top_device_info_reset_v(r) (((r) >> 2U) & 0x1U)
#define top_device_info_reset_valid_v() (0x00000001U)
#define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U)
#define top_device_info_entry_not_valid_v() (0x00000000U)
#define top_device_info_entry_enum_v() (0x00000002U)
#define top_device_info_entry_engine_type_v() (0x00000003U)
#define top_device_info_entry_data_v() (0x00000001U)
#define top_device_info_data_type_v(r) (((r) >> 30U) & 0x1U)
#define top_device_info_data_type_enum2_v() (0x00000000U)
#define top_device_info_data_inst_id_v(r) (((r) >> 26U) & 0xfU)
#define top_device_info_data_pri_base_v(r) (((r) >> 12U) & 0xfffU)
#define top_device_info_data_pri_base_align_v() (0x0000000cU)
#define top_device_info_data_fault_id_enum_v(r) (((r) >> 3U) & 0x1fU)
#define top_device_info_data_fault_id_v(r) (((r) >> 2U) & 0x1U)
#define top_device_info_data_fault_id_valid_v() (0x00000001U)
#define top_scratch1_r() (0x0002240cU)
#define top_scratch1_devinit_completed_v(r) (((r) >> 1U) & 0x1U)
#endif

175
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_trim_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,140 +59,41 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(void)
{
return 0x00132924U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s(void)
{
return 16U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m(void)
{
return U32(0xffffU) << 0U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s(void)
{
return 1U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f(void)
{
return 0x0U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
{
return 0x10000U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s(void)
{
return 1U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(u32 v)
{
return (v & 0x1U) << 20U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m(void)
{
return U32(0x1U) << 20U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(u32 r)
{
return (r >> 20U) & 0x1U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f(void)
{
return 0x0U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
{
return 0x100000U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s(void)
{
return 1U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m(void)
{
return U32(0x1U) << 24U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(u32 r)
{
return (r >> 24U) & 0x1U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f(void)
{
return 0x0U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
{
return 0x1000000U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(void)
{
return 0x70000000U;
}
static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(void)
{
return 0x00132928U;
}
static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(void)
{
return 0x00132128U;
}
static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(void)
{
return 0x30000000U;
}
static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(void)
{
return 0x0013212cU;
}
static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_r(void)
{
return 0x001373c0U;
}
static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(void)
{
return 0x20000000U;
}
static inline u32 trim_sys_clk_cntr_ncltcpll_cnt_r(void)
{
return 0x001373c4U;
}
static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_r(void)
{
return 0x001373b0U;
}
static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(void)
{
return 0x0U;
}
static inline u32 trim_sys_clk_cntr_ncsyspll_cnt_r(void)
{
return 0x001373b4U;
}
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r() (0x00132924U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s() (16U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(v)\
(((v)&0xffffU) << 0U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m() (U32(0xffffU) << 0U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(r)\
(((r) >> 0U) & 0xffffU)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s() (1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(v) (((v)&0x1U) << 16U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m() (U32(0x1U) << 16U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(r) (((r) >> 16U) & 0x1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f() (0x0U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s() (1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(v) (((v)&0x1U) << 20U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m() (U32(0x1U) << 20U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(r) (((r) >> 20U) & 0x1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f() (0x0U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s() (1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(v) (((v)&0x1U) << 24U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m() (U32(0x1U) << 24U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(r) (((r) >> 24U) & 0x1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f() (0x0U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f() (0x70000000U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r() (0x00132928U)
#define trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r() (0x00132128U)
#define trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f()\
(0x30000000U)
#define trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r() (0x0013212cU)
#define trim_sys_clk_cntr_ncltcpll_cfg_r() (0x001373c0U)
#define trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f() (0x20000000U)
#define trim_sys_clk_cntr_ncltcpll_cnt_r() (0x001373c4U)
#define trim_sys_clk_cntr_ncsyspll_cfg_r() (0x001373b0U)
#define trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f() (0x0U)
#define trim_sys_clk_cntr_ncsyspll_cnt_r() (0x001373b4U)
#endif

109
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xp_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,88 +59,27 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 xp_dl_mgr_r(u32 i)
{
return nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 xp_dl_mgr_safe_timing_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 xp_pl_link_config_r(u32 i)
{
return nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 xp_pl_link_config_ltssm_status_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 xp_pl_link_config_ltssm_status_idle_v(void)
{
return 0x00000000U;
}
static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 xp_pl_link_config_ltssm_directive_m(void)
{
return U32(0xfU) << 0U;
}
static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void)
{
return 0x00000000U;
}
static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void)
{
return 0x00000001U;
}
static inline u32 xp_pl_link_config_max_link_rate_f(u32 v)
{
return (v & 0x3U) << 18U;
}
static inline u32 xp_pl_link_config_max_link_rate_m(void)
{
return U32(0x3U) << 18U;
}
static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void)
{
return 0x00000002U;
}
static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void)
{
return 0x00000001U;
}
static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void)
{
return 0x00000000U;
}
static inline u32 xp_pl_link_config_target_tx_width_f(u32 v)
{
return (v & 0x7U) << 20U;
}
static inline u32 xp_pl_link_config_target_tx_width_m(void)
{
return U32(0x7U) << 20U;
}
static inline u32 xp_pl_link_config_target_tx_width_x1_v(void)
{
return 0x00000007U;
}
static inline u32 xp_pl_link_config_target_tx_width_x2_v(void)
{
return 0x00000006U;
}
static inline u32 xp_pl_link_config_target_tx_width_x4_v(void)
{
return 0x00000005U;
}
static inline u32 xp_pl_link_config_target_tx_width_x8_v(void)
{
return 0x00000004U;
}
static inline u32 xp_pl_link_config_target_tx_width_x16_v(void)
{
return 0x00000000U;
}
#define xp_dl_mgr_r(i)\
(nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32((i), 4U)))
#define xp_dl_mgr_safe_timing_f(v) (((v)&0x1U) << 2U)
#define xp_pl_link_config_r(i)\
(nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32((i), 4U)))
#define xp_pl_link_config_ltssm_status_f(v) (((v)&0x1U) << 4U)
#define xp_pl_link_config_ltssm_status_idle_v() (0x00000000U)
#define xp_pl_link_config_ltssm_directive_f(v) (((v)&0xfU) << 0U)
#define xp_pl_link_config_ltssm_directive_m() (U32(0xfU) << 0U)
#define xp_pl_link_config_ltssm_directive_normal_operations_v() (0x00000000U)
#define xp_pl_link_config_ltssm_directive_change_speed_v() (0x00000001U)
#define xp_pl_link_config_max_link_rate_f(v) (((v)&0x3U) << 18U)
#define xp_pl_link_config_max_link_rate_m() (U32(0x3U) << 18U)
#define xp_pl_link_config_max_link_rate_2500_mtps_v() (0x00000002U)
#define xp_pl_link_config_max_link_rate_5000_mtps_v() (0x00000001U)
#define xp_pl_link_config_max_link_rate_8000_mtps_v() (0x00000000U)
#define xp_pl_link_config_target_tx_width_f(v) (((v)&0x7U) << 20U)
#define xp_pl_link_config_target_tx_width_m() (U32(0x7U) << 20U)
#define xp_pl_link_config_target_tx_width_x1_v() (0x00000007U)
#define xp_pl_link_config_target_tx_width_x2_v() (0x00000006U)
#define xp_pl_link_config_target_tx_width_x4_v() (0x00000005U)
#define xp_pl_link_config_target_tx_width_x8_v() (0x00000004U)
#define xp_pl_link_config_target_tx_width_x16_v() (0x00000000U)
#endif

187
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,152 +59,41 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 xve_rom_ctrl_r(void)
{
return 0x00000050U;
}
static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void)
{
return 0x0U;
}
static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void)
{
return 0x1U;
}
static inline u32 xve_link_control_status_r(void)
{
return 0x00000088U;
}
static inline u32 xve_link_control_status_link_speed_m(void)
{
return U32(0xfU) << 16U;
}
static inline u32 xve_link_control_status_link_speed_v(u32 r)
{
return (r >> 16U) & 0xfU;
}
static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void)
{
return 0x00000001U;
}
static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void)
{
return 0x00000002U;
}
static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void)
{
return 0x00000003U;
}
static inline u32 xve_link_control_status_link_width_m(void)
{
return U32(0x3fU) << 20U;
}
static inline u32 xve_link_control_status_link_width_v(u32 r)
{
return (r >> 20U) & 0x3fU;
}
static inline u32 xve_link_control_status_link_width_x1_v(void)
{
return 0x00000001U;
}
static inline u32 xve_link_control_status_link_width_x2_v(void)
{
return 0x00000002U;
}
static inline u32 xve_link_control_status_link_width_x4_v(void)
{
return 0x00000004U;
}
static inline u32 xve_link_control_status_link_width_x8_v(void)
{
return 0x00000008U;
}
static inline u32 xve_link_control_status_link_width_x16_v(void)
{
return 0x00000010U;
}
static inline u32 xve_priv_xv_r(void)
{
return 0x00000150U;
}
static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 xve_priv_xv_cya_l0s_enable_m(void)
{
return U32(0x1U) << 7U;
}
static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r)
{
return (r >> 7U) & 0x1U;
}
static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v)
{
return (v & 0x1U) << 8U;
}
static inline u32 xve_priv_xv_cya_l1_enable_m(void)
{
return U32(0x1U) << 8U;
}
static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r)
{
return (r >> 8U) & 0x1U;
}
static inline u32 xve_cya_2_r(void)
{
return 0x00000704U;
}
static inline u32 xve_reset_r(void)
{
return 0x00000718U;
}
static inline u32 xve_reset_reset_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 xve_reset_gpu_on_sw_reset_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 xve_reset_counter_en_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 xve_reset_counter_val_f(u32 v)
{
return (v & 0x7ffU) << 4U;
}
static inline u32 xve_reset_counter_val_m(void)
{
return U32(0x7ffU) << 4U;
}
static inline u32 xve_reset_counter_val_v(u32 r)
{
return (r >> 4U) & 0x7ffU;
}
static inline u32 xve_reset_clock_on_sw_reset_m(void)
{
return U32(0x1U) << 15U;
}
static inline u32 xve_reset_clock_counter_en_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 xve_reset_clock_counter_val_f(u32 v)
{
return (v & 0x7ffU) << 17U;
}
static inline u32 xve_reset_clock_counter_val_m(void)
{
return U32(0x7ffU) << 17U;
}
static inline u32 xve_reset_clock_counter_val_v(u32 r)
{
return (r >> 17U) & 0x7ffU;
}
#define xve_rom_ctrl_r() (0x00000050U)
#define xve_rom_ctrl_rom_shadow_f(v) (((v)&0x1U) << 0U)
#define xve_rom_ctrl_rom_shadow_disabled_f() (0x0U)
#define xve_rom_ctrl_rom_shadow_enabled_f() (0x1U)
#define xve_link_control_status_r() (0x00000088U)
#define xve_link_control_status_link_speed_m() (U32(0xfU) << 16U)
#define xve_link_control_status_link_speed_v(r) (((r) >> 16U) & 0xfU)
#define xve_link_control_status_link_speed_link_speed_2p5_v() (0x00000001U)
#define xve_link_control_status_link_speed_link_speed_5p0_v() (0x00000002U)
#define xve_link_control_status_link_speed_link_speed_8p0_v() (0x00000003U)
#define xve_link_control_status_link_width_m() (U32(0x3fU) << 20U)
#define xve_link_control_status_link_width_v(r) (((r) >> 20U) & 0x3fU)
#define xve_link_control_status_link_width_x1_v() (0x00000001U)
#define xve_link_control_status_link_width_x2_v() (0x00000002U)
#define xve_link_control_status_link_width_x4_v() (0x00000004U)
#define xve_link_control_status_link_width_x8_v() (0x00000008U)
#define xve_link_control_status_link_width_x16_v() (0x00000010U)
#define xve_priv_xv_r() (0x00000150U)
#define xve_priv_xv_cya_l0s_enable_f(v) (((v)&0x1U) << 7U)
#define xve_priv_xv_cya_l0s_enable_m() (U32(0x1U) << 7U)
#define xve_priv_xv_cya_l0s_enable_v(r) (((r) >> 7U) & 0x1U)
#define xve_priv_xv_cya_l1_enable_f(v) (((v)&0x1U) << 8U)
#define xve_priv_xv_cya_l1_enable_m() (U32(0x1U) << 8U)
#define xve_priv_xv_cya_l1_enable_v(r) (((r) >> 8U) & 0x1U)
#define xve_cya_2_r() (0x00000704U)
#define xve_reset_r() (0x00000718U)
#define xve_reset_reset_m() (U32(0x1U) << 0U)
#define xve_reset_gpu_on_sw_reset_m() (U32(0x1U) << 1U)
#define xve_reset_counter_en_m() (U32(0x1U) << 2U)
#define xve_reset_counter_val_f(v) (((v)&0x7ffU) << 4U)
#define xve_reset_counter_val_m() (U32(0x7ffU) << 4U)
#define xve_reset_counter_val_v(r) (((r) >> 4U) & 0x7ffU)
#define xve_reset_clock_on_sw_reset_m() (U32(0x1U) << 15U)
#define xve_reset_clock_counter_en_m() (U32(0x1U) << 16U)
#define xve_reset_clock_counter_val_f(v) (((v)&0x7ffU) << 17U)
#define xve_reset_clock_counter_val_m() (U32(0x7ffU) << 17U)
#define xve_reset_clock_counter_val_v(r) (((r) >> 17U) & 0x7ffU)
#endif

227
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,184 +59,49 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 bus_bar0_window_r(void)
{
return 0x00001700U;
}
static inline u32 bus_bar0_window_base_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 bus_bar0_window_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
{
return 0x2000000U;
}
static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
{
return 0x3000000U;
}
static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
{
return 0x00000010U;
}
static inline u32 bus_bar1_block_r(void)
{
return 0x00001704U;
}
static inline u32 bus_bar1_block_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 bus_bar1_block_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 bus_bar1_block_mode_virtual_f(void)
{
return 0x80000000U;
}
static inline u32 bus_bar2_block_r(void)
{
return 0x00001714U;
}
static inline u32 bus_bar2_block_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 bus_bar2_block_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 bus_bar2_block_mode_virtual_f(void)
{
return 0x80000000U;
}
static inline u32 bus_bar1_block_ptr_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 bus_bar2_block_ptr_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 bus_bind_status_r(void)
{
return 0x00001710U;
}
static inline u32 bus_bind_status_bar1_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 bus_bind_status_bar1_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar1_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
{
return 0x2U;
}
static inline u32 bus_bind_status_bar2_pending_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 bus_bind_status_bar2_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 bus_bind_status_bar2_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar2_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 bus_bind_status_bar2_pending_busy_f(void)
{
return 0x4U;
}
static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
{
return (r >> 3U) & 0x1U;
}
static inline u32 bus_bind_status_bar2_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 bus_bind_status_bar2_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
{
return 0x8U;
}
static inline u32 bus_intr_0_r(void)
{
return 0x00001100U;
}
static inline u32 bus_intr_0_pri_squash_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 bus_intr_0_pri_fecserr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 bus_intr_0_pri_timeout_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 bus_intr_en_0_r(void)
{
return 0x00001140U;
}
static inline u32 bus_intr_en_0_pri_squash_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 bus_intr_en_0_pri_fecserr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 bus_intr_en_0_pri_timeout_m(void)
{
return U32(0x1U) << 3U;
}
#define bus_bar0_window_r() (0x00001700U)
#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U)
#define bus_bar0_window_target_vid_mem_f() (0x0U)
#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U)
#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U)
#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U)
#define bus_bar1_block_r() (0x00001704U)
#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define bus_bar1_block_target_vid_mem_f() (0x0U)
#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar1_block_mode_virtual_f() (0x80000000U)
#define bus_bar2_block_r() (0x00001714U)
#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define bus_bar2_block_target_vid_mem_f() (0x0U)
#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar2_block_mode_virtual_f() (0x80000000U)
#define bus_bar1_block_ptr_shift_v() (0x0000000cU)
#define bus_bar2_block_ptr_shift_v() (0x0000000cU)
#define bus_bind_status_r() (0x00001710U)
#define bus_bind_status_bar1_pending_v(r) (((r) >> 0U) & 0x1U)
#define bus_bind_status_bar1_pending_empty_f() (0x0U)
#define bus_bind_status_bar1_pending_busy_f() (0x1U)
#define bus_bind_status_bar1_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define bus_bind_status_bar1_outstanding_false_f() (0x0U)
#define bus_bind_status_bar1_outstanding_true_f() (0x2U)
#define bus_bind_status_bar2_pending_v(r) (((r) >> 2U) & 0x1U)
#define bus_bind_status_bar2_pending_empty_v() (0x00000000U)
#define bus_bind_status_bar2_pending_empty_f() (0x0U)
#define bus_bind_status_bar2_pending_busy_v() (0x00000001U)
#define bus_bind_status_bar2_pending_busy_f() (0x4U)
#define bus_bind_status_bar2_outstanding_v(r) (((r) >> 3U) & 0x1U)
#define bus_bind_status_bar2_outstanding_false_v() (0x00000000U)
#define bus_bind_status_bar2_outstanding_false_f() (0x0U)
#define bus_bind_status_bar2_outstanding_true_v() (0x00000001U)
#define bus_bind_status_bar2_outstanding_true_f() (0x8U)
#define bus_intr_0_r() (0x00001100U)
#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U)
#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U)
#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U)
#define bus_intr_en_0_r() (0x00001140U)
#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U)
#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U)
#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U)
#endif

184
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,148 +59,42 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ccsr_channel_inst_r(u32 i)
{
return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 ccsr_channel_inst__size_1_v(void)
{
return 0x00000200U;
}
static inline u32 ccsr_channel_inst_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 ccsr_channel_inst_bind_false_f(void)
{
return 0x0U;
}
static inline u32 ccsr_channel_inst_bind_true_f(void)
{
return 0x80000000U;
}
static inline u32 ccsr_channel_r(u32 i)
{
return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 ccsr_channel__size_1_v(void)
{
return 0x00000200U;
}
static inline u32 ccsr_channel_enable_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ccsr_channel_enable_in_use_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_enable_set_f(u32 v)
{
return (v & 0x1U) << 10U;
}
static inline u32 ccsr_channel_enable_set_true_f(void)
{
return 0x400U;
}
static inline u32 ccsr_channel_enable_clr_true_f(void)
{
return 0x800U;
}
static inline u32 ccsr_channel_status_v(u32 r)
{
return (r >> 24U) & 0xfU;
}
static inline u32 ccsr_channel_status_idle_v(void)
{
return 0x00000000U;
}
static inline u32 ccsr_channel_status_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
{
return 0x00000002U;
}
static inline u32 ccsr_channel_status_pending_acquire_v(void)
{
return 0x00000003U;
}
static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
{
return 0x00000004U;
}
static inline u32 ccsr_channel_status_on_pbdma_v(void)
{
return 0x00000005U;
}
static inline u32 ccsr_channel_status_on_pbdma_and_eng_v(void)
{
return 0x00000006U;
}
static inline u32 ccsr_channel_status_on_eng_v(void)
{
return 0x00000007U;
}
static inline u32 ccsr_channel_status_on_eng_pending_acquire_v(void)
{
return 0x00000008U;
}
static inline u32 ccsr_channel_status_on_eng_pending_v(void)
{
return 0x00000009U;
}
static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
{
return 0x0000000aU;
}
static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
{
return 0x0000000bU;
}
static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
{
return 0x0000000cU;
}
static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
{
return 0x0000000dU;
}
static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
{
return 0x0000000eU;
}
static inline u32 ccsr_channel_next_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 ccsr_channel_next_true_v(void)
{
return 0x00000001U;
}
static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
{
return 0x100U;
}
static inline u32 ccsr_channel_busy_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ccsr_channel_busy_true_v(void)
{
return 0x00000001U;
}
#define ccsr_channel_inst_r(i)\
(nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel_inst__size_1_v() (0x00000200U)
#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define ccsr_channel_inst_target_vid_mem_f() (0x0U)
#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U)
#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U)
#define ccsr_channel_inst_bind_false_f() (0x0U)
#define ccsr_channel_inst_bind_true_f() (0x80000000U)
#define ccsr_channel_r(i)\
(nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel__size_1_v() (0x00000200U)
#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U)
#define ccsr_channel_enable_in_use_v() (0x00000001U)
#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U)
#define ccsr_channel_enable_set_true_f() (0x400U)
#define ccsr_channel_enable_clr_true_f() (0x800U)
#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU)
#define ccsr_channel_status_idle_v() (0x00000000U)
#define ccsr_channel_status_pending_v() (0x00000001U)
#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U)
#define ccsr_channel_status_pending_acquire_v() (0x00000003U)
#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U)
#define ccsr_channel_status_on_pbdma_v() (0x00000005U)
#define ccsr_channel_status_on_pbdma_and_eng_v() (0x00000006U)
#define ccsr_channel_status_on_eng_v() (0x00000007U)
#define ccsr_channel_status_on_eng_pending_acquire_v() (0x00000008U)
#define ccsr_channel_status_on_eng_pending_v() (0x00000009U)
#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU)
#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU)
#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU)
#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU)
#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU)
#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U)
#define ccsr_channel_next_true_v() (0x00000001U)
#define ccsr_channel_force_ctx_reload_true_f() (0x100U)
#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U)
#define ccsr_channel_busy_true_v() (0x00000001U)
#endif

38
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,32 +59,12 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ce_intr_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32(i, 128U));
}
static inline u32 ce_intr_status_blockpipe_pending_f(void)
{
return 0x1U;
}
static inline u32 ce_intr_status_blockpipe_reset_f(void)
{
return 0x1U;
}
static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
{
return 0x2U;
}
static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
{
return 0x2U;
}
static inline u32 ce_intr_status_launcherr_pending_f(void)
{
return 0x4U;
}
static inline u32 ce_intr_status_launcherr_reset_f(void)
{
return 0x4U;
}
#define ce_intr_status_r(i)\
(nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32((i), 128U)))
#define ce_intr_status_blockpipe_pending_f() (0x1U)
#define ce_intr_status_blockpipe_reset_f() (0x1U)
#define ce_intr_status_nonblockpipe_pending_f() (0x2U)
#define ce_intr_status_nonblockpipe_reset_f() (0x2U)
#define ce_intr_status_launcherr_pending_f() (0x4U)
#define ce_intr_status_launcherr_reset_f() (0x4U)
#endif

578
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,440 +59,144 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ctxsw_prog_fecs_header_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_gpccs_header_stride_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
{
return 0x00000008U;
}
static inline u32 ctxsw_prog_main_image_patch_count_o(void)
{
return 0x00000010U;
}
static inline u32 ctxsw_prog_main_image_context_id_o(void)
{
return 0x000000f0U;
}
static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
{
return 0x00000014U;
}
static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
{
return 0x00000018U;
}
static inline u32 ctxsw_prog_main_image_zcull_o(void)
{
return 0x0000001cU;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
{
return 0x00000001U;
}
static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
{
return 0x00000002U;
}
static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
{
return 0x00000020U;
}
static inline u32 ctxsw_prog_main_image_pm_o(void)
{
return 0x00000028U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
{
return U32(0x7U) << 0U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
{
return U32(0x7U) << 3U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
{
return 0x8U;
}
static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
{
return 0x0000002cU;
}
static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
{
return 0x000000f4U;
}
static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
{
return 0x000000d0U;
}
static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
{
return 0x000000d4U;
}
static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
{
return 0x000000d8U;
}
static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
{
return 0x000000dcU;
}
static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
{
return 0x000000f8U;
}
static inline u32 ctxsw_prog_main_image_magic_value_o(void)
{
return 0x000000fcU;
}
static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
{
return 0x600dc0deU;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
{
return 0x000000f4U;
}
static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
{
return (r >> 16U) & 0xffffU;
}
static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
{
return 0x000000f8U;
}
static inline u32 ctxsw_prog_local_magic_value_o(void)
{
return 0x000000fcU;
}
static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
{
return 0xad0becabU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
{
return 0x000000ecU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
{
return 0x00000100U;
}
static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
{
return 0x00000000U;
}
static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
{
return 0x00000002U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
{
return 0x000000a0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
{
return 2U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
{
return 0x2U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
{
return 0x000000a4U;
}
static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
{
return 0x000000a8U;
}
static inline u32 ctxsw_prog_main_image_misc_options_o(void)
{
return 0x0000003cU;
}
static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_pmu_options_o(void)
{
return 0x00000070U;
}
static inline u32 ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
{
return 0x00000080U;
}
static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
{
return 0x00000068U;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
{
return 0x00000084U;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
{
return 0x2U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
{
return 0x000000acU;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
{
return 0x000000b0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
{
return U32(0xfffffffU) << 0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
{
return U32(0x3U) << 28U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
{
return 0x20000000U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
{
return 0x30000000U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
{
return 0x000000b4U;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
{
return 0x00000080U;
}
static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
{
return 0x00000020U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
{
return 0x00000000U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
{
return 0x00000000U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
{
return 0x600dbeefU;
}
static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
{
return 0x00000008U;
}
static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
{
return 0x00000018U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
{
return 0x0000001cU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
{
return (r >> 0U) & 0xffffffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
{
return U32(0xffU) << 24U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
{
return (r >> 24U) & 0xffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
{
return 0x00000001U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
{
return 0x1000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
{
return 0x00000002U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
{
return 0x2000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
{
return 0x0000000aU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
{
return 0xa000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
{
return 0x0000000bU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
{
return 0xb000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
{
return 0x0000000cU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
{
return 0xc000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
{
return 0x0000000dU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
{
return 0xd000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
{
return 0x00000003U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
{
return 0x3000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
{
return 0x00000004U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
{
return 0x4000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
{
return 0x00000005U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
{
return 0x5000000U;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
{
return 0x000000ffU;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
{
return 0xff000000U;
}
#define ctxsw_prog_fecs_header_v() (0x00000100U)
#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U)
#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U)
#define ctxsw_prog_main_image_patch_count_o() (0x00000010U)
#define ctxsw_prog_main_image_context_id_o() (0x000000f0U)
#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U)
#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U)
#define ctxsw_prog_main_image_zcull_o() (0x0000001cU)
#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U)
#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U)
#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U)
#define ctxsw_prog_main_image_pm_o() (0x00000028U)
#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U)
#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U)
#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U)
#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U)
#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U)
#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U)
#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU)
#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U)
#define ctxsw_prog_main_image_num_wfi_save_ops_o() (0x000000d0U)
#define ctxsw_prog_main_image_num_cta_save_ops_o() (0x000000d4U)
#define ctxsw_prog_main_image_num_gfxp_save_ops_o() (0x000000d8U)
#define ctxsw_prog_main_image_num_cilp_save_ops_o() (0x000000dcU)
#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U)
#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU)
#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU)
#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU)
#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U)
#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU)
#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U)
#define ctxsw_prog_local_magic_value_o() (0x000000fcU)
#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU)
#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU)
#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU)
#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U)
#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U)
#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\
(0x00000000U)
#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\
(0x00000002U)
#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\
(((v)&0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\
(((r) >> 0U) & 0x3U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U)
#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U)
#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U)
#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU)
#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U)
#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U)
#define ctxsw_prog_main_image_pmu_options_o() (0x00000070U)
#define ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(v)\
(((v)&0x1U) << 0U)
#define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U)
#define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\
(((v)&0x3U) << 0U)
#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\
(0x1U)
#define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U)
#define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U)
#define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\
(((v)&0x3U) << 0U)
#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U)
#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\
(((v)&0xffffU) << 0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\
(U32(0xfffffffU) << 0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m()\
(U32(0x3U) << 28U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f()\
(0x0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f()\
(0x20000000U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f()\
(0x30000000U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\
(((v)&0xffffffffU) << 0U)
#define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U)
#define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U)
#define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U)
#define ctxsw_prog_record_timestamp_magic_value_lo_v_value_v() (0x00000000U)
#define ctxsw_prog_record_timestamp_magic_value_hi_o() (0x00000004U)
#define ctxsw_prog_record_timestamp_magic_value_hi_v_value_v() (0x600dbeefU)
#define ctxsw_prog_record_timestamp_context_id_o() (0x00000008U)
#define ctxsw_prog_record_timestamp_context_ptr_o() (0x0000000cU)
#define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U)
#define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v) (((v)&0xffffffU) << 0U)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\
(((r) >> 0U) & 0xffffffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v) (((v)&0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\
(0x00000001U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f()\
(0x1000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v() (0x00000002U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f() (0x2000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v()\
(0x0000000aU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f() (0xa000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v()\
(0x0000000bU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f()\
(0xb000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v()\
(0x0000000cU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f()\
(0xc000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v()\
(0x0000000dU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f()\
(0xd000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v() (0x00000003U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f() (0x3000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v()\
(0x00000004U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f()\
(0x4000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v()\
(0x00000005U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f()\
(0x5000000U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v()\
(0x000000ffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f()\
(0xff000000U)
#endif

687
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,548 +59,145 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 falcon_falcon_irqsset_r(void)
{
return 0x00000000U;
}
static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
{
return 0x40U;
}
static inline u32 falcon_falcon_irqsclr_r(void)
{
return 0x00000004U;
}
static inline u32 falcon_falcon_irqstat_r(void)
{
return 0x00000008U;
}
static inline u32 falcon_falcon_irqstat_halt_true_f(void)
{
return 0x10U;
}
static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
{
return 0x20U;
}
static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
{
return 0x40U;
}
static inline u32 falcon_falcon_irqmode_r(void)
{
return 0x0000000cU;
}
static inline u32 falcon_falcon_irqmset_r(void)
{
return 0x00000010U;
}
static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqmclr_r(void)
{
return 0x00000014U;
}
static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_irqmask_r(void)
{
return 0x00000018U;
}
static inline u32 falcon_falcon_irqdest_r(void)
{
return 0x0000001cU;
}
static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
{
return (v & 0x1U) << 7U;
}
static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
{
return (v & 0x1U) << 17U;
}
static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
{
return (v & 0x1U) << 18U;
}
static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
{
return (v & 0x1U) << 19U;
}
static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
{
return (v & 0x1U) << 20U;
}
static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
{
return (v & 0x1U) << 21U;
}
static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
{
return (v & 0x1U) << 22U;
}
static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
{
return (v & 0x1U) << 23U;
}
static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 falcon_falcon_curctx_r(void)
{
return 0x00000050U;
}
static inline u32 falcon_falcon_nxtctx_r(void)
{
return 0x00000054U;
}
static inline u32 falcon_falcon_mailbox0_r(void)
{
return 0x00000040U;
}
static inline u32 falcon_falcon_mailbox1_r(void)
{
return 0x00000044U;
}
static inline u32 falcon_falcon_itfen_r(void)
{
return 0x00000048U;
}
static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
{
return 0x1U;
}
static inline u32 falcon_falcon_idlestate_r(void)
{
return 0x0000004cU;
}
static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
{
return (r >> 1U) & 0x7fffU;
}
static inline u32 falcon_falcon_os_r(void)
{
return 0x00000080U;
}
static inline u32 falcon_falcon_engctl_r(void)
{
return 0x000000a4U;
}
static inline u32 falcon_falcon_cpuctl_r(void)
{
return 0x00000100U;
}
static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v)
{
return (v & 0x1U) << 3U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 falcon_falcon_cpuctl_stopped_m(void)
{
return U32(0x1U) << 5U;
}
static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
{
return (r >> 6U) & 0x1U;
}
static inline u32 falcon_falcon_cpuctl_alias_r(void)
{
return 0x00000130U;
}
static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v)
{
return (v & 0x1U) << 1U;
}
static inline u32 falcon_falcon_imemc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_imemc_offs_f(u32 v)
{
return (v & 0x3fU) << 2U;
}
static inline u32 falcon_falcon_imemc_blk_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 falcon_falcon_imemc_secure_f(u32 v)
{
return (v & 0x1U) << 28U;
}
static inline u32 falcon_falcon_imemd_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_imemt_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 falcon_falcon_sctl_r(void)
{
return 0x00000240U;
}
static inline u32 falcon_falcon_mmu_phys_sec_r(void)
{
return 0x00100ce4U;
}
static inline u32 falcon_falcon_bootvec_r(void)
{
return 0x00000104U;
}
static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 falcon_falcon_dmactl_r(void)
{
return 0x0000010cU;
}
static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 falcon_falcon_hwcfg_r(void)
{
return 0x00000108U;
}
static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
{
return (r >> 0U) & 0x1ffU;
}
static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
{
return (r >> 9U) & 0x1ffU;
}
static inline u32 falcon_falcon_dmatrfbase_r(void)
{
return 0x00000110U;
}
static inline u32 falcon_falcon_dmatrfbase1_r(void)
{
return 0x00000128U;
}
static inline u32 falcon_falcon_dmatrfmoffs_r(void)
{
return 0x00000114U;
}
static inline u32 falcon_falcon_imctl_debug_r(void)
{
return 0x0000015cU;
}
static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v)
{
return (v & 0xffffffU) << 0U;
}
static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v)
{
return (v & 0x7U) << 24U;
}
static inline u32 falcon_falcon_imstat_r(void)
{
return 0x00000144U;
}
static inline u32 falcon_falcon_traceidx_r(void)
{
return 0x00000148U;
}
static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 falcon_falcon_traceidx_idx_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 falcon_falcon_tracepc_r(void)
{
return 0x0000014cU;
}
static inline u32 falcon_falcon_tracepc_pc_v(u32 r)
{
return (r >> 0U) & 0xffffffU;
}
static inline u32 falcon_falcon_dmatrfcmd_r(void)
{
return 0x00000118U;
}
static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
{
return (v & 0x7U) << 8U;
}
static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
{
return (v & 0x7U) << 12U;
}
static inline u32 falcon_falcon_dmatrffboffs_r(void)
{
return 0x0000011cU;
}
static inline u32 falcon_falcon_exterraddr_r(void)
{
return 0x00000168U;
}
static inline u32 falcon_falcon_exterrstat_r(void)
{
return 0x0000016cU;
}
static inline u32 falcon_falcon_exterrstat_valid_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
{
return 0x00000001U;
}
static inline u32 falcon_falcon_icd_cmd_r(void)
{
return 0x00000200U;
}
static inline u32 falcon_falcon_icd_cmd_opc_s(void)
{
return 4U;
}
static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 falcon_falcon_icd_cmd_opc_m(void)
{
return U32(0xfU) << 0U;
}
static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
{
return 0x8U;
}
static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
{
return 0xeU;
}
static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
{
return (v & 0x1fU) << 8U;
}
static inline u32 falcon_falcon_icd_rdata_r(void)
{
return 0x0000020cU;
}
static inline u32 falcon_falcon_dmemc_r(u32 i)
{
return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
{
return (v & 0x3fU) << 2U;
}
static inline u32 falcon_falcon_dmemc_offs_m(void)
{
return U32(0x3fU) << 2U;
}
static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
{
return (v & 0xffU) << 8U;
}
static inline u32 falcon_falcon_dmemc_blk_m(void)
{
return U32(0xffU) << 8U;
}
static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
{
return (v & 0x1U) << 25U;
}
static inline u32 falcon_falcon_dmemd_r(u32 i)
{
return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 falcon_falcon_debug1_r(void)
{
return 0x00000090U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
{
return 1U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
{
return (v & 0x1U) << 16U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
{
return 0x0U;
}
static inline u32 falcon_falcon_debuginfo_r(void)
{
return 0x00000094U;
}
#define falcon_falcon_irqsset_r() (0x00000000U)
#define falcon_falcon_irqsset_swgen0_set_f() (0x40U)
#define falcon_falcon_irqsclr_r() (0x00000004U)
#define falcon_falcon_irqstat_r() (0x00000008U)
#define falcon_falcon_irqstat_halt_true_f() (0x10U)
#define falcon_falcon_irqstat_exterr_true_f() (0x20U)
#define falcon_falcon_irqstat_swgen0_true_f() (0x40U)
#define falcon_falcon_irqmode_r() (0x0000000cU)
#define falcon_falcon_irqmset_r() (0x00000010U)
#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqmclr_r() (0x00000014U)
#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_irqmask_r() (0x00000018U)
#define falcon_falcon_irqdest_r() (0x0000001cU)
#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U)
#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U)
#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U)
#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U)
#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U)
#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U)
#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U)
#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U)
#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U)
#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U)
#define falcon_falcon_curctx_r() (0x00000050U)
#define falcon_falcon_nxtctx_r() (0x00000054U)
#define falcon_falcon_mailbox0_r() (0x00000040U)
#define falcon_falcon_mailbox1_r() (0x00000044U)
#define falcon_falcon_itfen_r() (0x00000048U)
#define falcon_falcon_itfen_ctxen_enable_f() (0x1U)
#define falcon_falcon_idlestate_r() (0x0000004cU)
#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U)
#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU)
#define falcon_falcon_os_r() (0x00000080U)
#define falcon_falcon_engctl_r() (0x000000a4U)
#define falcon_falcon_cpuctl_r() (0x00000100U)
#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U)
#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U)
#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define falcon_falcon_cpuctl_alias_r() (0x00000130U)
#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U)
#define falcon_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U)
#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U)
#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U)
#define falcon_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemt_r(i)\
(nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_sctl_r() (0x00000240U)
#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define falcon_falcon_bootvec_r() (0x00000104U)
#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U)
#define falcon_falcon_dmactl_r() (0x0000010cU)
#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U)
#define falcon_falcon_hwcfg_r() (0x00000108U)
#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
#define falcon_falcon_dmatrfbase_r() (0x00000110U)
#define falcon_falcon_dmatrfbase1_r() (0x00000128U)
#define falcon_falcon_dmatrfmoffs_r() (0x00000114U)
#define falcon_falcon_imctl_debug_r() (0x0000015cU)
#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U)
#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U)
#define falcon_falcon_imstat_r() (0x00000144U)
#define falcon_falcon_traceidx_r() (0x00000148U)
#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU)
#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U)
#define falcon_falcon_tracepc_r() (0x0000014cU)
#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU)
#define falcon_falcon_dmatrfcmd_r() (0x00000118U)
#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U)
#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U)
#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U)
#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U)
#define falcon_falcon_dmatrffboffs_r() (0x0000011cU)
#define falcon_falcon_exterraddr_r() (0x0010a168U)
#define falcon_falcon_exterrstat_r() (0x0010a16cU)
#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U)
#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U)
#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U)
#define falcon_falcon_icd_cmd_r() (0x00000200U)
#define falcon_falcon_icd_cmd_opc_s() (4U)
#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U)
#define falcon_falcon_icd_rdata_r() (0x0000020cU)
#define falcon_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U)
#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U)
#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U)
#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U)
#define falcon_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_debug1_r() (0x00000090U)
#define falcon_falcon_debug1_ctxsw_mode_s() (1U)
#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U)
#define falcon_falcon_debuginfo_r() (0x00000094U)
#endif

507
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,408 +59,105 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fb_fbhub_num_active_ltcs_r(void)
{
return 0x00100800U;
}
static inline u32 fb_mmu_ctrl_r(void)
{
return 0x00100c80U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 fb_priv_mmu_phy_secure_r(void)
{
return 0x00100ce4U;
}
static inline u32 fb_mmu_invalidate_pdb_r(void)
{
return 0x00100cb8U;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_invalidate_r(void)
{
return 0x00100cbcU;
}
static inline u32 fb_mmu_invalidate_all_va_true_f(void)
{
return 0x1U;
}
static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
{
return 1U;
}
static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
{
return (v & 0x1U) << 2U;
}
static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
{
return 0x4U;
}
static inline u32 fb_mmu_invalidate_replay_s(void)
{
return 3U;
}
static inline u32 fb_mmu_invalidate_replay_f(u32 v)
{
return (v & 0x7U) << 3U;
}
static inline u32 fb_mmu_invalidate_replay_m(void)
{
return U32(0x7U) << 3U;
}
static inline u32 fb_mmu_invalidate_replay_v(u32 r)
{
return (r >> 3U) & 0x7U;
}
static inline u32 fb_mmu_invalidate_replay_none_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_replay_start_f(void)
{
return 0x8U;
}
static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
{
return 0x10U;
}
static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
{
return 0x18U;
}
static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
{
return 0x20U;
}
static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
{
return 0x20U;
}
static inline u32 fb_mmu_invalidate_sys_membar_s(void)
{
return 1U;
}
static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
{
return (v & 0x1U) << 6U;
}
static inline u32 fb_mmu_invalidate_sys_membar_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
{
return (r >> 6U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
{
return 0x40U;
}
static inline u32 fb_mmu_invalidate_ack_s(void)
{
return 2U;
}
static inline u32 fb_mmu_invalidate_ack_f(u32 v)
{
return (v & 0x3U) << 7U;
}
static inline u32 fb_mmu_invalidate_ack_m(void)
{
return U32(0x3U) << 7U;
}
static inline u32 fb_mmu_invalidate_ack_v(u32 r)
{
return (r >> 7U) & 0x3U;
}
static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
{
return 0x100U;
}
static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
{
return 0x80U;
}
static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
{
return 6U;
}
static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
{
return (v & 0x3fU) << 9U;
}
static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
{
return U32(0x3fU) << 9U;
}
static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
{
return (r >> 9U) & 0x3fU;
}
static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
{
return 5U;
}
static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
{
return (v & 0x1fU) << 15U;
}
static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
{
return U32(0x1fU) << 15U;
}
static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
{
return (r >> 15U) & 0x1fU;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
{
return 1U;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
{
return (v & 0x1U) << 20U;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
{
return U32(0x1U) << 20U;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
{
return (r >> 20U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
{
return 0x100000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
{
return 3U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
{
return (v & 0x7U) << 24U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
{
return U32(0x7U) << 24U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
{
return (r >> 24U) & 0x7U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
{
return 0x1000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
{
return 0x2000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
{
return 0x3000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
{
return 0x4000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
{
return 0x5000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
{
return 0x6000000U;
}
static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
{
return 0x7000000U;
}
static inline u32 fb_mmu_invalidate_trigger_s(void)
{
return 1U;
}
static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 fb_mmu_invalidate_trigger_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 fb_mmu_invalidate_trigger_true_f(void)
{
return 0x80000000U;
}
static inline u32 fb_mmu_debug_wr_r(void)
{
return 0x00100cc8U;
}
static inline u32 fb_mmu_debug_wr_aperture_s(void)
{
return 2U;
}
static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
{
return (v & 0x3U) << 0U;
}
static inline u32 fb_mmu_debug_wr_aperture_m(void)
{
return U32(0x3U) << 0U;
}
static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
{
return (r >> 0U) & 0x3U;
}
static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 fb_mmu_debug_wr_vol_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_wr_vol_true_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_debug_wr_vol_true_f(void)
{
return 0x4U;
}
static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
{
return 0x0000000cU;
}
static inline u32 fb_mmu_debug_rd_r(void)
{
return 0x00100cccU;
}
static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 fb_mmu_debug_rd_vol_false_f(void)
{
return 0x0U;
}
static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
{
return 0x0000000cU;
}
static inline u32 fb_mmu_debug_ctrl_r(void)
{
return 0x00100cc4U;
}
static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 fb_mmu_debug_ctrl_debug_m(void)
{
return U32(0x1U) << 16U;
}
static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_vpr_info_r(void)
{
return 0x00100cd0U;
}
static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
{
return 0x00000000U;
}
static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
{
return 0x00000001U;
}
static inline u32 fb_niso_flush_sysmem_addr_r(void)
{
return 0x00100c10U;
}
#define fb_fbhub_num_active_ltcs_r() (0x00100800U)
#define fb_mmu_ctrl_r() (0x00100c80U)
#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U)
#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U)
#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU)
#define fb_priv_mmu_phy_secure_r() (0x00100ce4U)
#define fb_mmu_invalidate_pdb_r() (0x00100cb8U)
#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U)
#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U)
#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_invalidate_r() (0x00100cbcU)
#define fb_mmu_invalidate_all_va_true_f() (0x1U)
#define fb_mmu_invalidate_all_pdb_true_f() (0x2U)
#define fb_mmu_invalidate_hubtlb_only_s() (1U)
#define fb_mmu_invalidate_hubtlb_only_f(v) (((v)&0x1U) << 2U)
#define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U)
#define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U)
#define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U)
#define fb_mmu_invalidate_replay_s() (3U)
#define fb_mmu_invalidate_replay_f(v) (((v)&0x7U) << 3U)
#define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U)
#define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U)
#define fb_mmu_invalidate_replay_none_f() (0x0U)
#define fb_mmu_invalidate_replay_start_f() (0x8U)
#define fb_mmu_invalidate_replay_start_ack_all_f() (0x10U)
#define fb_mmu_invalidate_replay_cancel_targeted_f() (0x18U)
#define fb_mmu_invalidate_replay_cancel_global_f() (0x20U)
#define fb_mmu_invalidate_replay_cancel_f() (0x20U)
#define fb_mmu_invalidate_sys_membar_s() (1U)
#define fb_mmu_invalidate_sys_membar_f(v) (((v)&0x1U) << 6U)
#define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U)
#define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U)
#define fb_mmu_invalidate_sys_membar_true_f() (0x40U)
#define fb_mmu_invalidate_ack_s() (2U)
#define fb_mmu_invalidate_ack_f(v) (((v)&0x3U) << 7U)
#define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U)
#define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U)
#define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U)
#define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U)
#define fb_mmu_invalidate_ack_ack_globally_f() (0x80U)
#define fb_mmu_invalidate_cancel_client_id_s() (6U)
#define fb_mmu_invalidate_cancel_client_id_f(v) (((v)&0x3fU) << 9U)
#define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U)
#define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU)
#define fb_mmu_invalidate_cancel_gpc_id_s() (5U)
#define fb_mmu_invalidate_cancel_gpc_id_f(v) (((v)&0x1fU) << 15U)
#define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U)
#define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU)
#define fb_mmu_invalidate_cancel_client_type_s() (1U)
#define fb_mmu_invalidate_cancel_client_type_f(v) (((v)&0x1U) << 20U)
#define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U)
#define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U)
#define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U)
#define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U)
#define fb_mmu_invalidate_cancel_cache_level_s() (3U)
#define fb_mmu_invalidate_cancel_cache_level_f(v) (((v)&0x7U) << 24U)
#define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U)
#define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U)
#define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U)
#define fb_mmu_invalidate_cancel_cache_level_pte_only_f() (0x1000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f() (0x2000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f() (0x3000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f() (0x4000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f() (0x5000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U)
#define fb_mmu_invalidate_trigger_s() (1U)
#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U)
#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U)
#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_invalidate_trigger_true_f() (0x80000000U)
#define fb_mmu_debug_wr_r() (0x00100cc8U)
#define fb_mmu_debug_wr_aperture_s() (2U)
#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_wr_vol_false_f() (0x0U)
#define fb_mmu_debug_wr_vol_true_v() (0x00000001U)
#define fb_mmu_debug_wr_vol_true_f() (0x4U)
#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_rd_r() (0x00100cccU)
#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_rd_vol_false_f() (0x0U)
#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U)
#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_ctrl_r() (0x00100cc4U)
#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U)
#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U)
#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U)
#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U)
#define fb_mmu_vpr_info_r() (0x00100cd0U)
#define fb_mmu_vpr_info_fetch_v(r) (((r) >> 2U) & 0x1U)
#define fb_mmu_vpr_info_fetch_false_v() (0x00000000U)
#define fb_mmu_vpr_info_fetch_true_v() (0x00000001U)
#define fb_niso_flush_sysmem_addr_r() (0x00100c10U)
#endif

831
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,652 +59,185 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fifo_bar1_base_r(void)
{
return 0x00002254U;
}
static inline u32 fifo_bar1_base_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 fifo_bar1_base_valid_false_f(void)
{
return 0x0U;
}
static inline u32 fifo_bar1_base_valid_true_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_runlist_base_r(void)
{
return 0x00002270U;
}
static inline u32 fifo_runlist_base_ptr_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 fifo_runlist_base_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
{
return 0x20000000U;
}
static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 fifo_runlist_r(void)
{
return 0x00002274U;
}
static inline u32 fifo_runlist_engine_f(u32 v)
{
return (v & 0xfU) << 20U;
}
static inline u32 fifo_eng_runlist_base_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_eng_runlist_base__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_eng_runlist_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_eng_runlist__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_eng_runlist_length_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 fifo_eng_runlist_length_max_v(void)
{
return 0x0000ffffU;
}
static inline u32 fifo_eng_runlist_pending_true_f(void)
{
return 0x100000U;
}
static inline u32 fifo_pb_timeslice_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_pb_timeslice_timeout_16_f(void)
{
return 0x10U;
}
static inline u32 fifo_pb_timeslice_timescale_0_f(void)
{
return 0x0U;
}
static inline u32 fifo_pb_timeslice_enable_true_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_pbdma_map_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_intr_0_r(void)
{
return 0x00002100U;
}
static inline u32 fifo_intr_0_bind_error_pending_f(void)
{
return 0x1U;
}
static inline u32 fifo_intr_0_bind_error_reset_f(void)
{
return 0x1U;
}
static inline u32 fifo_intr_0_sched_error_pending_f(void)
{
return 0x100U;
}
static inline u32 fifo_intr_0_sched_error_reset_f(void)
{
return 0x100U;
}
static inline u32 fifo_intr_0_chsw_error_pending_f(void)
{
return 0x10000U;
}
static inline u32 fifo_intr_0_chsw_error_reset_f(void)
{
return 0x10000U;
}
static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
{
return 0x800000U;
}
static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
{
return 0x800000U;
}
static inline u32 fifo_intr_0_lb_error_pending_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_intr_0_lb_error_reset_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
{
return 0x2000000U;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
{
return 0x8000000U;
}
static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
{
return 0x8000000U;
}
static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
{
return 0x10000000U;
}
static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
{
return 0x20000000U;
}
static inline u32 fifo_intr_0_runlist_event_pending_f(void)
{
return 0x40000000U;
}
static inline u32 fifo_intr_0_channel_intr_pending_f(void)
{
return 0x80000000U;
}
static inline u32 fifo_intr_en_0_r(void)
{
return 0x00002140U;
}
static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
{
return (v & 0x1U) << 8U;
}
static inline u32 fifo_intr_en_0_sched_error_m(void)
{
return U32(0x1U) << 8U;
}
static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
{
return (v & 0x1U) << 28U;
}
static inline u32 fifo_intr_en_0_mmu_fault_m(void)
{
return U32(0x1U) << 28U;
}
static inline u32 fifo_intr_en_1_r(void)
{
return 0x00002528U;
}
static inline u32 fifo_intr_bind_error_r(void)
{
return 0x0000252cU;
}
static inline u32 fifo_intr_sched_error_r(void)
{
return 0x0000254cU;
}
static inline u32 fifo_intr_sched_error_code_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
{
return 0x0000000aU;
}
static inline u32 fifo_intr_chsw_error_r(void)
{
return 0x0000256cU;
}
static inline u32 fifo_intr_mmu_fault_id_r(void)
{
return 0x0000259cU;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
{
return 0x0U;
}
static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
{
return (r >> 0U) & 0xfffffffU;
}
static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
{
return nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32(i, 16U));
}
static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 fifo_intr_mmu_fault_info_access_type_v(u32 r)
{
return (r >> 16U) & 0x7U;
}
static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
{
return (r >> 20U) & 0x1U;
}
static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
{
return (r >> 8U) & 0x7fU;
}
static inline u32 fifo_intr_pbdma_id_r(void)
{
return 0x000025a0U;
}
static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
{
return (r >> (0U + i*1U)) & 0x1U;
}
static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_intr_runlist_r(void)
{
return 0x00002a00U;
}
static inline u32 fifo_fb_timeout_r(void)
{
return 0x00002a04U;
}
static inline u32 fifo_fb_timeout_period_m(void)
{
return U32(0x3fffffffU) << 0U;
}
static inline u32 fifo_fb_timeout_period_max_f(void)
{
return 0x3fffffffU;
}
static inline u32 fifo_error_sched_disable_r(void)
{
return 0x0000262cU;
}
static inline u32 fifo_sched_disable_r(void)
{
return 0x00002630U;
}
static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 fifo_sched_disable_runlist_m(u32 i)
{
return U32(0x1U) << (0U + i*1U);
}
static inline u32 fifo_sched_disable_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_preempt_r(void)
{
return 0x00002634U;
}
static inline u32 fifo_preempt_pending_true_f(void)
{
return 0x100000U;
}
static inline u32 fifo_preempt_type_channel_f(void)
{
return 0x0U;
}
static inline u32 fifo_preempt_type_tsg_f(void)
{
return 0x1000000U;
}
static inline u32 fifo_preempt_chid_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 fifo_preempt_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 fifo_trigger_mmu_fault_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
{
return (v & 0x1fU) << 0U;
}
static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
{
return (v & 0x1U) << 8U;
}
static inline u32 fifo_engine_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U));
}
static inline u32 fifo_engine_status__size_1_v(void)
{
return 0x00000002U;
}
static inline u32 fifo_engine_status_id_v(u32 r)
{
return (r >> 0U) & 0xfffU;
}
static inline u32 fifo_engine_status_id_type_v(u32 r)
{
return (r >> 12U) & 0x1U;
}
static inline u32 fifo_engine_status_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctx_status_v(u32 r)
{
return (r >> 13U) & 0x7U;
}
static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_ctx_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
{
return 0x00000005U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
{
return 0x00000006U;
}
static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
{
return 0x00000007U;
}
static inline u32 fifo_engine_status_next_id_v(u32 r)
{
return (r >> 16U) & 0xfffU;
}
static inline u32 fifo_engine_status_next_id_type_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 fifo_engine_status_next_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_next_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_faulted_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 fifo_engine_status_faulted_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_engine_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 fifo_engine_status_engine_idle_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_engine_status_engine_busy_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctxsw_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
{
return 0x8000U;
}
static inline u32 fifo_pbdma_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fifo_pbdma_status__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_id_v(u32 r)
{
return (r >> 0U) & 0xfffU;
}
static inline u32 fifo_pbdma_status_id_type_v(u32 r)
{
return (r >> 12U) & 0x1U;
}
static inline u32 fifo_pbdma_status_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
{
return (r >> 13U) & 0x7U;
}
static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
{
return 0x00000005U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
{
return 0x00000006U;
}
static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
{
return 0x00000007U;
}
static inline u32 fifo_pbdma_status_next_id_v(u32 r)
{
return (r >> 16U) & 0xfffU;
}
static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_pbdma_status_chsw_v(u32 r)
{
return (r >> 15U) & 0x1U;
}
static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_lo_r(void)
{
return 0x00002a70U;
}
static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v)
{
return (v & 0xfffffU) << 12U;
}
static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_hi_r(void)
{
return 0x00002a74U;
}
static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_size_r(void)
{
return 0x00002a78U;
}
static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
{
return (v & 0x1ffU) << 0U;
}
static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
{
return 0x000000c0U;
}
static inline u32 fifo_replay_fault_buffer_get_r(void)
{
return 0x00002a7cU;
}
static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
{
return (v & 0x1ffU) << 0U;
}
static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_put_r(void)
{
return 0x00002a80U;
}
static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
{
return (v & 0x1ffU) << 0U;
}
static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_info_r(void)
{
return 0x00002a84U;
}
static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v)
{
return (v & 0x1U) << 24U;
}
static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v)
{
return (v & 0x1U) << 28U;
}
static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void)
{
return 0x00000000U;
}
static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void)
{
return 0x00000001U;
}
static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void)
{
return 0x00000001U;
}
#define fifo_bar1_base_r() (0x00002254U)
#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU)
#define fifo_bar1_base_valid_false_f() (0x0U)
#define fifo_bar1_base_valid_true_f() (0x10000000U)
#define fifo_runlist_base_r() (0x00002270U)
#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U)
#define fifo_runlist_base_target_vid_mem_f() (0x0U)
#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U)
#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U)
#define fifo_runlist_r() (0x00002274U)
#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U)
#define fifo_eng_runlist_base_r(i)\
(nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist_base__size_1_v() (0x00000001U)
#define fifo_eng_runlist_r(i)\
(nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist__size_1_v() (0x00000001U)
#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U)
#define fifo_eng_runlist_length_max_v() (0x0000ffffU)
#define fifo_eng_runlist_pending_true_f() (0x100000U)
#define fifo_pb_timeslice_r(i)\
(nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_pb_timeslice_timeout_16_f() (0x10U)
#define fifo_pb_timeslice_timescale_0_f() (0x0U)
#define fifo_pb_timeslice_enable_true_f() (0x10000000U)
#define fifo_pbdma_map_r(i)\
(nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_intr_0_r() (0x00002100U)
#define fifo_intr_0_bind_error_pending_f() (0x1U)
#define fifo_intr_0_bind_error_reset_f() (0x1U)
#define fifo_intr_0_sched_error_pending_f() (0x100U)
#define fifo_intr_0_sched_error_reset_f() (0x100U)
#define fifo_intr_0_chsw_error_pending_f() (0x10000U)
#define fifo_intr_0_chsw_error_reset_f() (0x10000U)
#define fifo_intr_0_fb_flush_timeout_pending_f() (0x800000U)
#define fifo_intr_0_fb_flush_timeout_reset_f() (0x800000U)
#define fifo_intr_0_lb_error_pending_f() (0x1000000U)
#define fifo_intr_0_lb_error_reset_f() (0x1000000U)
#define fifo_intr_0_replayable_fault_error_pending_f() (0x2000000U)
#define fifo_intr_0_dropped_mmu_fault_pending_f() (0x8000000U)
#define fifo_intr_0_dropped_mmu_fault_reset_f() (0x8000000U)
#define fifo_intr_0_mmu_fault_pending_f() (0x10000000U)
#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U)
#define fifo_intr_0_runlist_event_pending_f() (0x40000000U)
#define fifo_intr_0_channel_intr_pending_f() (0x80000000U)
#define fifo_intr_en_0_r() (0x00002140U)
#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U)
#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U)
#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U)
#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U)
#define fifo_intr_en_1_r() (0x00002528U)
#define fifo_intr_bind_error_r() (0x0000252cU)
#define fifo_intr_sched_error_r() (0x0000254cU)
#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U)
#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU)
#define fifo_intr_chsw_error_r() (0x0000256cU)
#define fifo_intr_mmu_fault_id_r() (0x0000259cU)
#define fifo_intr_mmu_fault_eng_id_graphics_v() (0x00000000U)
#define fifo_intr_mmu_fault_eng_id_graphics_f() (0x0U)
#define fifo_intr_mmu_fault_inst_r(i)\
(nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_inst_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define fifo_intr_mmu_fault_inst_ptr_align_shift_v() (0x0000000cU)
#define fifo_intr_mmu_fault_lo_r(i)\
(nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_hi_r(i)\
(nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_info_r(i)\
(nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32((i), 16U)))
#define fifo_intr_mmu_fault_info_type_v(r) (((r) >> 0U) & 0x1fU)
#define fifo_intr_mmu_fault_info_access_type_v(r) (((r) >> 16U) & 0x7U)
#define fifo_intr_mmu_fault_info_client_type_v(r) (((r) >> 20U) & 0x1U)
#define fifo_intr_mmu_fault_info_client_type_gpc_v() (0x00000000U)
#define fifo_intr_mmu_fault_info_client_type_hub_v() (0x00000001U)
#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU)
#define fifo_intr_pbdma_id_r() (0x000025a0U)
#define fifo_intr_pbdma_id_status_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define fifo_intr_pbdma_id_status_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U)
#define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U)
#define fifo_intr_runlist_r() (0x00002a00U)
#define fifo_fb_timeout_r() (0x00002a04U)
#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U)
#define fifo_fb_timeout_period_max_f() (0x3fffffffU)
#define fifo_error_sched_disable_r() (0x0000262cU)
#define fifo_sched_disable_r() (0x00002630U)
#define fifo_sched_disable_runlist_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define fifo_sched_disable_runlist_m(i)\
(U32(0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_true_v() (0x00000001U)
#define fifo_preempt_r() (0x00002634U)
#define fifo_preempt_pending_true_f() (0x100000U)
#define fifo_preempt_type_channel_f() (0x0U)
#define fifo_preempt_type_tsg_f() (0x1000000U)
#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U)
#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U)
#define fifo_trigger_mmu_fault_r(i)\
(nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U)
#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U)
#define fifo_engine_status_r(i)\
(nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_engine_status__size_1_v() (0x00000002U)
#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU)
#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U)
#define fifo_engine_status_id_type_chid_v() (0x00000000U)
#define fifo_engine_status_id_type_tsgid_v() (0x00000001U)
#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U)
#define fifo_engine_status_ctx_status_invalid_v() (0x00000000U)
#define fifo_engine_status_ctx_status_valid_v() (0x00000001U)
#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U)
#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U)
#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U)
#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU)
#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U)
#define fifo_engine_status_next_id_type_chid_v() (0x00000000U)
#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U)
#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U)
#define fifo_engine_status_faulted_true_v() (0x00000001U)
#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U)
#define fifo_engine_status_engine_idle_v() (0x00000000U)
#define fifo_engine_status_engine_busy_v() (0x00000001U)
#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U)
#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U)
#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U)
#define fifo_pbdma_status_r(i)\
(nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_pbdma_status__size_1_v() (0x00000001U)
#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU)
#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U)
#define fifo_pbdma_status_id_type_chid_v() (0x00000000U)
#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U)
#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U)
#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U)
#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U)
#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U)
#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U)
#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU)
#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U)
#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U)
#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U)
#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U)
#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U)
#define fifo_replay_fault_buffer_lo_r() (0x00002a70U)
#define fifo_replay_fault_buffer_lo_enable_v(r) (((r) >> 0U) & 0x1U)
#define fifo_replay_fault_buffer_lo_enable_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_lo_enable_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_lo_base_f(v) (((v)&0xfffffU) << 12U)
#define fifo_replay_fault_buffer_lo_base_reset_v() (0x00000000U)
#define fifo_replay_fault_buffer_hi_r() (0x00002a74U)
#define fifo_replay_fault_buffer_hi_base_f(v) (((v)&0xffU) << 0U)
#define fifo_replay_fault_buffer_hi_base_reset_v() (0x00000000U)
#define fifo_replay_fault_buffer_size_r() (0x00002a78U)
#define fifo_replay_fault_buffer_size_hw_f(v) (((v)&0x1ffU) << 0U)
#define fifo_replay_fault_buffer_size_hw_entries_v() (0x000000c0U)
#define fifo_replay_fault_buffer_get_r() (0x00002a7cU)
#define fifo_replay_fault_buffer_get_offset_hw_f(v) (((v)&0x1ffU) << 0U)
#define fifo_replay_fault_buffer_get_offset_hw_init_v() (0x00000000U)
#define fifo_replay_fault_buffer_put_r() (0x00002a80U)
#define fifo_replay_fault_buffer_put_offset_hw_f(v) (((v)&0x1ffU) << 0U)
#define fifo_replay_fault_buffer_put_offset_hw_init_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_r() (0x00002a84U)
#define fifo_replay_fault_buffer_info_overflow_f(v) (((v)&0x1U) << 0U)
#define fifo_replay_fault_buffer_info_overflow_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_overflow_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_overflow_clear_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_write_nack_f(v) (((v)&0x1U) << 24U)
#define fifo_replay_fault_buffer_info_write_nack_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_write_nack_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_write_nack_clear_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(v)\
(((v)&0x1U) << 28U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v()\
(0x00000000U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v()\
(0x00000001U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v()\
(0x00000001U)
#endif

162
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,132 +59,36 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 flush_l2_system_invalidate_r(void)
{
return 0x00070004U;
}
static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_flush_dirty_r(void)
{
return 0x00070010U;
}
static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_clean_comptags_r(void)
{
return 0x0007000cU;
}
static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
{
return 0x00000000U;
}
static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
{
return 0x0U;
}
static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
{
return 0x00000001U;
}
static inline u32 flush_fb_flush_r(void)
{
return 0x00070000U;
}
static inline u32 flush_fb_flush_pending_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 flush_fb_flush_pending_busy_v(void)
{
return 0x00000001U;
}
static inline u32 flush_fb_flush_pending_busy_f(void)
{
return 0x1U;
}
static inline u32 flush_fb_flush_outstanding_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 flush_fb_flush_outstanding_true_v(void)
{
return 0x00000001U;
}
#define flush_l2_system_invalidate_r() (0x00070004U)
#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U)
#define flush_l2_system_invalidate_pending_busy_f() (0x1U)
#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U)
#define flush_l2_flush_dirty_r() (0x00070010U)
#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U)
#define flush_l2_flush_dirty_pending_empty_f() (0x0U)
#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U)
#define flush_l2_flush_dirty_pending_busy_f() (0x1U)
#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U)
#define flush_l2_flush_dirty_outstanding_false_f() (0x0U)
#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U)
#define flush_l2_clean_comptags_r() (0x0007000cU)
#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U)
#define flush_l2_clean_comptags_pending_empty_f() (0x0U)
#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U)
#define flush_l2_clean_comptags_pending_busy_f() (0x1U)
#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U)
#define flush_l2_clean_comptags_outstanding_false_f() (0x0U)
#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U)
#define flush_fb_flush_r() (0x00070000U)
#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U)
#define flush_fb_flush_pending_busy_v() (0x00000001U)
#define flush_fb_flush_pending_busy_f() (0x1U)
#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U)
#define flush_fb_flush_outstanding_true_v() (0x00000001U)
#endif

126
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,100 +59,32 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 fuse_status_opt_gpc_r(void)
{
return 0x00021c1cU;
}
static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
{
return nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
{
return 0x00021944U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
{
return U32(0xffU) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
{
return 0x00021948U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
{
return 0x1U;
}
static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
{
return 0x0U;
}
static inline u32 fuse_status_opt_fbio_r(void)
{
return 0x00021c14U;
}
static inline u32 fuse_status_opt_fbio_data_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 fuse_status_opt_fbio_data_m(void)
{
return U32(0xffffU) << 0U;
}
static inline u32 fuse_status_opt_fbio_data_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
{
return nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 fuse_status_opt_fbp_r(void)
{
return 0x00021d38U;
}
static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
{
return (r >> (0U + i*1U)) & 0x1U;
}
static inline u32 fuse_opt_ecc_en_r(void)
{
return 0x00021228U;
}
static inline u32 fuse_opt_feature_fuses_override_disable_r(void)
{
return 0x000213f0U;
}
static inline u32 fuse_opt_sec_debug_en_r(void)
{
return 0x00021218U;
}
static inline u32 fuse_opt_priv_sec_en_r(void)
{
return 0x00021434U;
}
#define fuse_status_opt_gpc_r() (0x00021c1cU)
#define fuse_status_opt_tpc_gpc_r(i)\
(nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_tpc_gpc_r(i)\
(nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U)
#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0xffU) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0xffU) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0xffU)
#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U)
#define fuse_status_opt_fbio_r() (0x00021c14U)
#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U)
#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U)
#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU)
#define fuse_status_opt_rop_l2_fbp_r(i)\
(nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_status_opt_fbp_r() (0x00021d38U)
#define fuse_status_opt_fbp_idx_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U)
#define fuse_opt_ecc_en_r() (0x00021228U)
#define fuse_opt_feature_fuses_override_disable_r() (0x000213f0U)
#define fuse_opt_sec_debug_en_r() (0x00021218U)
#define fuse_opt_priv_sec_en_r() (0x00021434U)
#endif

342
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,276 +59,72 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 gmmu_new_pde_is_pte_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pde_is_pte_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pde_aperture_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pde_aperture_invalid_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
{
return 0x2U;
}
static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
{
return 0x4U;
}
static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
{
return 0x6U;
}
static inline u32 gmmu_new_pde_address_sys_f(u32 v)
{
return (v & 0xffffffU) << 8U;
}
static inline u32 gmmu_new_pde_address_sys_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pde_vol_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pde_vol_true_f(void)
{
return 0x8U;
}
static inline u32 gmmu_new_pde_vol_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pde_address_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 gmmu_new_pde__size_v(void)
{
return 0x00000008U;
}
static inline u32 gmmu_new_dual_pde_is_pte_w(void)
{
return 0U;
}
static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
{
return 0U;
}
static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
{
return 0x2U;
}
static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
{
return 0x4U;
}
static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
{
return 0x6U;
}
static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
{
return 0U;
}
static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
{
return 2U;
}
static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
{
return 0x2U;
}
static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
{
return 0x4U;
}
static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
{
return 0x6U;
}
static inline u32 gmmu_new_dual_pde_vol_small_w(void)
{
return 2U;
}
static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
{
return 0x8U;
}
static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_dual_pde_vol_big_w(void)
{
return 0U;
}
static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
{
return 0x8U;
}
static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
{
return (v & 0xffffffU) << 8U;
}
static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
{
return 2U;
}
static inline u32 gmmu_new_dual_pde_address_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
{
return 0x00000008U;
}
static inline u32 gmmu_new_dual_pde__size_v(void)
{
return 0x00000010U;
}
static inline u32 gmmu_new_pte__size_v(void)
{
return 0x00000008U;
}
static inline u32 gmmu_new_pte_valid_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_valid_true_f(void)
{
return 0x1U;
}
static inline u32 gmmu_new_pte_valid_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pte_privilege_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_privilege_true_f(void)
{
return 0x20U;
}
static inline u32 gmmu_new_pte_privilege_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pte_address_sys_f(u32 v)
{
return (v & 0xffffffU) << 8U;
}
static inline u32 gmmu_new_pte_address_sys_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_address_vid_f(u32 v)
{
return (v & 0xffffffU) << 8U;
}
static inline u32 gmmu_new_pte_address_vid_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_vol_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_vol_true_f(void)
{
return 0x8U;
}
static inline u32 gmmu_new_pte_vol_false_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pte_aperture_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
{
return 0x0U;
}
static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
{
return 0x4U;
}
static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
{
return 0x6U;
}
static inline u32 gmmu_new_pte_read_only_w(void)
{
return 0U;
}
static inline u32 gmmu_new_pte_read_only_true_f(void)
{
return 0x40U;
}
static inline u32 gmmu_new_pte_comptagline_f(u32 v)
{
return (v & 0x3ffffU) << 4U;
}
static inline u32 gmmu_new_pte_comptagline_w(void)
{
return 1U;
}
static inline u32 gmmu_new_pte_kind_f(u32 v)
{
return (v & 0xffU) << 24U;
}
static inline u32 gmmu_new_pte_kind_w(void)
{
return 1U;
}
static inline u32 gmmu_new_pte_address_shift_v(void)
{
return 0x0000000cU;
}
static inline u32 gmmu_pte_kind_f(u32 v)
{
return (v & 0xffU) << 4U;
}
static inline u32 gmmu_pte_kind_w(void)
{
return 1U;
}
static inline u32 gmmu_pte_kind_invalid_v(void)
{
return 0x000000ffU;
}
static inline u32 gmmu_pte_kind_pitch_v(void)
{
return 0x00000000U;
}
#define gmmu_new_pde_is_pte_w() (0U)
#define gmmu_new_pde_is_pte_false_f() (0x0U)
#define gmmu_new_pde_aperture_w() (0U)
#define gmmu_new_pde_aperture_invalid_f() (0x0U)
#define gmmu_new_pde_aperture_video_memory_f() (0x2U)
#define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U)
#define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_pde_address_sys_f(v) (((v)&0xffffffU) << 8U)
#define gmmu_new_pde_address_sys_w() (0U)
#define gmmu_new_pde_vol_w() (0U)
#define gmmu_new_pde_vol_true_f() (0x8U)
#define gmmu_new_pde_vol_false_f() (0x0U)
#define gmmu_new_pde_address_shift_v() (0x0000000cU)
#define gmmu_new_pde__size_v() (0x00000008U)
#define gmmu_new_dual_pde_is_pte_w() (0U)
#define gmmu_new_dual_pde_is_pte_false_f() (0x0U)
#define gmmu_new_dual_pde_aperture_big_w() (0U)
#define gmmu_new_dual_pde_aperture_big_invalid_f() (0x0U)
#define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U)
#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U)
#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_dual_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U)
#define gmmu_new_dual_pde_address_big_sys_w() (0U)
#define gmmu_new_dual_pde_aperture_small_w() (2U)
#define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U)
#define gmmu_new_dual_pde_aperture_small_video_memory_f() (0x2U)
#define gmmu_new_dual_pde_aperture_small_sys_mem_coh_f() (0x4U)
#define gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_dual_pde_vol_small_w() (2U)
#define gmmu_new_dual_pde_vol_small_true_f() (0x8U)
#define gmmu_new_dual_pde_vol_small_false_f() (0x0U)
#define gmmu_new_dual_pde_vol_big_w() (0U)
#define gmmu_new_dual_pde_vol_big_true_f() (0x8U)
#define gmmu_new_dual_pde_vol_big_false_f() (0x0U)
#define gmmu_new_dual_pde_address_small_sys_f(v) (((v)&0xffffffU) << 8U)
#define gmmu_new_dual_pde_address_small_sys_w() (2U)
#define gmmu_new_dual_pde_address_shift_v() (0x0000000cU)
#define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U)
#define gmmu_new_dual_pde__size_v() (0x00000010U)
#define gmmu_new_pte__size_v() (0x00000008U)
#define gmmu_new_pte_valid_w() (0U)
#define gmmu_new_pte_valid_true_f() (0x1U)
#define gmmu_new_pte_valid_false_f() (0x0U)
#define gmmu_new_pte_privilege_w() (0U)
#define gmmu_new_pte_privilege_true_f() (0x20U)
#define gmmu_new_pte_privilege_false_f() (0x0U)
#define gmmu_new_pte_address_sys_f(v) (((v)&0xffffffU) << 8U)
#define gmmu_new_pte_address_sys_w() (0U)
#define gmmu_new_pte_address_vid_f(v) (((v)&0xffffffU) << 8U)
#define gmmu_new_pte_address_vid_w() (0U)
#define gmmu_new_pte_vol_w() (0U)
#define gmmu_new_pte_vol_true_f() (0x8U)
#define gmmu_new_pte_vol_false_f() (0x0U)
#define gmmu_new_pte_aperture_w() (0U)
#define gmmu_new_pte_aperture_video_memory_f() (0x0U)
#define gmmu_new_pte_aperture_sys_mem_coh_f() (0x4U)
#define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_pte_read_only_w() (0U)
#define gmmu_new_pte_read_only_true_f() (0x40U)
#define gmmu_new_pte_comptagline_f(v) (((v)&0x3ffffU) << 4U)
#define gmmu_new_pte_comptagline_w() (1U)
#define gmmu_new_pte_kind_f(v) (((v)&0xffU) << 24U)
#define gmmu_new_pte_kind_w() (1U)
#define gmmu_new_pte_address_shift_v() (0x0000000cU)
#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U)
#define gmmu_pte_kind_w() (1U)
#define gmmu_pte_kind_invalid_v() (0x000000ffU)
#define gmmu_pte_kind_pitch_v() (0x00000000U)
#endif

5491
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
View File

File diff suppressed because it is too large Load Diff

628
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,484 +59,150 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 ltc_pltcg_base_v(void)
{
return 0x00140000U;
}
static inline u32 ltc_pltcg_extent_v(void)
{
return 0x0017ffffU;
}
static inline u32 ltc_ltc0_ltss_v(void)
{
return 0x00140200U;
}
static inline u32 ltc_ltc0_lts0_v(void)
{
return 0x00140400U;
}
static inline u32 ltc_ltcs_ltss_v(void)
{
return 0x0017e200U;
}
static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
{
return 0x0014046cU;
}
static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
{
return 0x00140518U;
}
static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
{
return 0x0017e318U;
}
static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
{
return U32(0x1U) << 15U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
{
return 0x00140494U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
{
return (r >> 16U) & 0x3U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
{
return 0x00000000U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
{
return 0x00000002U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
{
return 0x0017e26cU;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
{
return 0x2U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
{
return 0x4U;
}
static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
{
return 0x0014046cU;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
{
return 0x0017e270U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
{
return (v & 0x3ffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
{
return 0x0017e274U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
{
return (v & 0x3ffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
{
return 0x0003ffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
{
return 0x0017e278U;
}
static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
{
return 0x0000000bU;
}
static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
{
return (r >> 0U) & 0x3ffffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
{
return 0x0017e27cU;
}
static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
{
return 0x0017e000U;
}
static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
{
return 0x0017e280U;
}
static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
{
return (r >> 24U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
{
return (r >> 28U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
{
return 0x0017e3f4U;
}
static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
{
return 0x0017e2acU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
{
return (v & 0x1fU) << 16U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
{
return 0x0017e338U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
{
return (v & 0xfU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
{
return nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
{
return 0x00000004U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
{
return 0x0017e34cU;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
{
return 32U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
{
return (v & 0xffffffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
{
return (r >> 0U) & 0xffffffffU;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
{
return 0x0017e2b0U;
}
static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
{
return 0x0017e214U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
{
return 0x00140214U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_intr_r(void)
{
return 0x0017e20cU;
}
static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
{
return 0x100U;
}
static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
{
return 0x200U;
}
static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
{
return U32(0x1U) << 20U;
}
static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
{
return 0x1000000U;
}
static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
{
return 0x2000000U;
}
static inline u32 ltc_ltc0_lts0_intr_r(void)
{
return 0x0014040cU;
}
static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
{
return 0x0014051cU;
}
static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
{
return U32(0xffU) << 0U;
}
static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
{
return U32(0xffU) << 16U;
}
static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
{
return (r >> 16U) & 0xffU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
{
return 0x0017e2a0U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
{
return (r >> 8U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
{
return 0x00000003U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
{
return 0x300U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
{
return (r >> 29U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
{
return 0x20000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
{
return 0x40000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
{
return 0x0017e2a4U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
{
return (r >> 8U) & 0xfU;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
{
return 0x00000003U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
{
return 0x300U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
{
return (r >> 16U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
{
return 0x10000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
{
return 0x10000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
{
return (r >> 29U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
{
return 0x20000000U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
{
return 0x40000000U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
{
return 0x001402a0U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
{
return 0x001402a4U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
{
return 0x00000001U;
}
static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
{
return 0x1U;
}
static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
{
return 0x0014058cU;
}
static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
{
return (r >> 0U) & 0xffffU;
}
static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
{
return (r >> 16U) & 0x1fU;
}
static inline u32 ltc_ltca_g_axi_pctrl_r(void)
{
return 0x00160000U;
}
static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v)
{
return (v & 0xffU) << 2U;
}
#define ltc_pltcg_base_v() (0x00140000U)
#define ltc_pltcg_extent_v() (0x0017ffffU)
#define ltc_ltc0_ltss_v() (0x00140200U)
#define ltc_ltc0_lts0_v() (0x00140400U)
#define ltc_ltcs_ltss_v() (0x0017e200U)
#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x0014046cU)
#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00140518U)
#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017e318U)
#define ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m() (U32(0x1U) << 15U)
#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00140494U)
#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U)
#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U)
#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e26cU)
#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U)
#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U)
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U)
#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU)
#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U)
#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x3ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x3ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU)
#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U)
#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU)
#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU)
#define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU)
#define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U)
#define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U)
#define ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(r)\
(((r) >> 0U) & 0xffffU)
#define ltc_ltcs_ltss_cbc_param_cache_line_size_v(r) (((r) >> 24U) & 0xfU)
#define ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU)
#define ltc_ltcs_ltss_cbc_param2_r() (0x0017e3f4U)
#define ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(r)\
(((r) >> 0U) & 0xffffU)
#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU)
#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\
(((v)&0x1fU) << 16U)
#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
(nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U)))
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\
(((v)&0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\
(U32(0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\
(((r) >> 0U) & 0xffffffffU)
#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e2b0U)
#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U)
#define ltc_ltcs_ltss_g_elpg_r() (0x0017e214U)
#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U)
#define ltc_ltc0_ltss_g_elpg_r() (0x00140214U)
#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U)
#define ltc_ltcs_ltss_intr_r() (0x0017e20cU)
#define ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() (0x100U)
#define ltc_ltcs_ltss_intr_ecc_ded_error_pending_f() (0x200U)
#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U)
#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m() (U32(0x1U) << 30U)
#define ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() (0x1000000U)
#define ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f() (0x2000000U)
#define ltc_ltc0_lts0_intr_r() (0x0014040cU)
#define ltc_ltc0_lts0_dstg_ecc_report_r() (0x0014051cU)
#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_m() (U32(0xffU) << 0U)
#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(r) (((r) >> 0U) & 0xffU)
#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_m() (U32(0xffU) << 16U)
#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(r) (((r) >> 16U) & 0xffU)
#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\
(((r) >> 8U) & 0xfU)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\
(0x00000003U)
#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\
(((r) >> 28U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\
(0x10000000U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\
(((r) >> 29U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\
(0x20000000U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\
(((r) >> 30U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\
(0x40000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e2a4U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\
(((r) >> 8U) & 0xfU)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U)
#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\
(((r) >> 16U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\
(((r) >> 28U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\
(((r) >> 29U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\
(0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\
(0x20000000U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\
(((r) >> 30U) & 0x1U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U)
#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x001402a0U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x001402a4U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U)
#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U)
#define ltc_ltc0_lts0_tstg_info_1_r() (0x0014058cU)
#define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r) (((r) >> 0U) & 0xffffU)
#define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r) (((r) >> 16U) & 0x1fU)
#define ltc_ltca_g_axi_pctrl_r() (0x00160000U)
#define ltc_ltca_g_axi_pctrl_user_sid_f(v) (((v)&0xffU) << 2U)
#endif

252
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,200 +59,58 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 mc_boot_0_r(void)
{
return 0x00000000U;
}
static inline u32 mc_boot_0_architecture_v(u32 r)
{
return (r >> 24U) & 0x1fU;
}
static inline u32 mc_boot_0_implementation_v(u32 r)
{
return (r >> 20U) & 0xfU;
}
static inline u32 mc_boot_0_major_revision_v(u32 r)
{
return (r >> 4U) & 0xfU;
}
static inline u32 mc_boot_0_minor_revision_v(u32 r)
{
return (r >> 0U) & 0xfU;
}
static inline u32 mc_intr_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 mc_intr_pfifo_pending_f(void)
{
return 0x100U;
}
static inline u32 mc_intr_replayable_fault_pending_f(void)
{
return 0x200U;
}
static inline u32 mc_intr_pfb_pending_f(void)
{
return 0x2000U;
}
static inline u32 mc_intr_pgraph_pending_f(void)
{
return 0x1000U;
}
static inline u32 mc_intr_pmu_pending_f(void)
{
return 0x1000000U;
}
static inline u32 mc_intr_ltc_pending_f(void)
{
return 0x2000000U;
}
static inline u32 mc_intr_priv_ring_pending_f(void)
{
return 0x40000000U;
}
static inline u32 mc_intr_pbus_pending_f(void)
{
return 0x10000000U;
}
static inline u32 mc_intr_en_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 mc_intr_en_set_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 mc_intr_en_clear_r(u32 i)
{
return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 mc_enable_r(void)
{
return 0x00000200U;
}
static inline u32 mc_enable_xbar_enabled_f(void)
{
return 0x4U;
}
static inline u32 mc_enable_l2_enabled_f(void)
{
return 0x8U;
}
static inline u32 mc_enable_pmedia_s(void)
{
return 1U;
}
static inline u32 mc_enable_pmedia_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 mc_enable_pmedia_m(void)
{
return U32(0x1U) << 4U;
}
static inline u32 mc_enable_pmedia_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 mc_enable_priv_ring_enabled_f(void)
{
return 0x20U;
}
static inline u32 mc_enable_ce0_m(void)
{
return U32(0x1U) << 6U;
}
static inline u32 mc_enable_pfifo_enabled_f(void)
{
return 0x100U;
}
static inline u32 mc_enable_pgraph_enabled_f(void)
{
return 0x1000U;
}
static inline u32 mc_enable_pwr_v(u32 r)
{
return (r >> 13U) & 0x1U;
}
static inline u32 mc_enable_pwr_disabled_v(void)
{
return 0x00000000U;
}
static inline u32 mc_enable_pwr_enabled_f(void)
{
return 0x2000U;
}
static inline u32 mc_enable_pfb_enabled_f(void)
{
return 0x100000U;
}
static inline u32 mc_enable_ce2_m(void)
{
return U32(0x1U) << 21U;
}
static inline u32 mc_enable_ce2_enabled_f(void)
{
return 0x200000U;
}
static inline u32 mc_enable_blg_enabled_f(void)
{
return 0x8000000U;
}
static inline u32 mc_enable_perfmon_enabled_f(void)
{
return 0x10000000U;
}
static inline u32 mc_enable_hub_enabled_f(void)
{
return 0x20000000U;
}
static inline u32 mc_intr_ltc_r(void)
{
return 0x000001c0U;
}
static inline u32 mc_enable_pb_r(void)
{
return 0x00000204U;
}
static inline u32 mc_enable_pb_0_s(void)
{
return 1U;
}
static inline u32 mc_enable_pb_0_f(u32 v)
{
return (v & 0x1U) << 0U;
}
static inline u32 mc_enable_pb_0_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 mc_enable_pb_0_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 mc_enable_pb_0_enabled_v(void)
{
return 0x00000001U;
}
static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
{
return (v & 0x1U) << (0U + i*1U);
}
static inline u32 mc_elpg_enable_r(void)
{
return 0x0000020cU;
}
static inline u32 mc_elpg_enable_xbar_enabled_f(void)
{
return 0x4U;
}
static inline u32 mc_elpg_enable_pfb_enabled_f(void)
{
return 0x100000U;
}
static inline u32 mc_elpg_enable_hub_enabled_f(void)
{
return 0x20000000U;
}
#define mc_boot_0_r() (0x00000000U)
#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU)
#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU)
#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU)
#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU)
#define mc_intr_r(i)\
(nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32((i), 4U)))
#define mc_intr_pfifo_pending_f() (0x100U)
#define mc_intr_replayable_fault_pending_f() (0x200U)
#define mc_intr_pfb_pending_f() (0x2000U)
#define mc_intr_pgraph_pending_f() (0x1000U)
#define mc_intr_pmu_pending_f() (0x1000000U)
#define mc_intr_ltc_pending_f() (0x2000000U)
#define mc_intr_priv_ring_pending_f() (0x40000000U)
#define mc_intr_pbus_pending_f() (0x10000000U)
#define mc_intr_en_r(i)\
(nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32((i), 4U)))
#define mc_intr_en_set_r(i)\
(nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32((i), 4U)))
#define mc_intr_en_clear_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U)))
#define mc_enable_r() (0x00000200U)
#define mc_enable_xbar_enabled_f() (0x4U)
#define mc_enable_l2_enabled_f() (0x8U)
#define mc_enable_pmedia_s() (1U)
#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U)
#define mc_enable_pmedia_m() (U32(0x1U) << 4U)
#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U)
#define mc_enable_priv_ring_enabled_f() (0x20U)
#define mc_enable_ce0_m() (U32(0x1U) << 6U)
#define mc_enable_pfifo_enabled_f() (0x100U)
#define mc_enable_pgraph_enabled_f() (0x1000U)
#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U)
#define mc_enable_pwr_disabled_v() (0x00000000U)
#define mc_enable_pwr_enabled_f() (0x2000U)
#define mc_enable_pfb_enabled_f() (0x100000U)
#define mc_enable_ce2_m() (U32(0x1U) << 21U)
#define mc_enable_ce2_enabled_f() (0x200000U)
#define mc_enable_blg_enabled_f() (0x8000000U)
#define mc_enable_perfmon_enabled_f() (0x10000000U)
#define mc_enable_hub_enabled_f() (0x20000000U)
#define mc_intr_ltc_r() (0x000001c0U)
#define mc_enable_pb_r() (0x00000204U)
#define mc_enable_pb_0_s() (1U)
#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U)
#define mc_enable_pb_0_m() (U32(0x1U) << 0U)
#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U)
#define mc_enable_pb_0_enabled_v() (0x00000001U)
#define mc_enable_pb_sel_f(v, i)\
(((v) & 0x1) << (0U + i*1U))
#define mc_elpg_enable_r() (0x0000020cU)
#define mc_elpg_enable_xbar_enabled_f() (0x4U)
#define mc_elpg_enable_pfb_enabled_f() (0x100000U)
#define mc_elpg_enable_hub_enabled_f() (0x20000000U)
#endif

759
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,576 +59,189 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pbdma_gp_entry1_r(void)
{
return 0x10000004U;
}
static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
{
return (r >> 0U) & 0xffU;
}
static inline u32 pbdma_gp_entry1_length_f(u32 v)
{
return (v & 0x1fffffU) << 10U;
}
static inline u32 pbdma_gp_entry1_length_v(u32 r)
{
return (r >> 10U) & 0x1fffffU;
}
static inline u32 pbdma_gp_base_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_base__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 pbdma_gp_base_offset_f(u32 v)
{
return (v & 0x1fffffffU) << 3U;
}
static inline u32 pbdma_gp_base_rsvd_s(void)
{
return 3U;
}
static inline u32 pbdma_gp_base_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
{
return (v & 0x1fU) << 16U;
}
static inline u32 pbdma_gp_fetch_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_get_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_put_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_timeout_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_timeout__size_1_v(void)
{
return 0x00000001U;
}
static inline u32 pbdma_timeout_period_m(void)
{
return U32(0xffffffffU) << 0U;
}
static inline u32 pbdma_timeout_period_max_f(void)
{
return 0xffffffffU;
}
static inline u32 pbdma_pb_fetch_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_pb_fetch_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_get_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_get_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_put_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_put_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_formats_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_formats_gp_fermi0_f(void)
{
return 0x0U;
}
static inline u32 pbdma_formats_pb_fermi1_f(void)
{
return 0x100U;
}
static inline u32 pbdma_formats_mp_fermi0_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_pb_header_priv_user_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_method_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_subchannel_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_level_main_f(void)
{
return 0x0U;
}
static inline u32 pbdma_pb_header_first_true_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_pb_header_type_inc_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_pb_header_type_non_inc_f(void)
{
return 0x60000000U;
}
static inline u32 pbdma_hdr_shadow_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_shadow_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_gp_shadow_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_subdevice_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_subdevice_id_f(u32 v)
{
return (v & 0xfffU) << 0U;
}
static inline u32 pbdma_subdevice_status_active_f(void)
{
return 0x10000000U;
}
static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_method0_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method0_fifo_size_v(void)
{
return 0x00000004U;
}
static inline u32 pbdma_method0_addr_f(u32 v)
{
return (v & 0xfffU) << 2U;
}
static inline u32 pbdma_method0_addr_v(u32 r)
{
return (r >> 2U) & 0xfffU;
}
static inline u32 pbdma_method0_subch_v(u32 r)
{
return (r >> 16U) & 0x7U;
}
static inline u32 pbdma_method0_first_true_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_method0_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_method1_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method2_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_method3_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_data0_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_target_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_target_engine_sw_f(void)
{
return 0x1fU;
}
static inline u32 pbdma_acquire_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_acquire_retry_man_2_f(void)
{
return 0x2U;
}
static inline u32 pbdma_acquire_retry_exp_2_f(void)
{
return 0x100U;
}
static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
{
return (v & 0xfU) << 11U;
}
static inline u32 pbdma_acquire_timeout_exp_max_v(void)
{
return 0x0000000fU;
}
static inline u32 pbdma_acquire_timeout_exp_max_f(void)
{
return 0x7800U;
}
static inline u32 pbdma_acquire_timeout_man_f(u32 v)
{
return (v & 0xffffU) << 15U;
}
static inline u32 pbdma_acquire_timeout_man_max_v(void)
{
return 0x0000ffffU;
}
static inline u32 pbdma_acquire_timeout_man_max_f(void)
{
return 0x7fff8000U;
}
static inline u32 pbdma_acquire_timeout_en_enable_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_acquire_timeout_en_disable_f(void)
{
return 0x0U;
}
static inline u32 pbdma_status_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_channel_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_signature_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_signature_hw_valid_f(void)
{
return 0xfaceU;
}
static inline u32 pbdma_signature_sw_zero_f(void)
{
return 0x0U;
}
static inline u32 pbdma_userd_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_userd_target_vid_mem_f(void)
{
return 0x0U;
}
static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
{
return 0x2U;
}
static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
{
return 0x3U;
}
static inline u32 pbdma_userd_addr_f(u32 v)
{
return (v & 0x7fffffU) << 9U;
}
static inline u32 pbdma_userd_hi_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_userd_hi_addr_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 pbdma_config_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_config_auth_level_privileged_f(void)
{
return 0x100U;
}
static inline u32 pbdma_hce_ctrl_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
{
return 0x20U;
}
static inline u32 pbdma_intr_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_0_memreq_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pbdma_intr_0_memreq_pending_f(void)
{
return 0x1U;
}
static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
{
return 0x2U;
}
static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
{
return 0x4U;
}
static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
{
return 0x8U;
}
static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
{
return 0x10U;
}
static inline u32 pbdma_intr_0_memflush_pending_f(void)
{
return 0x20U;
}
static inline u32 pbdma_intr_0_memop_pending_f(void)
{
return 0x40U;
}
static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
{
return 0x80U;
}
static inline u32 pbdma_intr_0_lbreq_pending_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
{
return 0x200U;
}
static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
{
return 0x400U;
}
static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
{
return 0x800U;
}
static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
{
return 0x1000U;
}
static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
{
return 0x2000U;
}
static inline u32 pbdma_intr_0_gpptr_pending_f(void)
{
return 0x4000U;
}
static inline u32 pbdma_intr_0_gpentry_pending_f(void)
{
return 0x8000U;
}
static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
{
return 0x10000U;
}
static inline u32 pbdma_intr_0_pbptr_pending_f(void)
{
return 0x20000U;
}
static inline u32 pbdma_intr_0_pbentry_pending_f(void)
{
return 0x40000U;
}
static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
{
return 0x80000U;
}
static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
{
return 0x100000U;
}
static inline u32 pbdma_intr_0_method_pending_f(void)
{
return 0x200000U;
}
static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
{
return 0x400000U;
}
static inline u32 pbdma_intr_0_device_pending_f(void)
{
return 0x800000U;
}
static inline u32 pbdma_intr_0_semaphore_pending_f(void)
{
return 0x2000000U;
}
static inline u32 pbdma_intr_0_acquire_pending_f(void)
{
return 0x4000000U;
}
static inline u32 pbdma_intr_0_pri_pending_f(void)
{
return 0x8000000U;
}
static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
{
return 0x20000000U;
}
static inline u32 pbdma_intr_0_pbseg_pending_f(void)
{
return 0x40000000U;
}
static inline u32 pbdma_intr_0_signature_pending_f(void)
{
return 0x80000000U;
}
static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void)
{
return 0x10000000U;
}
static inline u32 pbdma_intr_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_en_0_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_en_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_r(u32 i)
{
return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
{
return 0x100U;
}
static inline u32 pbdma_intr_stall_1_r(u32 i)
{
return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
{
return 0x1U;
}
static inline u32 pbdma_udma_nop_r(void)
{
return 0x00000008U;
}
static inline u32 pbdma_allowed_syncpoints_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400e8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v)
{
return (v & 0x7fffU) << 16U;
}
static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r)
{
return (r >> 16U) & 0x7fffU;
}
static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v)
{
return (v & 0x1U) << 15U;
}
static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v)
{
return (v & 0x7fffU) << 0U;
}
static inline u32 pbdma_syncpointa_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_syncpointa_payload_v(u32 r)
{
return (r >> 0U) & 0xffffffffU;
}
static inline u32 pbdma_syncpointb_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_syncpointb_op_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pbdma_syncpointb_op_wait_v(void)
{
return 0x00000000U;
}
static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
{
return 0x00000001U;
}
static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
{
return (r >> 8U) & 0xfffU;
}
static inline u32 pbdma_runlist_timeslice_r(u32 i)
{
return nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32(i, 8192U));
}
static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
{
return 0x80U;
}
static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
{
return 0x3000U;
}
static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
{
return 0x10000000U;
}
#define pbdma_gp_entry1_r() (0x10000004U)
#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU)
#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U)
#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU)
#define pbdma_gp_base_r(i)\
(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base__size_1_v() (0x00000001U)
#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U)
#define pbdma_gp_base_rsvd_s() (3U)
#define pbdma_gp_base_hi_r(i)\
(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U)
#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U)
#define pbdma_gp_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_get_r(i)\
(nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_put_r(i)\
(nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_timeout_r(i)\
(nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_timeout__size_1_v() (0x00000001U)
#define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U)
#define pbdma_timeout_period_max_f() (0xffffffffU)
#define pbdma_pb_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_pb_fetch_hi_r(i)\
(nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_get_r(i)\
(nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_get_hi_r(i)\
(nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_put_r(i)\
(nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_put_hi_r(i)\
(nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_formats_r(i)\
(nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_formats_gp_fermi0_f() (0x0U)
#define pbdma_formats_pb_fermi1_f() (0x100U)
#define pbdma_formats_mp_fermi0_f() (0x0U)
#define pbdma_pb_header_r(i)\
(nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_pb_header_priv_user_f() (0x0U)
#define pbdma_pb_header_method_zero_f() (0x0U)
#define pbdma_pb_header_subchannel_zero_f() (0x0U)
#define pbdma_pb_header_level_main_f() (0x0U)
#define pbdma_pb_header_first_true_f() (0x400000U)
#define pbdma_pb_header_type_inc_f() (0x20000000U)
#define pbdma_pb_header_type_non_inc_f() (0x60000000U)
#define pbdma_hdr_shadow_r(i)\
(nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_shadow_0_r(i)\
(nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_shadow_1_r(i)\
(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_r(i)\
(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U)
#define pbdma_subdevice_status_active_f() (0x10000000U)
#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U)
#define pbdma_method0_r(i)\
(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method0_fifo_size_v() (0x00000004U)
#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U)
#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU)
#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U)
#define pbdma_method0_first_true_f() (0x400000U)
#define pbdma_method0_valid_true_f() (0x80000000U)
#define pbdma_method1_r(i)\
(nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method2_r(i)\
(nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method3_r(i)\
(nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_data0_r(i)\
(nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_target_r(i)\
(nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_target_engine_sw_f() (0x1fU)
#define pbdma_acquire_r(i)\
(nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_acquire_retry_man_2_f() (0x2U)
#define pbdma_acquire_retry_exp_2_f() (0x100U)
#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U)
#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU)
#define pbdma_acquire_timeout_exp_max_f() (0x7800U)
#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U)
#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU)
#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U)
#define pbdma_acquire_timeout_en_enable_f() (0x80000000U)
#define pbdma_acquire_timeout_en_disable_f() (0x0U)
#define pbdma_status_r(i)\
(nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_channel_r(i)\
(nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_signature_r(i)\
(nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_signature_hw_valid_f() (0xfaceU)
#define pbdma_signature_sw_zero_f() (0x0U)
#define pbdma_userd_r(i)\
(nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_target_vid_mem_f() (0x0U)
#define pbdma_userd_target_sys_mem_coh_f() (0x2U)
#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U)
#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U)
#define pbdma_userd_hi_r(i)\
(nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U)
#define pbdma_config_r(i)\
(nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_config_auth_level_privileged_f() (0x100U)
#define pbdma_hce_ctrl_r(i)\
(nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U)
#define pbdma_intr_0_r(i)\
(nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U)
#define pbdma_intr_0_memreq_pending_f() (0x1U)
#define pbdma_intr_0_memack_timeout_pending_f() (0x2U)
#define pbdma_intr_0_memack_extra_pending_f() (0x4U)
#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U)
#define pbdma_intr_0_memdat_extra_pending_f() (0x10U)
#define pbdma_intr_0_memflush_pending_f() (0x20U)
#define pbdma_intr_0_memop_pending_f() (0x40U)
#define pbdma_intr_0_lbconnect_pending_f() (0x80U)
#define pbdma_intr_0_lbreq_pending_f() (0x100U)
#define pbdma_intr_0_lback_timeout_pending_f() (0x200U)
#define pbdma_intr_0_lback_extra_pending_f() (0x400U)
#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U)
#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U)
#define pbdma_intr_0_gpfifo_pending_f() (0x2000U)
#define pbdma_intr_0_gpptr_pending_f() (0x4000U)
#define pbdma_intr_0_gpentry_pending_f() (0x8000U)
#define pbdma_intr_0_gpcrc_pending_f() (0x10000U)
#define pbdma_intr_0_pbptr_pending_f() (0x20000U)
#define pbdma_intr_0_pbentry_pending_f() (0x40000U)
#define pbdma_intr_0_pbcrc_pending_f() (0x80000U)
#define pbdma_intr_0_xbarconnect_pending_f() (0x100000U)
#define pbdma_intr_0_method_pending_f() (0x200000U)
#define pbdma_intr_0_methodcrc_pending_f() (0x400000U)
#define pbdma_intr_0_device_pending_f() (0x800000U)
#define pbdma_intr_0_semaphore_pending_f() (0x2000000U)
#define pbdma_intr_0_acquire_pending_f() (0x4000000U)
#define pbdma_intr_0_pri_pending_f() (0x8000000U)
#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U)
#define pbdma_intr_0_pbseg_pending_f() (0x40000000U)
#define pbdma_intr_0_signature_pending_f() (0x80000000U)
#define pbdma_intr_0_syncpoint_illegal_pending_f() (0x10000000U)
#define pbdma_intr_1_r(i)\
(nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_en_0_r(i)\
(nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_en_0_lbreq_enabled_f() (0x100U)
#define pbdma_intr_en_1_r(i)\
(nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_r(i)\
(nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_lbreq_enabled_f() (0x100U)
#define pbdma_intr_stall_1_r(i)\
(nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U)
#define pbdma_udma_nop_r() (0x00000008U)
#define pbdma_allowed_syncpoints_r(i)\
(nvgpu_safe_add_u32(0x000400e8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_allowed_syncpoints_0_valid_f(v) (((v)&0x1U) << 31U)
#define pbdma_allowed_syncpoints_0_index_f(v) (((v)&0x7fffU) << 16U)
#define pbdma_allowed_syncpoints_0_index_v(r) (((r) >> 16U) & 0x7fffU)
#define pbdma_allowed_syncpoints_1_valid_f(v) (((v)&0x1U) << 15U)
#define pbdma_allowed_syncpoints_1_index_f(v) (((v)&0x7fffU) << 0U)
#define pbdma_syncpointa_r(i)\
(nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_syncpointa_payload_v(r) (((r) >> 0U) & 0xffffffffU)
#define pbdma_syncpointb_r(i)\
(nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_syncpointb_op_v(r) (((r) >> 0U) & 0x1U)
#define pbdma_syncpointb_op_wait_v() (0x00000000U)
#define pbdma_syncpointb_wait_switch_v(r) (((r) >> 4U) & 0x1U)
#define pbdma_syncpointb_wait_switch_en_v() (0x00000001U)
#define pbdma_syncpointb_syncpt_index_v(r) (((r) >> 8U) & 0xfffU)
#define pbdma_runlist_timeslice_r(i)\
(nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_runlist_timeslice_timeout_128_f() (0x80U)
#define pbdma_runlist_timeslice_timescale_3_f() (0x3000U)
#define pbdma_runlist_timeslice_enable_true_f() (0x10000000U)
#endif

202
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,164 +59,44 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 perf_pmmsys_base_v(void)
{
return 0x001b0000U;
}
static inline u32 perf_pmmsys_extent_v(void)
{
return 0x001b0fffU;
}
static inline u32 perf_pmasys_control_r(void)
{
return 0x001b4000U;
}
static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
{
return (r >> 4U) & 0x1U;
}
static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
{
return 0x10U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
{
return (v & 0x1U) << 5U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
{
return (r >> 5U) & 0x1U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
{
return 0x20U;
}
static inline u32 perf_pmasys_mem_block_r(void)
{
return 0x001b4070U;
}
static inline u32 perf_pmasys_mem_block_base_f(u32 v)
{
return (v & 0xfffffffU) << 0U;
}
static inline u32 perf_pmasys_mem_block_target_f(u32 v)
{
return (v & 0x3U) << 28U;
}
static inline u32 perf_pmasys_mem_block_target_v(u32 r)
{
return (r >> 28U) & 0x3U;
}
static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
{
return 0x00000000U;
}
static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
{
return 0x0U;
}
static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
{
return 0x00000002U;
}
static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
{
return 0x20000000U;
}
static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
{
return 0x00000003U;
}
static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
{
return 0x30000000U;
}
static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
{
return (v & 0x1U) << 31U;
}
static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 perf_pmasys_mem_block_valid_true_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_mem_block_valid_true_f(void)
{
return 0x80000000U;
}
static inline u32 perf_pmasys_mem_block_valid_false_v(void)
{
return 0x00000000U;
}
static inline u32 perf_pmasys_mem_block_valid_false_f(void)
{
return 0x0U;
}
static inline u32 perf_pmasys_outbase_r(void)
{
return 0x001b4074U;
}
static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
{
return (v & 0x7ffffffU) << 5U;
}
static inline u32 perf_pmasys_outbaseupper_r(void)
{
return 0x001b4078U;
}
static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
{
return (v & 0xffU) << 0U;
}
static inline u32 perf_pmasys_outsize_r(void)
{
return 0x001b407cU;
}
static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
{
return (v & 0x7ffffffU) << 5U;
}
static inline u32 perf_pmasys_mem_bytes_r(void)
{
return 0x001b4084U;
}
static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 perf_pmasys_mem_bump_r(void)
{
return 0x001b4088U;
}
static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
{
return (v & 0xfffffffU) << 4U;
}
static inline u32 perf_pmasys_enginestatus_r(void)
{
return 0x001b40a4U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
{
return (v & 0x1U) << 4U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
{
return 0x00000001U;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
{
return 0x10U;
}
#define perf_pmmsys_base_v() (0x001b0000U)
#define perf_pmmsys_extent_v() (0x001b0fffU)
#define perf_pmasys_control_r() (0x001b4000U)
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)
#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U)
#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U)
#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U)
#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U)
#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U)
#define perf_pmasys_mem_block_r() (0x001b4070U)
#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U)
#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U)
#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U)
#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U)
#define perf_pmasys_mem_block_target_lfb_f() (0x0U)
#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U)
#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U)
#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U)
#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U)
#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U)
#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U)
#define perf_pmasys_mem_block_valid_true_v() (0x00000001U)
#define perf_pmasys_mem_block_valid_true_f() (0x80000000U)
#define perf_pmasys_mem_block_valid_false_v() (0x00000000U)
#define perf_pmasys_mem_block_valid_false_f() (0x0U)
#define perf_pmasys_outbase_r() (0x001b4074U)
#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U)
#define perf_pmasys_outbaseupper_r() (0x001b4078U)
#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U)
#define perf_pmasys_outsize_r() (0x001b407cU)
#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U)
#define perf_pmasys_mem_bytes_r() (0x001b4084U)
#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U)
#define perf_pmasys_mem_bump_r() (0x001b4088U)
#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U)
#define perf_pmasys_enginestatus_r() (0x001b40a4U)
#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U)
#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U)
#endif

8
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,8 +59,6 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pram_data032_r(u32 i)
{
return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U));
}
#define pram_data032_r(i)\
(nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U)))
#endif

139
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,112 +59,33 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringmaster_command_r(void)
{
return 0x0012004cU;
}
static inline u32 pri_ringmaster_command_cmd_m(void)
{
return U32(0x3fU) << 0U;
}
static inline u32 pri_ringmaster_command_cmd_v(u32 r)
{
return (r >> 0U) & 0x3fU;
}
static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
{
return 0x00000000U;
}
static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
{
return 0x1U;
}
static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
{
return 0x2U;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
{
return 0x3U;
}
static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
{
return 0x0U;
}
static inline u32 pri_ringmaster_command_data_r(void)
{
return 0x00120048U;
}
static inline u32 pri_ringmaster_start_results_r(void)
{
return 0x00120050U;
}
static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
{
return 0x00000001U;
}
static inline u32 pri_ringmaster_intr_status0_r(void)
{
return 0x00120058U;
}
static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
{
return (r >> 0U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
{
return (r >> 2U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
{
return (r >> 8U) & 0x1U;
}
static inline u32 pri_ringmaster_intr_status1_r(void)
{
return 0x0012005cU;
}
static inline u32 pri_ringmaster_global_ctl_r(void)
{
return 0x00120060U;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
{
return 0x1U;
}
static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
{
return 0x0U;
}
static inline u32 pri_ringmaster_enum_fbp_r(void)
{
return 0x00120074U;
}
static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 pri_ringmaster_enum_gpc_r(void)
{
return 0x00120078U;
}
static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 pri_ringmaster_enum_ltc_r(void)
{
return 0x0012006cU;
}
static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
#define pri_ringmaster_command_r() (0x0012004cU)
#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U)
#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU)
#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U)
#define pri_ringmaster_command_cmd_start_ring_f() (0x1U)
#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U)
#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U)
#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U)
#define pri_ringmaster_command_data_r() (0x00120048U)
#define pri_ringmaster_start_results_r() (0x00120050U)
#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U)
#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U)
#define pri_ringmaster_intr_status0_r() (0x00120058U)
#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\
(((r) >> 0U) & 0x1U)
#define pri_ringmaster_intr_status0_disconnect_fault_v(r) (((r) >> 1U) & 0x1U)
#define pri_ringmaster_intr_status0_overflow_fault_v(r) (((r) >> 2U) & 0x1U)
#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\
(((r) >> 8U) & 0x1U)
#define pri_ringmaster_intr_status1_r() (0x0012005cU)
#define pri_ringmaster_global_ctl_r() (0x00120060U)
#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U)
#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U)
#define pri_ringmaster_enum_fbp_r() (0x00120074U)
#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU)
#define pri_ringmaster_enum_gpc_r() (0x00120078U)
#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU)
#define pri_ringmaster_enum_ltc_r() (0x0012006cU)
#define pri_ringmaster_enum_ltc_count_v(r) (((r) >> 0U) & 0x1fU)
#endif

40
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function naming determines intended use:
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
@@ -59,32 +59,14 @@
#include <nvgpu/types.h>
#include <nvgpu/safe_ops.h>
static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
{
return nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32(i, 4U));
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
{
return 0x00128120U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
{
return 0x00128124U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
{
return 0x00128128U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_subid_v(u32 r)
{
return (r >> 24U) & 0x3fU;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(u32 r)
{
return (r >> 20U) & 0x3U;
}
static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
{
return 0x0012812cU;
}
#define pri_ringstation_gpc_master_config_r(i)\
(nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32((i), 4U)))
#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U)
#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U)
#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U)
#define pri_ringstation_gpc_gpc0_priv_error_info_subid_v(r)\
(((r) >> 24U) & 0x3fU)
#define pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(r)\
(((r) >> 20U) & 0x3U)
#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU)
#endif

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