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gpu: nvgpu: fix priv error register reads

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Current code does not compute priv error register offsets
properly. This leads to invalid decoding of priv errors, and
can also trigger additional priv errors.

- add GPU_LIT_GPC_PRIV_STRIDE define
- return proj_gpc_priv_stride for GPU_LIT_GPC_PRIV_STRIDE in hals
- use GPU_LIT_GPC_PRIV_STRIDE instead of GPU_LIT_GPC_STRIDE in
  g->ops.priv_ring.isr() to compute priv error register offsets.

Bug 2093058

Change-Id: Ia7c36ccba0441126784bb0e00452f2cf1196ef71
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1682118
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2018-03-26 11:42:42 -07:00
committed by mobile promotions
parent 1557ee63ed
commit 8a64eea483
8 changed files with 22 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -141,6 +141,7 @@ enum gk20a_cbc_op {
#define GPU_LIT_GPFIFO_CLASS 34
#define GPU_LIT_I2M_CLASS 35
#define GPU_LIT_DMA_COPY_CLASS 36
#define GPU_LIT_GPC_PRIV_STRIDE 37
#define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v)

10
drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
View File

@@ -58,7 +58,7 @@ void gk20a_priv_ring_isr(struct gk20a *g)
u32 cmd;
s32 retry = 100;
u32 gpc;
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 gpc_priv_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE);
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
return;
@@ -80,10 +80,10 @@ void gk20a_priv_ring_isr(struct gk20a *g)
for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
if (status1 & BIT(gpc)) {
gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc,
gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride),
gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride),
gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride),
gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride));
gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_priv_stride),
gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_priv_stride),
gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_priv_stride),
gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_priv_stride));
}
}
/* clear interrupt */

3
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -172,6 +172,9 @@ int gm20b_get_litter_value(struct gk20a *g, int value)
case GPU_LIT_DMA_COPY_CLASS:
ret = MAXWELL_DMA_COPY_A;
break;
case GPU_LIT_GPC_PRIV_STRIDE:
ret = proj_gpc_priv_stride_v();
break;
default:
nvgpu_err(g, "Missing definition %d", value);
BUG();

3
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -198,6 +198,9 @@ static int gp106_get_litter_value(struct gk20a *g, int value)
case GPU_LIT_DMA_COPY_CLASS:
ret = PASCAL_DMA_COPY_A;
break;
case GPU_LIT_GPC_PRIV_STRIDE:
ret = proj_gpc_priv_stride_v();
break;
default:
BUG();
break;

4
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -181,7 +181,9 @@ int gp10b_get_litter_value(struct gk20a *g, int value)
case GPU_LIT_DMA_COPY_CLASS:
ret = PASCAL_DMA_COPY_A;
break;
case GPU_LIT_GPC_PRIV_STRIDE:
ret = proj_gpc_priv_stride_v();
break;
default:
nvgpu_err(g, "Missing definition %d", value);
BUG();

2
drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
View File

@@ -145,7 +145,7 @@ void gp10b_priv_ring_isr(struct gk20a *g)
}
if (status1) {
gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE);
for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
offset = gpc * gpc_stride;
if (status1 & BIT(gpc)) {

3
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -232,6 +232,9 @@ static int gv100_get_litter_value(struct gk20a *g, int value)
case GPU_LIT_DMA_COPY_CLASS:
ret = VOLTA_DMA_COPY_A;
break;
case GPU_LIT_GPC_PRIV_STRIDE:
ret = proj_gpc_priv_stride_v();
break;
default:
break;
}

4
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -209,7 +209,9 @@ int gv11b_get_litter_value(struct gk20a *g, int value)
case GPU_LIT_DMA_COPY_CLASS:
ret = VOLTA_DMA_COPY_A;
break;
case GPU_LIT_GPC_PRIV_STRIDE:
ret = proj_gpc_priv_stride_v();
break;
default:
nvgpu_err(g, "Missing definition %d", value);
BUG();