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gpu: nvgpu: Use reset_enum to get mc engine mask

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Currently, we need to include the MC hardware header in nvlink file
to generate reset mask.
We can use the reset_enum present in DEVICE_INFO table's IOCTRL entry
which is meant to index into NV_PMC_ENABLE_DEVICE register bitfields.
This allows us to not #include the MC hardware header in nvlink IP
file.

JIRA NVGPU-966

Change-Id: I037498038b12f795ee444916fb586355ebf04bb3
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796819
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2018-08-10 16:28:21 +05:30
committed by mobile promotions
parent 90f268963c
commit 8c8cdacf7a
1 changed files with 5 additions and 1 deletions
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6
drivers/gpu/nvgpu/gv100/nvlink_gv100.c
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@@ -2688,6 +2688,7 @@ void gv100_nvlink_get_connected_link_mask(u32 *link_mask)
int gv100_nvlink_early_init(struct gk20a *g)
{
int err = 0;
u32 mc_reset_nvlink_mask;
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK))
return -EINVAL;
@@ -2703,7 +2704,10 @@ int gv100_nvlink_early_init(struct gk20a *g)
goto nvlink_init_exit;
/* Enable NVLINK in MC */
g->ops.mc.reset(g, mc_enable_nvlink_enabled_f());
mc_reset_nvlink_mask = BIT32(g->nvlink.ioctrl_table[0].reset_enum);
nvgpu_log(g, gpu_dbg_nvlink, "mc_reset_nvlink_mask: 0x%x",
mc_reset_nvlink_mask);
g->ops.mc.reset(g, mc_reset_nvlink_mask);
err = g->ops.nvlink.discover_link(g);
if (err || g->nvlink.discovered_links == 0) {