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gpu: nvgpu: doxygen update for unit os_utils

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Add range value details for various os_utils functions.

Jira NVGPU-6258

Change-Id: Ib930a24d2a4b8e98520d87fcc2f48bef81d26fbd
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480205
(cherry picked from commit 210e1dd5360d29cad1a432e8de48669d51de134c)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2483388
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
prsethi
2021-02-04 07:54:58 +00:00
committed by mobile promotions
parent bc0e81adda
commit 8d55f14fc9
2 changed files with 9 additions and 2 deletions
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8
drivers/gpu/nvgpu/include/nvgpu/io.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -46,6 +46,7 @@ struct gk20a;
* *
* @param g [in] GPU super structure. * @param g [in] GPU super structure.
* @param r [in] Register offset in GPU IO space. * @param r [in] Register offset in GPU IO space.
* Range: 0 - TEGRA_GK20A_BAR0_SIZE.
* @param v [in] Value to write at the offset. * @param v [in] Value to write at the offset.
* *
* Write a 32-bit value to register offset in GPU IO space with an * Write a 32-bit value to register offset in GPU IO space with an
@@ -77,6 +78,7 @@ void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v);
* *
* @param g [in] GPU super structure. * @param g [in] GPU super structure.
* @param r [in] Register offset in GPU IO space. * @param r [in] Register offset in GPU IO space.
* Range: 0 - TEGRA_GK20A_BAR0_SIZE.
* *
* Read a 32-bit value from register offset in GPU IO space. If all * Read a 32-bit value from register offset in GPU IO space. If all
* the bits are set in the value read then check for gpu state validity. * the bits are set in the value read then check for gpu state validity.
@@ -91,6 +93,7 @@ u32 nvgpu_readl(struct gk20a *g, u32 r);
* *
* @param g [in] GPU super structure. * @param g [in] GPU super structure.
* @param r [in] Register offset in GPU IO space. * @param r [in] Register offset in GPU IO space.
* Range: 0 - TEGRA_GK20A_BAR0_SIZE.
* *
* Read a 32-bit to register offset from a GPU IO space. nvgpu_readl() is * Read a 32-bit to register offset from a GPU IO space. nvgpu_readl() is
* called from this function. This function is implemented by the OS layer. * called from this function. This function is implemented by the OS layer.
@@ -135,6 +138,7 @@ void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v);
* *
* @param g [in] GPU super structure. * @param g [in] GPU super structure.
* @param r [in] Register offset in io-region. * @param r [in] Register offset in io-region.
* Range: 0 - TEGRA_GK20A_BAR1_SIZE.
* @param v [in] Value to write at the offset. * @param v [in] Value to write at the offset.
* *
* - Write a 32-bit value to register offset of region bar1. * - Write a 32-bit value to register offset of region bar1.
@@ -148,6 +152,7 @@ void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v);
* *
* @param g [in] GPU super structure. * @param g [in] GPU super structure.
* @param b [in] Register offset in io-region. * @param b [in] Register offset in io-region.
* Range: 0 - TEGRA_GK20A_BAR1_SIZE.
* *
* - Read a 32-bit value from a region bar1. * - Read a 32-bit value from a region bar1.
* *
@@ -171,6 +176,7 @@ bool nvgpu_io_exists(struct gk20a *g);
* *
* @param g [in] GPU super structure. * @param g [in] GPU super structure.
* @param r [in] Register offset in io-region. * @param r [in] Register offset in io-region.
* Range: 0 - TEGRA_GK20A_BAR0_SIZE.
* *
* - BAR0 Offset is valid if it falls into BAR0 range. * - BAR0 Offset is valid if it falls into BAR0 range.
* *

3
drivers/gpu/nvgpu/include/nvgpu/timers.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -269,6 +269,7 @@ u64 nvgpu_hr_timestamp(void);
* @brief OS specific implementation to provide precise microsecond delay * @brief OS specific implementation to provide precise microsecond delay
* *
* @param usecs [in] Delay in microseconds. * @param usecs [in] Delay in microseconds.
* Range: 0 - 500ms.
* *
* - Wait using nanospin_ns until usecs expires. Log error if API returns non * - Wait using nanospin_ns until usecs expires. Log error if API returns non
* zero value once wait time expires. * zero value once wait time expires.