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gpu: nvgpu: unit: use gr/ce engine interrupt mask

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nvgpu_engine_interrupt_mask has been split into
nvgpu_gr_engine_interrupt_mask and nvgpu_gr_engine_interrupt_mask.
Update test_engine_interrupt_mask to combine them.

Jira NVGPU-3693

Change-Id: I1e09ff3efd83415120773da75f8b512a481ee14c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2249913
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-11-27 14:30:47 -05:00
committed by Alex Waterman
parent 0ba37ecf4d
commit 8fa2fcd9da
2 changed files with 7 additions and 4 deletions
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4
userspace/units/fifo/engine/nvgpu-engine.c
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@@ -362,7 +362,9 @@ int test_engine_interrupt_mask(struct unit_module *m,
struct gk20a *g, void *args)
{
int ret = UNIT_FAIL;
u32 intr_mask = nvgpu_engine_interrupt_mask(g);
u32 intr_mask =
nvgpu_gr_engine_interrupt_mask(g) |
nvgpu_ce_engine_interrupt_mask(g);
u32 all_mask = 0U;
u32 ce_reset_mask;
u32 mask;