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gpu: nvgpu: PMU NS ucode boot update

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Removed gpmu_ucode.bin usage by fetching PMU ucode descriptor
and image from respective files for NS boot.

JIRA NVGPU-5183

Change-Id: I597c5dd17b4a58603f550b32980d7d0ca9624aed
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2376448
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
mkumbar
2020-07-16 15:51:23 +05:30
committed by Alex Waterman
parent 3f75e62c26
commit 918fa1a658
4 changed files with 29 additions and 43 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/nvgpu/common/pmu/fw/fw.c
View File

@@ -33,9 +33,7 @@
#include <nvgpu/pmu/fw.h> #include <nvgpu/pmu/fw.h>
#include <nvgpu/pmu/pmu_pg.h> #include <nvgpu/pmu/pmu_pg.h>
/* PMU NS UCODE IMG */ /* PMU UCODE IMG */
#define NVGPU_PMU_NS_UCODE_IMAGE "gpmu_ucode.bin"
/* PMU SECURE UCODE IMG */
#define NVGPU_PMU_UCODE_IMAGE "gpmu_ucode_image.bin" #define NVGPU_PMU_UCODE_IMAGE "gpmu_ucode_image.bin"
#define NVGPU_PMU_UCODE_DESC "gpmu_ucode_desc.bin" #define NVGPU_PMU_UCODE_DESC "gpmu_ucode_desc.bin"
#define NVGPU_PMU_UCODE_SIG "pmu_sig.bin" #define NVGPU_PMU_UCODE_SIG "pmu_sig.bin"
@@ -211,19 +209,6 @@ static int pmu_fw_read_and_init_ops(struct gk20a *g, struct nvgpu_pmu *pmu,
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
/* non-secure PMU boot uocde */
rtos_fw->fw_image = nvgpu_request_firmware(g,
NVGPU_PMU_NS_UCODE_IMAGE, 0);
if (rtos_fw->fw_image == NULL) {
nvgpu_err(g,
"failed to load non-secure pmu ucode!!");
goto exit;
}
desc = (struct pmu_ucode_desc *)
(void *)rtos_fw->fw_image->data;
} else {
/* secure boot ucodes's */ /* secure boot ucodes's */
nvgpu_pmu_dbg(g, "requesting PMU ucode image"); nvgpu_pmu_dbg(g, "requesting PMU ucode image");
rtos_fw->fw_image = rtos_fw->fw_image =
@@ -245,6 +230,7 @@ static int pmu_fw_read_and_init_ops(struct gk20a *g, struct nvgpu_pmu *pmu,
goto release_img_fw; goto release_img_fw;
} }
if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
nvgpu_pmu_dbg(g, "requesting PMU ucode sign"); nvgpu_pmu_dbg(g, "requesting PMU ucode sign");
rtos_fw->fw_sig = rtos_fw->fw_sig =
nvgpu_request_firmware(g, nvgpu_request_firmware(g,
@@ -254,10 +240,10 @@ static int pmu_fw_read_and_init_ops(struct gk20a *g, struct nvgpu_pmu *pmu,
err = -ENOENT; err = -ENOENT;
goto release_desc; goto release_desc;
} }
}
desc = (struct pmu_ucode_desc *)(void *) desc = (struct pmu_ucode_desc *)(void *)
rtos_fw->fw_desc->data; rtos_fw->fw_desc->data;
}
err = nvgpu_pmu_init_fw_ver_ops(g, pmu, desc->app_version); err = nvgpu_pmu_init_fw_ver_ops(g, pmu, desc->app_version);
if (err != 0) { if (err != 0) {

4
drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c
View File

@@ -39,8 +39,8 @@ static int pmu_prepare_ns_ucode_blob(struct gk20a *g)
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
desc = (struct pmu_ucode_desc *)(void *)rtos_fw->fw_image->data; desc = (struct pmu_ucode_desc *)(void *)rtos_fw->fw_desc->data;
ucode_image = (u32 *)(void *)((u8 *)desc + desc->descriptor_size); ucode_image = (u32 *)(void *)rtos_fw->fw_image->data;
if (!nvgpu_mem_is_valid(&rtos_fw->ucode)) { if (!nvgpu_mem_is_valid(&rtos_fw->ucode)) {
err = nvgpu_dma_alloc_map_sys(vm, PMU_RTOS_UCODE_SIZE_MAX, err = nvgpu_dma_alloc_map_sys(vm, PMU_RTOS_UCODE_SIZE_MAX,

2
drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
View File

@@ -625,7 +625,7 @@ int gk20a_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
fw = nvgpu_pmu_fw_image_desc(g, pmu); fw = nvgpu_pmu_fw_desc_desc(g, pmu);
desc = (struct pmu_ucode_desc *)(void *)fw->data; desc = (struct pmu_ucode_desc *)(void *)fw->data;
gk20a_writel(g, pwr_falcon_itfen_r(), gk20a_writel(g, pwr_falcon_itfen_r(),

4
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -146,7 +146,7 @@ int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
fw = nvgpu_pmu_fw_image_desc(g, pmu); fw = nvgpu_pmu_fw_desc_desc(g, pmu);
desc = (struct pmu_ucode_desc *)(void *)fw->data; desc = (struct pmu_ucode_desc *)(void *)fw->data;
nvgpu_writel(g, pwr_falcon_itfen_r(), nvgpu_writel(g, pwr_falcon_itfen_r(),