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gpu: nvgpu: rename gv11b zbc hals

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Renamed gr_gv11b zbc hal function which do register access as
gv11b_gr_zbc* hal function.

gr_gv11b_add_zbc_s -> gv11b_gr_zbc_add_stencil

common code gr_gv11b zbc hal functions are renamed as
nvgpu_gr_zbc* hal functions.

gr_gv11b_zbc_s_query_table -> nvgpu_gr_zbc_stencil_query_table
gr_gv11b_add_zbc_type_s -> nvgpu_gr_zbc_add_type_stencil
gr_gv11b_load_stencil_default_tbl ->
                     nvgpu_gr_zbc_load_stencil_default_tbl
gr_gv11b_load_stencil_tbl -> nvgpu_gr_zbc_load_stencil_tbl

gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg ->
		gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg
gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg ->
		gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg

JIRA NVGPU-1882

Change-Id: I00b62923d72d0165ce86316ec6047e99ecabacbd
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018951
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-02-13 22:17:33 -08:00
committed by mobile promotions
parent b2cb5b097b
commit 92e12c0ca2
6 changed files with 44 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -348,12 +348,13 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.add_depth = NULL,
.set_table = vgpu_gr_add_zbc,
.query_table = vgpu_gr_query_zbc,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.stencil_query_table =
nvgpu_gr_zbc_stencil_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
.add_type_stencil = gr_gv11b_add_zbc_type_s,
.load_stencil_tbl = gr_gv11b_load_stencil_tbl,
.add_stencil = gr_gv11b_add_zbc_stencil,
nvgpu_gr_zbc_load_stencil_default_tbl,
.add_type_stencil = nvgpu_gr_zbc_add_type_stencil,
.load_stencil_tbl = nvgpu_gr_zbc_load_stencil_tbl,
.add_stencil = gv11b_gr_zbc_add_stencil,
.get_gpcs_swdx_dss_zbc_c_format_reg = NULL,
.get_gpcs_swdx_dss_zbc_z_format_reg = NULL,
}

15
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -584,16 +584,17 @@ static const struct gpu_ops gv100_ops = {
.add_depth = gp10b_gr_zbc_add_depth,
.set_table = nvgpu_gr_zbc_set_table,
.query_table = nvgpu_gr_zbc_query_table,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.stencil_query_table =
nvgpu_gr_zbc_stencil_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
.add_type_stencil = gr_gv11b_add_zbc_type_s,
.load_stencil_tbl = gr_gv11b_load_stencil_tbl,
.add_stencil = gr_gv11b_add_zbc_stencil,
nvgpu_gr_zbc_load_stencil_default_tbl,
.add_type_stencil = nvgpu_gr_zbc_add_type_stencil,
.load_stencil_tbl = nvgpu_gr_zbc_load_stencil_tbl,
.add_stencil = gv11b_gr_zbc_add_stencil,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg,
gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg,
gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg,
}
},
.fb = {

14
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1140,7 +1140,7 @@ int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
return 0;
}
int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr,
int nvgpu_gr_zbc_stencil_query_table(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_query_params *query_params)
{
u32 index = query_params->index_size;
@@ -1158,7 +1158,7 @@ int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr,
return 0;
}
bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr,
bool nvgpu_gr_zbc_add_type_stencil(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val, int *ret_val)
{
struct zbc_s_table *s_tbl;
@@ -1198,7 +1198,7 @@ bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr,
return added;
}
int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr,
int gv11b_gr_zbc_add_stencil(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *stencil_val, u32 index)
{
u32 zbc_s;
@@ -1224,7 +1224,7 @@ int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr,
return 0;
}
int gr_gv11b_load_stencil_default_tbl(struct gk20a *g,
int nvgpu_gr_zbc_load_stencil_default_tbl(struct gk20a *g,
struct gr_gk20a *gr)
{
struct zbc_entry zbc_val;
@@ -1262,7 +1262,7 @@ fail:
return err;
}
int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr)
int nvgpu_gr_zbc_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr)
{
int ret;
u32 i;
@@ -4780,12 +4780,12 @@ void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g)
}
u32 gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g)
u32 gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g)
{
return gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r();
}
u32 gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g)
u32 gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g)
{
return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r();
}

14
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -103,19 +103,19 @@ int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc,
int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc,
u32 gpc_exception);
void gr_gv11b_enable_gpc_exceptions(struct gk20a *g);
u32 gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g);
u32 gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g);
u32 gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g);
u32 gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g);
int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event);
int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr,
int nvgpu_gr_zbc_stencil_query_table(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_query_params *query_params);
bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr,
bool nvgpu_gr_zbc_add_type_stencil(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val, int *ret_val);
int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr,
int gv11b_gr_zbc_add_stencil(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *stencil_val, u32 index);
int gr_gv11b_load_stencil_default_tbl(struct gk20a *g,
int nvgpu_gr_zbc_load_stencil_default_tbl(struct gk20a *g,
struct gr_gk20a *gr);
int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr);
int nvgpu_gr_zbc_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr);
u32 gr_gv11b_pagepool_default_size(struct gk20a *g);
u32 gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g);
int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,

15
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -543,16 +543,17 @@ static const struct gpu_ops gv11b_ops = {
.add_depth = gp10b_gr_zbc_add_depth,
.set_table = nvgpu_gr_zbc_set_table,
.query_table = nvgpu_gr_zbc_query_table,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.stencil_query_table =
nvgpu_gr_zbc_stencil_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
.add_type_stencil = gr_gv11b_add_zbc_type_s,
.load_stencil_tbl = gr_gv11b_load_stencil_tbl,
.add_stencil = gr_gv11b_add_zbc_stencil,
nvgpu_gr_zbc_load_stencil_default_tbl,
.add_type_stencil = nvgpu_gr_zbc_add_type_stencil,
.load_stencil_tbl = nvgpu_gr_zbc_load_stencil_tbl,
.add_stencil = gv11b_gr_zbc_add_stencil,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg,
gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg,
gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg,
}
},
.fb = {

15
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -608,16 +608,17 @@ static const struct gpu_ops tu104_ops = {
.add_depth = gp10b_gr_zbc_add_depth,
.set_table = nvgpu_gr_zbc_set_table,
.query_table = nvgpu_gr_zbc_query_table,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.stencil_query_table =
nvgpu_gr_zbc_stencil_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
.add_type_stencil = gr_gv11b_add_zbc_type_s,
.load_stencil_tbl = gr_gv11b_load_stencil_tbl,
.add_stencil = gr_gv11b_add_zbc_stencil,
nvgpu_gr_zbc_load_stencil_default_tbl,
.add_type_stencil = nvgpu_gr_zbc_add_type_stencil,
.load_stencil_tbl = nvgpu_gr_zbc_load_stencil_tbl,
.add_stencil = gv11b_gr_zbc_add_stencil,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg,
gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg,
gv11b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg,
}
},
.fb = {