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gpu: nvgpu: rename gk20a and gp10b zbc hals

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Renamed gr_gk20a zbc hal functions which involve register access as
gk20a_gr_zbc* hal functions.

gr_gk20a_add_zbc_color -> gk20a_gr_zbc_add_color
gr_gk20a_add_zbc_depth -> gk20a_gr_zbc_add_depth

gr_gk20a zbc hal functions without any register access are renamed as
common function as nvgpu_gr_zbc*

gk20a_gr_zbc_set_table -> nvgpu_gr_zbc_set_table
gr_gk20a_query_zbc -> nvgpu_gr_zbc_query_table

Renamed gr_gp10b zbc hal functions as gp10b_gr_zbc* hal functions.
gr_gp10b_add_zbc_color -> gp10b_gr_zbc_add_color
gr_gp10b_add_zbc_depth -> gp10b_gr_zbc_add_depth
gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg ->
	gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg
gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg ->
	gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg

common code added for nvgpu_gr_zbc_add_color and
nvgpu_gr_zbc_add_depth which update ltc, update local copy
and call add_color or add_depth hal function

All these functions will be moved to common/gr/zbc location
in future updates.

gk20a_writel replaced with nvgpu_writel function.

JIRA NVGPU-1882

Change-Id: I717739e0b20c243e8f5ed3e00f8f76755587bcee
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018737
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-02-13 16:19:50 -08:00
committed by mobile promotions
parent 220ba0dfa4
commit b2cb5b097b
9 changed files with 106 additions and 105 deletions
Download Patch File Download Diff File Expand all files Collapse all files

112
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -2491,7 +2491,7 @@ int gr_gk20a_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
return 0;
}
int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
int nvgpu_gr_zbc_add_color(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *color_val, u32 index)
{
u32 i;
@@ -2499,28 +2499,6 @@ int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
/* update l2 table */
g->ops.ltc.set_zbc_color_entry(g, color_val, index);
/* update ds table */
gk20a_writel(g, gr_ds_zbc_color_r_r(),
gr_ds_zbc_color_r_val_f(color_val->color_ds[0]));
gk20a_writel(g, gr_ds_zbc_color_g_r(),
gr_ds_zbc_color_g_val_f(color_val->color_ds[1]));
gk20a_writel(g, gr_ds_zbc_color_b_r(),
gr_ds_zbc_color_b_val_f(color_val->color_ds[2]));
gk20a_writel(g, gr_ds_zbc_color_a_r(),
gr_ds_zbc_color_a_val_f(color_val->color_ds[3]));
gk20a_writel(g, gr_ds_zbc_color_fmt_r(),
gr_ds_zbc_color_fmt_val_f(color_val->format));
gk20a_writel(g, gr_ds_zbc_tbl_index_r(),
gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE));
/* trigger the write */
gk20a_writel(g, gr_ds_zbc_tbl_ld_r(),
gr_ds_zbc_tbl_ld_select_c_f() |
gr_ds_zbc_tbl_ld_action_write_f() |
gr_ds_zbc_tbl_ld_trigger_active_f());
/* update local copy */
for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) {
gr->zbc_col_tbl[index].color_l2[i] = color_val->color_l2[i];
@@ -2529,36 +2507,77 @@ int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
gr->zbc_col_tbl[index].format = color_val->format;
gr->zbc_col_tbl[index].ref_cnt++;
/* update zbc registers */
g->ops.gr.zbc.add_color(g, gr, color_val, index);
return 0;
}
int gk20a_gr_zbc_add_color(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *color_val, u32 index)
{
/* update ds table */
nvgpu_writel(g, gr_ds_zbc_color_r_r(),
gr_ds_zbc_color_r_val_f(color_val->color_ds[0]));
nvgpu_writel(g, gr_ds_zbc_color_g_r(),
gr_ds_zbc_color_g_val_f(color_val->color_ds[1]));
nvgpu_writel(g, gr_ds_zbc_color_b_r(),
gr_ds_zbc_color_b_val_f(color_val->color_ds[2]));
nvgpu_writel(g, gr_ds_zbc_color_a_r(),
gr_ds_zbc_color_a_val_f(color_val->color_ds[3]));
nvgpu_writel(g, gr_ds_zbc_color_fmt_r(),
gr_ds_zbc_color_fmt_val_f(color_val->format));
nvgpu_writel(g, gr_ds_zbc_tbl_index_r(),
gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE));
/* trigger the write */
nvgpu_writel(g, gr_ds_zbc_tbl_ld_r(),
gr_ds_zbc_tbl_ld_select_c_f() |
gr_ds_zbc_tbl_ld_action_write_f() |
gr_ds_zbc_tbl_ld_trigger_active_f());
return 0;
}
int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
int nvgpu_gr_zbc_add_depth(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index)
{
/* update l2 table */
g->ops.ltc.set_zbc_depth_entry(g, depth_val, index);
/* update ds table */
gk20a_writel(g, gr_ds_zbc_z_r(),
gr_ds_zbc_z_val_f(depth_val->depth));
gk20a_writel(g, gr_ds_zbc_z_fmt_r(),
gr_ds_zbc_z_fmt_val_f(depth_val->format));
gk20a_writel(g, gr_ds_zbc_tbl_index_r(),
gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE));
/* trigger the write */
gk20a_writel(g, gr_ds_zbc_tbl_ld_r(),
gr_ds_zbc_tbl_ld_select_z_f() |
gr_ds_zbc_tbl_ld_action_write_f() |
gr_ds_zbc_tbl_ld_trigger_active_f());
/* update local copy */
gr->zbc_dep_tbl[index].depth = depth_val->depth;
gr->zbc_dep_tbl[index].format = depth_val->format;
gr->zbc_dep_tbl[index].ref_cnt++;
/* update zbc registers */
g->ops.gr.zbc.add_depth(g, gr, depth_val, index);
return 0;
}
int gk20a_gr_zbc_add_depth(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index)
{
/* update ds table */
nvgpu_writel(g, gr_ds_zbc_z_r(),
gr_ds_zbc_z_val_f(depth_val->depth));
nvgpu_writel(g, gr_ds_zbc_z_fmt_r(),
gr_ds_zbc_z_fmt_val_f(depth_val->format));
nvgpu_writel(g, gr_ds_zbc_tbl_index_r(),
gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE));
/* trigger the write */
nvgpu_writel(g, gr_ds_zbc_tbl_ld_r(),
gr_ds_zbc_tbl_ld_select_z_f() |
gr_ds_zbc_tbl_ld_action_write_f() |
gr_ds_zbc_tbl_ld_trigger_active_f());
return 0;
}
@@ -2606,7 +2625,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
&gr->zbc_col_tbl[gr->max_used_color_index];
WARN_ON(c_tbl->ref_cnt != 0U);
ret = g->ops.gr.zbc.add_color(g, gr,
ret = nvgpu_gr_zbc_add_color(g, gr,
zbc_val, gr->max_used_color_index);
if (ret == 0) {
@@ -2637,7 +2656,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
&gr->zbc_dep_tbl[gr->max_used_depth_index];
WARN_ON(d_tbl->ref_cnt != 0U);
ret = g->ops.gr.zbc.add_depth(g, gr,
ret = nvgpu_gr_zbc_add_depth(g, gr,
zbc_val, gr->max_used_depth_index);
if (ret == 0) {
@@ -2677,7 +2696,7 @@ err_mutex:
/* get a zbc table entry specified by index
* return table size when type is invalid */
int gr_gk20a_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
int nvgpu_gr_zbc_query_table(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_query_params *query_params)
{
u32 index = query_params->index_size;
@@ -2735,7 +2754,6 @@ int gr_gk20a_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
return 0;
}
static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr)
{
unsigned int i;
@@ -2752,7 +2770,7 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr)
(u8 *)c_tbl->color_l2, sizeof(zbc_val.color_l2));
zbc_val.format = c_tbl->format;
ret = g->ops.gr.zbc.add_color(g, gr, &zbc_val, i);
ret = nvgpu_gr_zbc_add_color(g, gr, &zbc_val, i);
if (ret != 0) {
return ret;
@@ -2766,7 +2784,7 @@ static int gr_gk20a_load_zbc_table(struct gk20a *g, struct gr_gk20a *gr)
zbc_val.depth = d_tbl->depth;
zbc_val.format = d_tbl->format;
ret = g->ops.gr.zbc.add_depth(g, gr, &zbc_val, i);
ret = nvgpu_gr_zbc_add_depth(g, gr, &zbc_val, i);
if (ret != 0) {
return ret;
}
@@ -2870,7 +2888,7 @@ depth_fail:
return err;
}
int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
int nvgpu_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val)
{
nvgpu_log_fn(g, " ");

13
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -448,12 +448,15 @@ void gr_gk20a_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries,
/* zbc */
int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val);
int gr_gk20a_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
int nvgpu_gr_zbc_query_table(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_query_params *query_params);
int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
int nvgpu_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val);
int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr);
int nvgpu_gr_zbc_add_depth(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index);
int nvgpu_gr_zbc_add_color(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *color_val, u32 index);
/* pmu */
int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size);
int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g,
@@ -544,9 +547,9 @@ void gk20a_gr_suspend_all_sms(struct gk20a *g,
int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
struct channel_gk20a *ch, u64 sms, bool enable);
bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch);
int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
int gk20a_gr_zbc_add_color(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *color_val, u32 index);
int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
int gk20a_gr_zbc_add_depth(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index);
int gr_gk20a_wait_idle(struct gk20a *g);
int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,

8
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -411,10 +411,10 @@ static const struct gpu_ops gm20b_ops = {
gm20b_gr_config_get_pd_dist_skip_table_size,
},
.zbc = {
.add_color = gr_gk20a_add_zbc_color,
.add_depth = gr_gk20a_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.add_color = gk20a_gr_zbc_add_color,
.add_depth = gk20a_gr_zbc_add_depth,
.set_table = nvgpu_gr_zbc_set_table,
.query_table = nvgpu_gr_zbc_query_table,
.stencil_query_table = NULL,
.load_stencil_default_tbl = NULL,
.add_type_stencil = NULL,

34
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -521,30 +521,18 @@ void gr_gp10b_commit_global_pagepool(struct gk20a *g,
gr_gpcs_gcc_pagepool_total_pages_f(size), patch);
}
u32 gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g)
u32 gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g)
{
return gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r();
}
int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
int gp10b_gr_zbc_add_color(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *color_val, u32 index)
{
u32 i;
u32 zbc_c;
u32 zbc_c_format_reg =
g->ops.gr.zbc.get_gpcs_swdx_dss_zbc_c_format_reg(g);
/* update l2 table */
g->ops.ltc.set_zbc_color_entry(g, color_val, index);
/* update local copy */
for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) {
gr->zbc_col_tbl[index].color_l2[i] = color_val->color_l2[i];
gr->zbc_col_tbl[index].color_ds[i] = color_val->color_ds[i];
}
gr->zbc_col_tbl[index].format = color_val->format;
gr->zbc_col_tbl[index].ref_cnt++;
nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_r_r(index),
color_val->color_ds[0]);
nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_g_r(index),
@@ -561,31 +549,23 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
return 0;
}
u32 gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g)
u32 gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g)
{
return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r();
}
int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
int gp10b_gr_zbc_add_depth(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index)
{
u32 zbc_z;
u32 zbc_z_format_reg =
g->ops.gr.zbc.get_gpcs_swdx_dss_zbc_z_format_reg(g);
/* update l2 table */
g->ops.ltc.set_zbc_depth_entry(g, depth_val, index);
/* update local copy */
gr->zbc_dep_tbl[index].depth = depth_val->depth;
gr->zbc_dep_tbl[index].format = depth_val->format;
gr->zbc_dep_tbl[index].ref_cnt++;
gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth);
zbc_z = gk20a_readl(g, zbc_z_format_reg + (index & ~3U));
nvgpu_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth);
zbc_z = nvgpu_readl(g, zbc_z_format_reg + (index & ~3U));
zbc_z &= ~(U32(0x7f) << (index % 4U) * 7U);
zbc_z |= depth_val->format << (index % 4U) * 7U;
gk20a_writel(g, zbc_z_format_reg + (index & ~3U), zbc_z);
nvgpu_writel(g, zbc_z_format_reg + (index & ~3U), zbc_z);
return 0;
}

8
drivers/gpu/nvgpu/gp10b/gr_gp10b.h
View File

@@ -77,11 +77,11 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
void gr_gp10b_commit_global_pagepool(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx,
u64 addr, u32 size, bool patch);
u32 gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g);
u32 gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g);
int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
u32 gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g);
u32 gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g);
int gp10b_gr_zbc_add_color(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *color_val, u32 index);
int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
int gp10b_gr_zbc_add_depth(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index);
u32 gr_gp10b_pagepool_default_size(struct gk20a *g);
u32 gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g);

12
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -454,19 +454,19 @@ static const struct gpu_ops gp10b_ops = {
gm20b_gr_config_get_pd_dist_skip_table_size,
},
.zbc = {
.add_color = gr_gp10b_add_zbc_color,
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.add_color = gp10b_gr_zbc_add_color,
.add_depth = gp10b_gr_zbc_add_depth,
.set_table = nvgpu_gr_zbc_set_table,
.query_table = nvgpu_gr_zbc_query_table,
.stencil_query_table = NULL,
.load_stencil_default_tbl = NULL,
.add_type_stencil = NULL,
.load_stencil_tbl = NULL,
.add_stencil = NULL,
.get_gpcs_swdx_dss_zbc_c_format_reg =
gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg,
gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg,
.get_gpcs_swdx_dss_zbc_z_format_reg =
gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg,
gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg,
}
},
.fb = {

8
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -580,10 +580,10 @@ static const struct gpu_ops gv100_ops = {
gm20b_gr_config_get_pd_dist_skip_table_size,
},
.zbc = {
.add_color = gr_gp10b_add_zbc_color,
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.add_color = gp10b_gr_zbc_add_color,
.add_depth = gp10b_gr_zbc_add_depth,
.set_table = nvgpu_gr_zbc_set_table,
.query_table = nvgpu_gr_zbc_query_table,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,

8
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -539,10 +539,10 @@ static const struct gpu_ops gv11b_ops = {
gm20b_gr_config_get_pd_dist_skip_table_size,
},
.zbc = {
.add_color = gr_gp10b_add_zbc_color,
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.add_color = gp10b_gr_zbc_add_color,
.add_depth = gp10b_gr_zbc_add_depth,
.set_table = nvgpu_gr_zbc_set_table,
.query_table = nvgpu_gr_zbc_query_table,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,

8
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -604,10 +604,10 @@ static const struct gpu_ops tu104_ops = {
gm20b_gr_config_get_pd_dist_skip_table_size,
},
.zbc = {
.add_color = gr_gp10b_add_zbc_color,
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.add_color = gp10b_gr_zbc_add_color,
.add_depth = gp10b_gr_zbc_add_depth,
.set_table = nvgpu_gr_zbc_set_table,
.query_table = nvgpu_gr_zbc_query_table,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,