gpu: nvgpu: fix MISRA 10.5 issue in syncpt code

This change switches nvgpu_nvhost_syncpt_is_expired_ext()
to return a bool instead of an int to remove advisory rule
MISRA 10.5 violations.

MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.

JIRA NVGPU-3798

Change-Id: Ie0772ac7167a3c999129de0dc7f22cd96faa28fc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159801
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Scott Long
2019-07-23 14:49:21 -07:00
committed by mobile promotions
parent 8f99fe87d9
commit 93a74d6700
3 changed files with 4 additions and 4 deletions

View File

@@ -41,7 +41,7 @@ void nvgpu_nvhost_module_idle_ext(struct nvgpu_nvhost_dev *nvhost_dev);
void nvgpu_nvhost_debug_dump_device(struct nvgpu_nvhost_dev *nvhost_dev);
int nvgpu_nvhost_syncpt_is_expired_ext(struct nvgpu_nvhost_dev *nvhost_dev,
bool nvgpu_nvhost_syncpt_is_expired_ext(struct nvgpu_nvhost_dev *nvhost_dev,
u32 id, u32 thresh);
int nvgpu_nvhost_syncpt_wait_timeout_ext(struct nvgpu_nvhost_dev *nvhost_dev,
u32 id, u32 thresh, u32 timeout, u32 *value, struct timespec *ts);

View File

@@ -97,7 +97,7 @@ bool nvgpu_nvhost_syncpt_is_valid_pt_ext(
return nvhost_syncpt_is_valid_pt_ext(nvhost_dev->host1x_pdev, id);
}
int nvgpu_nvhost_syncpt_is_expired_ext(
bool nvgpu_nvhost_syncpt_is_expired_ext(
struct nvgpu_nvhost_dev *nvhost_dev, u32 id, u32 thresh)
{
return nvhost_syncpt_is_expired_ext(nvhost_dev->host1x_pdev,

View File

@@ -68,11 +68,11 @@ bool nvgpu_nvhost_syncpt_is_valid_pt_ext(
return false;
}
int nvgpu_nvhost_syncpt_is_expired_ext(
bool nvgpu_nvhost_syncpt_is_expired_ext(
struct nvgpu_nvhost_dev *nvhost_dev, u32 id, u32 thresh)
{
BUG();
return 0;
return false;
}
u32 nvgpu_nvhost_syncpt_incr_max_ext(