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gpu: nvgpu: add new hal.gr.init HAL to reset sys/gpc/be units

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gr_gk20a_init_golden_ctx_image() right now resets sys/gpc/be units by
directly accessing gr_fecs_ctxsw_reset_ctl_r() register

Move this register write/read sequence to common.hal.gr.init unit
through HAL operation g->ops.gr.init.override_context_reset()

Use new HAL in gr_gk20a_init_golden_ctx_image()

Also fix the delay() operations. delay() should be added before we read
back gr_fecs_ctxsw_reset_ctl_r() register and not after

Jira NVGPU-2961

Change-Id: I70d3a61b5aa60846815dee52ecac544066542695
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070608
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-03-12 16:04:11 +05:30
committed by mobile promotions
parent c4534b5ee3
commit 95f47ac13c
9 changed files with 46 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -1232,31 +1232,7 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
goto clean_up;
}
gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(),
gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() |
gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f());
(void) gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
nvgpu_udelay(10);
gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(),
gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f());
(void) gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
nvgpu_udelay(10);
g->ops.gr.init.override_context_reset(g);
err = g->ops.gr.init.fe_pwr_mode_force_on(g, false);
if (err != 0) {

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -426,6 +426,8 @@ static const struct gpu_ops gm20b_ops = {
.init = {
.fe_pwr_mode_force_on =
gm20b_gr_init_fe_pwr_mode_force_on,
.override_context_reset =
gm20b_gr_init_override_context_reset,
},
},
.fb = {

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -475,6 +475,8 @@ static const struct gpu_ops gp10b_ops = {
.init = {
.fe_pwr_mode_force_on =
gm20b_gr_init_fe_pwr_mode_force_on,
.override_context_reset =
gm20b_gr_init_override_context_reset,
},
},
.fb = {

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -611,6 +611,8 @@ static const struct gpu_ops gv100_ops = {
.init = {
.fe_pwr_mode_force_on =
gm20b_gr_init_fe_pwr_mode_force_on,
.override_context_reset =
gm20b_gr_init_override_context_reset,
},
},
.fb = {

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -568,6 +568,8 @@ static const struct gpu_ops gv11b_ops = {
.init = {
.fe_pwr_mode_force_on =
gm20b_gr_init_fe_pwr_mode_force_on,
.override_context_reset =
gm20b_gr_init_override_context_reset,
},
},
.fb = {

33
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
View File

@@ -31,6 +31,7 @@
#define FE_PWR_MODE_TIMEOUT_MAX_US 2000U
#define FE_PWR_MODE_TIMEOUT_DEFAULT_US 10U
#define FECS_CTXSW_RESET_DELAY_US 10U
int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on)
{
@@ -71,3 +72,35 @@ int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on)
return ret;
}
void gm20b_gr_init_override_context_reset(struct gk20a *g)
{
nvgpu_writel(g, gr_fecs_ctxsw_reset_ctl_r(),
gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() |
gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f());
nvgpu_udelay(FECS_CTXSW_RESET_DELAY_US);
(void) nvgpu_readl(g, gr_fecs_ctxsw_reset_ctl_r());
/* Deassert reset */
nvgpu_writel(g, gr_fecs_ctxsw_reset_ctl_r(),
gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() |
gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() |
gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f());
nvgpu_udelay(FECS_CTXSW_RESET_DELAY_US);
(void) nvgpu_readl(g, gr_fecs_ctxsw_reset_ctl_r());
}

1
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h
View File

@@ -28,5 +28,6 @@
struct gk20a;
int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on);
void gm20b_gr_init_override_context_reset(struct gk20a *g);
#endif /* NVGPU_GR_INIT_GM20B_H */

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -638,6 +638,7 @@ struct gpu_ops {
struct {
int (*fe_pwr_mode_force_on)(struct gk20a *g,
bool force_on);
void (*override_context_reset)(struct gk20a *g);
} init;
u32 (*fecs_falcon_base_addr)(void);

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -637,6 +637,8 @@ static const struct gpu_ops tu104_ops = {
.init = {
.fe_pwr_mode_force_on =
gm20b_gr_init_fe_pwr_mode_force_on,
.override_context_reset =
gm20b_gr_init_override_context_reset,
},
},
.fb = {