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95f47ac13c
gr_gk20a_init_golden_ctx_image() right now resets sys/gpc/be units by directly accessing gr_fecs_ctxsw_reset_ctl_r() register Move this register write/read sequence to common.hal.gr.init unit through HAL operation g->ops.gr.init.override_context_reset() Use new HAL in gr_gk20a_init_golden_ctx_image() Also fix the delay() operations. delay() should be added before we read back gr_fecs_ctxsw_reset_ctl_r() register and not after Jira NVGPU-2961 Change-Id: I70d3a61b5aa60846815dee52ecac544066542695 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2070608 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>