gpu: nvgpu: remove NVC0C0_SET_SHADER_EXCEPTIONS from gr intr test

Remove unused NVC0C0_SET_SHADER_EXCEPTIONS from gr intr unit test.
Update the mock io register with valid class number value.

Jira NVGPU-4454

Change-Id: I1b6772c7c8d2c75f05d57cb5eb2a630aa7b6b6e0
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2275286
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vinodg
2020-01-07 12:59:59 -08:00
committed by Alex Waterman
parent b662fdfaf7
commit 97ce51215b

View File

@@ -499,21 +499,16 @@ int test_gr_intr_without_channel(struct unit_module *m,
struct test_gr_intr_sw_mthd_exceptions sw_excep[] = {
[0] = {
.trapped_addr = NVC0C0_SET_SHADER_EXCEPTIONS,
.data[0] = NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE,
.data[1] = NVA297_SET_SHADER_EXCEPTIONS_ENABLE_TRUE,
},
[1] = {
.trapped_addr = NVC3C0_SET_SKEDCHECK,
.data[0] = NVC397_SET_SKEDCHECK_18_ENABLE,
.data[1] = NVC397_SET_SKEDCHECK_18_DISABLE,
},
[2] = {
[1] = {
.trapped_addr = NVC3C0_SET_SHADER_CUT_COLLECTOR,
.data[0] = NVC397_SET_SHADER_CUT_COLLECTOR_STATE_ENABLE,
.data[1] = NVC397_SET_SHADER_CUT_COLLECTOR_STATE_DISABLE,
},
[3] = {
[2] = {
.trapped_addr = 0,
.data[0] = 0,
.data[1] = 0,
@@ -533,6 +528,10 @@ int test_gr_intr_sw_exceptions(struct unit_module *m,
gr_intr_illegal_method_pending_f() |
gr_intr_class_error_pending_f());
/* valid class num */
nvgpu_posix_io_writel_reg_space(g,
gr_fe_object_table_r(0), VOLTA_COMPUTE_A);
for (i = 0; i < arry_cnt; i++) {
/* method & sub channel */
nvgpu_posix_io_writel_reg_space(g, gr_trapped_addr_r(),