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gpu: nvgpu: fix MISRA errors in runlist
Fix some mistakes from commit0fbc1a2652(gpu: nvgpu: avoid recursion in runlist construction) and commit998bf379df(gpu: nvgpu: add runlist_append_tsg) for MISRA rules 10.3 and 10.4. - cast a sizeof to u32 in a calculation to match in size, - make the NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* constants unsigned to make comparisons match in signedness. Jira NVGPU-1174 Change-Id: I00aa9758ca4352d8eb53a0e8ded42a1ba3b14561 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1938069 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -3330,7 +3330,7 @@ static u32 nvgpu_runlist_append_tsg(struct gk20a *g,
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struct tsg_gk20a *tsg)
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{
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struct fifo_gk20a *f = &g->fifo;
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u32 runlist_entry_words = f->runlist_entry_size / sizeof(u32);
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u32 runlist_entry_words = f->runlist_entry_size / (u32)sizeof(u32);
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struct channel_gk20a *ch;
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u32 count = 0;
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@@ -32,12 +32,10 @@ struct nvgpu_semaphore;
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struct channel_gk20a;
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struct tsg_gk20a;
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enum {
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NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW = 0U,
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NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM = 1U,
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NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH = 2U,
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NVGPU_FIFO_RUNLIST_INTERLEAVE_NUM_LEVELS = 3U,
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};
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#define NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW 0U
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#define NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM 1U
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#define NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH 2U
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#define NVGPU_FIFO_RUNLIST_INTERLEAVE_NUM_LEVELS 3U
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#define MAX_RUNLIST_BUFFERS 2
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