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gpu: nvgpu: fix MISRA errors in runlist

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Fix some mistakes from commit 0fbc1a2652 (gpu: nvgpu: avoid recursion in
runlist construction) and commit 998bf379df (gpu: nvgpu: add
runlist_append_tsg) for MISRA rules 10.3 and 10.4.

- cast a sizeof to u32 in a calculation to match in size,
- make the NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* constants unsigned to make
  comparisons match in signedness.

Jira NVGPU-1174

Change-Id: I00aa9758ca4352d8eb53a0e8ded42a1ba3b14561
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1938069
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2018-10-30 17:29:05 +02:00
committed by mobile promotions
parent e2c08f4f7b
commit 9adc7a6542
2 changed files with 5 additions and 7 deletions
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10
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
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@@ -32,12 +32,10 @@ struct nvgpu_semaphore;
struct channel_gk20a;
struct tsg_gk20a;
enum {
NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW = 0U,
NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM = 1U,
NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH = 2U,
NVGPU_FIFO_RUNLIST_INTERLEAVE_NUM_LEVELS = 3U,
};
#define NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW 0U
#define NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM 1U
#define NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH 2U
#define NVGPU_FIFO_RUNLIST_INTERLEAVE_NUM_LEVELS 3U
#define MAX_RUNLIST_BUFFERS 2