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gpu: nvgpu: Rename TPC powergating mutex

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Rename tpc_pg_lock to static_pg_lock and
have_tpc_pg_lock to have_static_pg_lock as it
is used for tpc/gpc/fbp power gating.

JIRA NVGPU-6433

Change-Id: I4c56b9710e303ad9e872bad4b5ed9a167acb9dd6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2537489
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2021-05-31 20:30:49 +05:30
committed by mobile promotions
parent 22c3ce37a7
commit 9f30609550
13 changed files with 48 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/Makefile
View File

@@ -44,7 +44,7 @@ ccflags-y += -DCONFIG_NVGPU_ENGINE_RESET
endif
ccflags-y += -DCONFIG_NVGPU_DETERMINISTIC_CHANNELS
ccflags-y += -DCONFIG_NVGPU_TPC_POWERGATE
ccflags-y += -DCONFIG_NVGPU_STATIC_POWERGATE
ccflags-y += -DCONFIG_NVGPU_ACR_LEGACY
ccflags-y += -DCONFIG_NVGPU_ENGINE_QUEUE
ccflags-y += -DCONFIG_NVGPU_FIFO_ENGINE_ACTIVITY

6
drivers/gpu/nvgpu/Makefile.shared.configs
View File

@@ -195,9 +195,9 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_USE_3LSS_ERR_INJECTION
CONFIG_NVGPU_NVLINK := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_NVLINK
# Enable tpc_powergate support for normal build.
CONFIG_NVGPU_TPC_POWERGATE := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_TPC_POWERGATE
# Enable static_powergate support for normal build.
CONFIG_NVGPU_STATIC_POWERGATE := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_STATIC_POWERGATE
# Enable mssnvlink0 reset control for normal build
CONFIG_MSSNVLINK0_RST_CONTROL := 1

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -726,7 +726,7 @@ ifeq ($(CONFIG_NVGPU_NON_FUSA),1)
srcs += common/power_features/power_features.c
endif
ifeq ($(CONFIG_NVGPU_TPC_POWERGATE),1)
ifeq ($(CONFIG_NVGPU_STATIC_POWERGATE),1)
srcs += hal/tpc/tpc_gv11b.c
endif

34
drivers/gpu/nvgpu/common/init/nvgpu_init.c
View File

@@ -377,20 +377,20 @@ int nvgpu_prepare_poweroff(struct gk20a *g)
return ret;
}
#ifdef CONFIG_NVGPU_TPC_POWERGATE
static bool have_tpc_pg_lock = false;
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
static bool have_static_pg_lock = false;
static int nvgpu_init_acquire_tpc_pg_lock(struct gk20a *g)
static int nvgpu_init_acquire_static_pg_lock(struct gk20a *g)
{
nvgpu_mutex_acquire(&g->tpc_pg_lock);
have_tpc_pg_lock = true;
nvgpu_mutex_acquire(&g->static_pg_lock);
have_static_pg_lock = true;
return 0;
}
static int nvgpu_init_release_tpc_pg_lock(struct gk20a *g)
static int nvgpu_init_release_static_pg_lock(struct gk20a *g)
{
nvgpu_mutex_release(&g->tpc_pg_lock);
have_tpc_pg_lock = false;
nvgpu_mutex_release(&g->static_pg_lock);
have_static_pg_lock = false;
return 0;
}
#endif
@@ -427,7 +427,7 @@ static int nvgpu_init_fbpa_ecc(struct gk20a *g)
}
#endif
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
static int nvgpu_init_power_gate(struct gk20a *g)
{
int err;
@@ -793,9 +793,9 @@ int nvgpu_finalize_poweron(struct gk20a *g)
NVGPU_INIT_TABLE_ENTRY(g->ops.fifo.fifo_init_support, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(g->ops.therm.elcg_init_idle_filters,
NO_FLAG),
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_power_gate, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_acquire_tpc_pg_lock, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_acquire_static_pg_lock, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_power_gate_gr, NO_FLAG),
#endif
NVGPU_INIT_TABLE_ENTRY(&nvgpu_netlist_init_ctx_vars, NO_FLAG),
@@ -826,8 +826,8 @@ int nvgpu_finalize_poweron(struct gk20a *g)
*/
NVGPU_INIT_TABLE_ENTRY(g->ops.ecc.ecc_finalize_support,
NO_FLAG),
#ifdef CONFIG_NVGPU_TPC_POWERGATE
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_release_tpc_pg_lock,
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_release_static_pg_lock,
NO_FLAG),
#endif
@@ -886,12 +886,12 @@ int nvgpu_finalize_poweron(struct gk20a *g)
return err;
done:
#ifdef CONFIG_NVGPU_TPC_POWERGATE
if (have_tpc_pg_lock) {
int release_err = nvgpu_init_release_tpc_pg_lock(g);
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
if (have_static_pg_lock) {
int release_err = nvgpu_init_release_static_pg_lock(g);
if (release_err != 0) {
nvgpu_err(g, "failed to release tpc_gp_lock");
nvgpu_err(g, "failed to release static_pg_lock");
}
}
#endif

4
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -1051,7 +1051,7 @@ static const struct gops_top gm20b_ops_top = {
.get_num_ltcs = gm20b_top_get_num_ltcs,
};
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
static const struct gops_tpc gm20b_ops_tpc = {
.init_tpc_powergate = NULL,
.tpc_gr_pg = NULL,
@@ -1168,7 +1168,7 @@ int gm20b_init_hal(struct gk20a *g)
gops->priv_ring = gm20b_ops_priv_ring;
gops->fuse = gm20b_ops_fuse;
gops->top = gm20b_ops_top;
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
gops->tpc = gm20b_ops_tpc;
#endif
gops->grmgr = gm20b_ops_grmgr;

4
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -1150,7 +1150,7 @@ static const struct gops_top gp10b_ops_top = {
.get_num_ltcs = gm20b_top_get_num_ltcs,
};
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
static const struct gops_tpc gp10b_ops_tpc = {
.init_tpc_powergate = NULL,
.tpc_gr_pg = NULL,
@@ -1257,7 +1257,7 @@ int gp10b_init_hal(struct gk20a *g)
gops->priv_ring = gp10b_ops_priv_ring;
gops->fuse = gp10b_ops_fuse;
gops->top = gp10b_ops_top;
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
gops->tpc = gp10b_ops_tpc;
#endif
gops->grmgr = gp10b_ops_grmgr;

6
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -191,7 +191,7 @@
#include "hal/cic/mon/cic_gv11b.h"
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
#include "hal/tpc/tpc_gv11b.h"
#endif
@@ -1429,7 +1429,7 @@ static const struct gops_top gv11b_ops_top = {
.get_num_lce = gv11b_top_get_num_lce,
};
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
static const struct gops_tpc gv11b_ops_tpc = {
.init_tpc_powergate = gv11b_tpc_powergate,
.tpc_gr_pg = gv11b_gr_pg_tpc,
@@ -1537,7 +1537,7 @@ int gv11b_init_hal(struct gk20a *g)
gops->priv_ring = gv11b_ops_priv_ring;
gops->fuse = gv11b_ops_fuse;
gops->top = gv11b_ops_top;
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
gops->tpc = gv11b_ops_tpc;
#endif
gops->grmgr = gv11b_ops_grmgr;

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -424,7 +424,7 @@ struct gk20a {
/** @cond DOXYGEN_SHOULD_SKIP_THIS */
u32 log_trace;
struct nvgpu_mutex tpc_pg_lock;
struct nvgpu_mutex static_pg_lock;
/** @endcond */
/** Stored HW version info */

4
drivers/gpu/nvgpu/include/nvgpu/gops/floorsweep.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,7 +22,7 @@
#ifndef NVGPU_GOPS_FLOORSWEEP_H
#define NVGPU_GOPS_FLOORSWEEP_H
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
struct gops_tpc {
int (*init_tpc_powergate)(struct gk20a *g, u32 fuse_status);
void (*tpc_gr_pg)(struct gk20a *g);

2
drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h
View File

@@ -218,7 +218,7 @@ struct gpu_ops {
struct gops_sec2 sec2;
struct gops_gsp gsp;
/** @endcond */
#ifdef CONFIG_NVGPU_TPC_POWERGATE
#ifdef CONFIG_NVGPU_STATIC_POWERGATE
struct gops_tpc tpc;
#endif
/** Wake up all threads waiting on semaphore wait. */

2
drivers/gpu/nvgpu/os/linux/driver_common.c
View File

@@ -70,7 +70,7 @@ static void nvgpu_init_vars(struct gk20a *g)
nvgpu_mutex_init(&g->dbg_sessions_lock);
nvgpu_mutex_init(&g->client_lock);
nvgpu_mutex_init(&g->power_lock);
nvgpu_mutex_init(&g->tpc_pg_lock);
nvgpu_mutex_init(&g->static_pg_lock);
nvgpu_mutex_init(&g->clk_arb_enable_lock);
nvgpu_mutex_init(&g->cg_pg_lock);
#if defined(CONFIG_NVGPU_CYCLESTATS)

10
drivers/gpu/nvgpu/os/linux/sysfs.c
View File

@@ -863,11 +863,11 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
unsigned long val = 0;
struct nvgpu_gr_obj_ctx_golden_image *gr_golden_image = NULL;
nvgpu_mutex_acquire(&g->tpc_pg_lock);
nvgpu_mutex_acquire(&g->static_pg_lock);
if (kstrtoul(buf, 10, &val) < 0) {
nvgpu_err(g, "invalid value");
nvgpu_mutex_release(&g->tpc_pg_lock);
nvgpu_mutex_release(&g->static_pg_lock);
return -EINVAL;
}
@@ -884,7 +884,7 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
nvgpu_gr_obj_ctx_get_golden_image_size(gr_golden_image)
!= 0) {
nvgpu_err(g, "golden image size already initialized");
nvgpu_mutex_release(&g->tpc_pg_lock);
nvgpu_mutex_release(&g->static_pg_lock);
return -ENODEV;
}
/* checking that the value from userspace is within
@@ -894,11 +894,11 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
g->tpc_pg_mask = val;
} else {
nvgpu_err(g, "TPC-PG mask is invalid");
nvgpu_mutex_release(&g->tpc_pg_lock);
nvgpu_mutex_release(&g->static_pg_lock);
return -EINVAL;
}
exit:
nvgpu_mutex_release(&g->tpc_pg_lock);
nvgpu_mutex_release(&g->static_pg_lock);
return count;
}

18
userspace/units/acr/nvgpu-acr.c
View File

@@ -340,7 +340,7 @@ static int prepare_gr_hw_sw(struct unit_module *m, struct gk20a *g)
err = nvgpu_gr_enable_hw(g);
if (err != 0) {
nvgpu_mutex_release(&g->tpc_pg_lock);
nvgpu_mutex_release(&g->static_pg_lock);
unit_return_fail(m, "failed to enable gr");
}
@@ -399,7 +399,7 @@ int test_acr_bootstrap_hs_acr(struct unit_module *m,
return -ENOMEM;
}
nvgpu_mutex_acquire(&g->tpc_pg_lock);
nvgpu_mutex_acquire(&g->static_pg_lock);
/*
* Prepare HW and SW setup needed
@@ -598,7 +598,7 @@ int test_acr_bootstrap_hs_acr(struct unit_module *m,
as expected\n");
}
nvgpu_mutex_release(&g->tpc_pg_lock);
nvgpu_mutex_release(&g->static_pg_lock);
return UNIT_SUCCESS;
}
@@ -619,7 +619,7 @@ int test_acr_construct_execute(struct unit_module *m,
unit_return_fail(m, "Test env init failed\n");
}
nvgpu_mutex_acquire(&g->tpc_pg_lock);
nvgpu_mutex_acquire(&g->static_pg_lock);
/*
* Prepare HW and SW setup needed for the test
@@ -693,7 +693,7 @@ int test_acr_construct_execute(struct unit_module *m,
unit_return_fail(m, "Bootstrap HS ACR didn't failed as \
expected\n");
}
nvgpu_mutex_release(&g->tpc_pg_lock);
nvgpu_mutex_release(&g->static_pg_lock);
return UNIT_SUCCESS;
}
@@ -712,7 +712,7 @@ int test_acr_is_lsf_lazy_bootstrap(struct unit_module *m,
}
nvgpu_mutex_acquire(&g->tpc_pg_lock);
nvgpu_mutex_acquire(&g->static_pg_lock);
/*
* Prepare HW and SW setup needed for the test
@@ -762,7 +762,7 @@ int test_acr_is_lsf_lazy_bootstrap(struct unit_module *m,
expected\n");
}
nvgpu_mutex_release(&g->tpc_pg_lock);
nvgpu_mutex_release(&g->static_pg_lock);
return UNIT_SUCCESS;
}
@@ -782,7 +782,7 @@ int test_acr_prepare_ucode_blob(struct unit_module *m,
unit_return_fail(m, "Test env init failed\n");
}
nvgpu_mutex_acquire(&g->tpc_pg_lock);
nvgpu_mutex_acquire(&g->static_pg_lock);
/*
* Prepare HW and SW setup needed for the test
@@ -882,7 +882,7 @@ int test_acr_prepare_ucode_blob(struct unit_module *m,
unit_return_fail(m, "prepare_ucode_blob test failed\n");
}
nvgpu_mutex_release(&g->tpc_pg_lock);
nvgpu_mutex_release(&g->static_pg_lock);
return UNIT_SUCCESS;
}