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gpu: nvgpu: patch SMPC only for main context image

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In __gr_gk20a_exec_ctx_ops(), we right now call gr_gk20a_ctx_patch_smpc()
even if operations are on pm_ctx image which is incorrect since this is
only required for SMPC operations on main context image

Fix this by not calling gr_gk20a_ctx_patch_smpc() for pm_ctx image

Jira NVGPU-1527
Jira NVGPU-1613

Change-Id: I5111fb0e6ea1f329750b42a37a98f5c006b47deb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011095
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-01-24 18:11:02 +05:30
committed by mobile promotions
parent 5b2eb887d5
commit a3068cebc6
1 changed files with 7 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -5601,7 +5601,6 @@ void gk20a_gr_init_ovr_sm_dsm_perf(void)
static int gr_gk20a_ctx_patch_smpc(struct gk20a *g,
struct channel_gk20a *ch,
u32 addr, u32 data,
struct nvgpu_mem *mem,
struct nvgpu_gr_ctx *gr_ctx)
{
u32 num_gpc = nvgpu_gr_config_get_gpc_count(g->gr.config);
@@ -7018,11 +7017,13 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
offsets[j] + 4U, v);
}
/* check to see if we need to add a special WAR
for some of the SMPC perf regs */
gr_gk20a_ctx_patch_smpc(g, ch, offset_addrs[j],
v, current_mem, gr_ctx);
if (current_mem == &gr_ctx->mem) {
/* check to see if we need to add a special WAR
for some of the SMPC perf regs */
gr_gk20a_ctx_patch_smpc(g, ch,
offset_addrs[j],
v, gr_ctx);
}
} else { /* read pass */
ctx_ops[i].value_lo =
nvgpu_mem_rd(g, current_mem, offsets[0]);