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gpu: nvgpu: resolve pmu mismatches

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Add the following pmu HALs for PMU registers
to avoid duplication of code for future chips:
- get_bar0_addr
- get_bar0_data
- get_bar0_timeout
- get_bar0_ctl
- get_bar0_error_status
- set_bar0_error_status
- get_bar0_fecs_error
- set_bar0_fecs_error
- get_mailbox
- get_pmu_debug

JIRA NVGPU-9758

Change-Id: If8b9c91ecd51d526babf12e3cee09048d736f0f4
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2897156
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Divya
2023-05-02 10:32:59 +00:00
committed by mobile promotions
parent 811f8546cf
commit a4175b1265
10 changed files with 138 additions and 18 deletions
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10
drivers/gpu/nvgpu/hal/init/hal_tu104.c
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@@ -1242,6 +1242,16 @@ static const struct gops_pmu tu104_ops_pmu = {
.get_exterrstat = gk20a_pmu_get_exterrstat,
.set_exterrstat = gk20a_pmu_set_exterrstat,
.get_exterraddr = gk20a_pmu_get_exterraddr,
.get_bar0_addr = gk20a_pmu_get_bar0_addr,
.get_bar0_data = gk20a_pmu_get_bar0_data,
.get_bar0_timeout = gk20a_pmu_get_bar0_timeout,
.get_bar0_ctl = gk20a_pmu_get_bar0_ctl,
.get_bar0_error_status = gk20a_pmu_get_bar0_error_status,
.set_bar0_error_status = gk20a_pmu_set_bar0_error_status,
.get_bar0_fecs_error = gk20a_pmu_get_bar0_fecs_error,
.set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error,
.get_mailbox = gk20a_pmu_get_mailbox,
.get_pmu_debug = gk20a_pmu_get_pmu_debug,
.pmu_isr = gk20a_pmu_isr,
.pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter,
.pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config,