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gpu: nvgpu: fix MISRA violations in bitops unit

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Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset.  OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.

Jira NVGPU-3545

Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
ajesh
2019-06-03 16:39:32 +05:30
committed by mobile promotions
parent 57cee55ce7
commit a6cbfca58c
22 changed files with 158 additions and 101 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/nvgpu-linux.yaml
View File

@@ -224,6 +224,7 @@ headers:
include/nvgpu/linux/dma.h, include/nvgpu/linux/dma.h,
include/nvgpu/linux/kmem.h, include/nvgpu/linux/kmem.h,
include/nvgpu/linux/lock.h, include/nvgpu/linux/lock.h,
include/nvgpu/linux/bitops.h,
include/nvgpu/linux/nvgpu_mem.h, include/nvgpu/linux/nvgpu_mem.h,
include/nvgpu/linux/os_fence_android.h, include/nvgpu/linux/os_fence_android.h,
include/nvgpu/linux/rwsem.h, include/nvgpu/linux/rwsem.h,

2
drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c
View File

@@ -367,7 +367,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g,
* image info and total falcon count * image info and total falcon count
*/ */
for (i = 0U; i < FALCON_ID_END; i++) { for (i = 0U; i < FALCON_ID_END; i++) {
if (test_bit((int)i, (void *)&acr->lsf_enable_mask) && if (nvgpu_test_bit(i, (void *)&acr->lsf_enable_mask) &&
acr->lsf[i].get_lsf_ucode_details != NULL) { acr->lsf[i].get_lsf_ucode_details != NULL) {
(void) memset(&ucode_img, 0, sizeof(ucode_img)); (void) memset(&ucode_img, 0, sizeof(ucode_img));

2
drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c
View File

@@ -477,7 +477,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g,
* image info and total falcon count * image info and total falcon count
*/ */
for (i = 0U; i < FALCON_ID_END; i++) { for (i = 0U; i < FALCON_ID_END; i++) {
if (test_bit((int)i, (void *)&acr->lsf_enable_mask) && if (nvgpu_test_bit(i, (void *)&acr->lsf_enable_mask) &&
acr->lsf[i].get_lsf_ucode_details != NULL) { acr->lsf[i].get_lsf_ucode_details != NULL) {
(void) memset(&ucode_img, 0, sizeof(ucode_img)); (void) memset(&ucode_img, 0, sizeof(ucode_img));

8
drivers/gpu/nvgpu/common/engine_queues/engine_fb_queue.c
View File

@@ -134,7 +134,7 @@ static int engine_fb_queue_set_element_use_state(
goto exit; goto exit;
} }
if (test_bit((int)queue_pos, if (nvgpu_test_bit(queue_pos,
(void *)&queue->fbq.element_in_use) && set) { (void *)&queue->fbq.element_in_use) && set) {
nvgpu_err(queue->g, nvgpu_err(queue->g,
"FBQ last received queue element not processed yet" "FBQ last received queue element not processed yet"
@@ -144,9 +144,9 @@ static int engine_fb_queue_set_element_use_state(
} }
if (set) { if (set) {
set_bit((int)queue_pos, (void *)&queue->fbq.element_in_use); nvgpu_set_bit(queue_pos, (void *)&queue->fbq.element_in_use);
} else { } else {
clear_bit((int)queue_pos, (void *)&queue->fbq.element_in_use); nvgpu_clear_bit(queue_pos, (void *)&queue->fbq.element_in_use);
} }
exit: exit:
@@ -164,7 +164,7 @@ static int engine_fb_queue_is_element_in_use(
goto exit; goto exit;
} }
*in_use = test_bit((int)queue_pos, (void *)&queue->fbq.element_in_use); *in_use = nvgpu_test_bit(queue_pos, (void *)&queue->fbq.element_in_use);
exit: exit:
return err; return err;

10
drivers/gpu/nvgpu/common/fifo/runlist.c
View File

@@ -100,7 +100,7 @@ static u32 nvgpu_runlist_append_tsg(struct gk20a *g,
/* add runnable channels bound to this TSG */ /* add runnable channels bound to this TSG */
nvgpu_list_for_each_entry(ch, &tsg->ch_list, nvgpu_list_for_each_entry(ch, &tsg->ch_list,
nvgpu_channel, ch_entry) { nvgpu_channel, ch_entry) {
if (!test_bit((int)ch->chid, if (!nvgpu_test_bit(ch->chid,
runlist->active_channels)) { runlist->active_channels)) {
continue; continue;
} }
@@ -337,24 +337,24 @@ static bool gk20a_runlist_modify_active_locked(struct gk20a *g, u32 runlist_id,
} }
if (add) { if (add) {
if (test_and_set_bit((int)ch->chid, if (nvgpu_test_and_set_bit(ch->chid,
runlist->active_channels)) { runlist->active_channels)) {
/* was already there */ /* was already there */
return false; return false;
} else { } else {
/* new, and belongs to a tsg */ /* new, and belongs to a tsg */
set_bit((int)tsg->tsgid, runlist->active_tsgs); nvgpu_set_bit(tsg->tsgid, runlist->active_tsgs);
tsg->num_active_channels++; tsg->num_active_channels++;
} }
} else { } else {
if (!test_and_clear_bit((int)ch->chid, if (!nvgpu_test_and_clear_bit(ch->chid,
runlist->active_channels)) { runlist->active_channels)) {
/* wasn't there */ /* wasn't there */
return false; return false;
} else { } else {
if (--tsg->num_active_channels == 0U) { if (--tsg->num_active_channels == 0U) {
/* was the only member of this tsg */ /* was the only member of this tsg */
clear_bit((int)tsg->tsgid, nvgpu_clear_bit(tsg->tsgid,
runlist->active_tsgs); runlist->active_tsgs);
} }
} }

2
drivers/gpu/nvgpu/common/fifo/tsg.c
View File

@@ -72,7 +72,7 @@ static bool gk20a_is_channel_active(struct gk20a *g, struct nvgpu_channel *ch)
for (i = 0; i < f->num_runlists; ++i) { for (i = 0; i < f->num_runlists; ++i) {
runlist = &f->active_runlist_info[i]; runlist = &f->active_runlist_info[i];
if (test_bit((int)ch->chid, runlist->active_channels)) { if (nvgpu_test_bit(ch->chid, runlist->active_channels)) {
return true; return true;
} }
} }

6
drivers/gpu/nvgpu/common/mm/allocators/bitmap_allocator.c
View File

@@ -136,7 +136,7 @@ static void nvgpu_bitmap_free_fixed(struct nvgpu_allocator *na,
alloc_lock(na); alloc_lock(na);
nvgpu_assert(offs <= U32_MAX); nvgpu_assert(offs <= U32_MAX);
nvgpu_assert(blks <= (u32)INT_MAX); nvgpu_assert(blks <= (u32)INT_MAX);
bitmap_clear(a->bitmap, (u32)offs, (int)blks); nvgpu_bitmap_clear(a->bitmap, (u32)offs, (u32)blks);
a->bytes_freed += blks * a->blk_size; a->bytes_freed += blks * a->blk_size;
alloc_unlock(na); alloc_unlock(na);
@@ -275,7 +275,7 @@ static u64 nvgpu_bitmap_balloc(struct nvgpu_allocator *na, u64 len)
fail_reset_bitmap: fail_reset_bitmap:
nvgpu_assert(blks <= (u32)INT_MAX); nvgpu_assert(blks <= (u32)INT_MAX);
nvgpu_assert(offs <= U32_MAX); nvgpu_assert(offs <= U32_MAX);
bitmap_clear(a->bitmap, (u32)offs, (int)blks); nvgpu_bitmap_clear(a->bitmap, (u32)offs, blks);
fail: fail:
a->next_blk = 0; a->next_blk = 0;
alloc_unlock(na); alloc_unlock(na);
@@ -313,7 +313,7 @@ static void nvgpu_bitmap_free(struct nvgpu_allocator *na, u64 addr)
nvgpu_assert(blks <= (u32)INT_MAX); nvgpu_assert(blks <= (u32)INT_MAX);
nvgpu_assert(offs <= U32_MAX); nvgpu_assert(offs <= U32_MAX);
bitmap_clear(a->bitmap, (u32)offs, (int)blks); nvgpu_bitmap_clear(a->bitmap, (u32)offs, (u32)blks);
alloc_dbg(na, "Free 0x%-10llx", addr); alloc_dbg(na, "Free 0x%-10llx", addr);
a->bytes_freed += alloc->length; a->bytes_freed += alloc->length;

6
drivers/gpu/nvgpu/common/mm/gmmu/pd_cache.c
View File

@@ -223,7 +223,7 @@ static int nvgpu_pd_cache_alloc_new(struct gk20a *g,
* This allocates the very first PD table in the set of tables in this * This allocates the very first PD table in the set of tables in this
* nvgpu_pd_mem_entry. * nvgpu_pd_mem_entry.
*/ */
set_bit(0, pentry->alloc_map); nvgpu_set_bit(0U, pentry->alloc_map);
pentry->allocs = 1; pentry->allocs = 1;
/* /*
@@ -261,7 +261,7 @@ static int nvgpu_pd_cache_alloc_from_partial(struct gk20a *g,
/* Bit map full. Somethings wrong. */ /* Bit map full. Somethings wrong. */
nvgpu_assert(bit_offs < nr_bits); nvgpu_assert(bit_offs < nr_bits);
set_bit((int)bit_offs, pentry->alloc_map); nvgpu_set_bit((u32)bit_offs, pentry->alloc_map);
pentry->allocs += 1U; pentry->allocs += 1U;
/* /*
@@ -405,7 +405,7 @@ static void nvgpu_pd_cache_do_free(struct gk20a *g,
u32 bit = pd->mem_offs / pentry->pd_size; u32 bit = pd->mem_offs / pentry->pd_size;
/* Mark entry as free. */ /* Mark entry as free. */
clear_bit((int)bit, pentry->alloc_map); nvgpu_clear_bit(bit, pentry->alloc_map);
pentry->allocs -= 1U; pentry->allocs -= 1U;
if (pentry->allocs > 0U) { if (pentry->allocs > 0U) {

4
drivers/gpu/nvgpu/common/pmu/ipc/pmu_seq.c
View File

@@ -126,7 +126,7 @@ int nvgpu_pmu_seq_acquire(struct gk20a *g,
return -EAGAIN; return -EAGAIN;
} }
nvgpu_assert(index <= U32_MAX); nvgpu_assert(index <= U32_MAX);
set_bit((int)index, sequences->pmu_seq_tbl); nvgpu_set_bit((u32)index, sequences->pmu_seq_tbl);
nvgpu_mutex_release(&sequences->pmu_seq_lock); nvgpu_mutex_release(&sequences->pmu_seq_lock);
seq = &sequences->seq[index]; seq = &sequences->seq[index];
@@ -151,7 +151,7 @@ void nvgpu_pmu_seq_release(struct gk20a *g,
seq->out_payload = NULL; seq->out_payload = NULL;
nvgpu_mutex_acquire(&sequences->pmu_seq_lock); nvgpu_mutex_acquire(&sequences->pmu_seq_lock);
clear_bit((int)seq->id, sequences->pmu_seq_tbl); nvgpu_clear_bit(seq->id, sequences->pmu_seq_tbl);
nvgpu_mutex_release(&sequences->pmu_seq_lock); nvgpu_mutex_release(&sequences->pmu_seq_lock);
} }

4
drivers/gpu/nvgpu/common/sec2/ipc/sec2_seq.c
View File

@@ -87,7 +87,7 @@ int nvgpu_sec2_seq_acquire(struct gk20a *g,
} }
nvgpu_assert(index < U64(INT_MAX)); nvgpu_assert(index < U64(INT_MAX));
set_bit(index, sequences->sec2_seq_tbl); nvgpu_set_bit(index, sequences->sec2_seq_tbl);
nvgpu_mutex_release(&sequences->sec2_seq_lock); nvgpu_mutex_release(&sequences->sec2_seq_lock);
@@ -113,7 +113,7 @@ static void sec2_seq_release(struct sec2_sequences *sequences,
seq->out_payload = NULL; seq->out_payload = NULL;
nvgpu_mutex_acquire(&sequences->sec2_seq_lock); nvgpu_mutex_acquire(&sequences->sec2_seq_lock);
clear_bit(seq->id, sequences->sec2_seq_tbl); nvgpu_clear_bit(seq->id, sequences->sec2_seq_tbl);
nvgpu_mutex_release(&sequences->sec2_seq_lock); nvgpu_mutex_release(&sequences->sec2_seq_lock);
} }

4
drivers/gpu/nvgpu/common/semaphore/semaphore_hw.c
View File

@@ -69,7 +69,7 @@ int nvgpu_hw_semaphore_init(struct nvgpu_channel *ch)
return 0; return 0;
fail_free_idx: fail_free_idx:
clear_bit(hw_sema_idx, p->semas_alloced); nvgpu_clear_bit((u32)hw_sema_idx, p->semas_alloced);
fail: fail:
nvgpu_mutex_release(&p->pool_lock); nvgpu_mutex_release(&p->pool_lock);
return ret; return ret;
@@ -88,7 +88,7 @@ void nvgpu_hw_semaphore_free(struct nvgpu_channel *ch)
nvgpu_mutex_acquire(&p->pool_lock); nvgpu_mutex_acquire(&p->pool_lock);
clear_bit(idx, p->semas_alloced); nvgpu_clear_bit((u32)idx, p->semas_alloced);
nvgpu_kfree(ch->g, hw_sema); nvgpu_kfree(ch->g, hw_sema);
ch->hw_sema = NULL; ch->hw_sema = NULL;

2
drivers/gpu/nvgpu/common/semaphore/semaphore_pool.c
View File

@@ -213,7 +213,7 @@ static void nvgpu_semaphore_pool_free(struct nvgpu_ref *ref)
nvgpu_semaphore_sea_lock(s); nvgpu_semaphore_sea_lock(s);
nvgpu_list_del(&p->pool_list_entry); nvgpu_list_del(&p->pool_list_entry);
clear_bit((int)p->page_idx, s->pools_alloced); nvgpu_clear_bit((u32)p->page_idx, s->pools_alloced);
s->page_count--; s->page_count--;
nvgpu_semaphore_sea_unlock(s); nvgpu_semaphore_sea_unlock(s);

4
drivers/gpu/nvgpu/common/semaphore/semaphore_priv.h
View File

@@ -153,7 +153,7 @@ static inline int semaphore_bitmap_alloc(unsigned long *bitmap,
return -ENOSPC; return -ENOSPC;
} }
set_bit(idx, bitmap); nvgpu_set_bit((u32)idx, bitmap);
return (int)idx; return (int)idx;
} }
@@ -181,4 +181,4 @@ static inline bool nvgpu_semaphore_value_released(u32 goal, u32 racer)
return racer - goal < 0x80000000U; return racer - goal < 0x80000000U;
} }
#endif /* NVGPU_SEMAPHORE_PRIV_H */ #endif /* NVGPU_SEMAPHORE_PRIV_H */

6
drivers/gpu/nvgpu/common/utils/enabled.c
View File

@@ -50,14 +50,14 @@ void nvgpu_free_enabled_flags(struct gk20a *g)
bool nvgpu_is_enabled(struct gk20a *g, int flag) bool nvgpu_is_enabled(struct gk20a *g, int flag)
{ {
return test_bit(flag, g->enabled_flags); return nvgpu_test_bit((u32)flag, g->enabled_flags);
} }
void nvgpu_set_enabled(struct gk20a *g, int flag, bool state) void nvgpu_set_enabled(struct gk20a *g, int flag, bool state)
{ {
if (state) { if (state) {
set_bit(flag, g->enabled_flags); nvgpu_set_bit((u32)flag, g->enabled_flags);
} else { } else {
clear_bit(flag, g->enabled_flags); nvgpu_clear_bit((u32)flag, g->enabled_flags);
} }
} }

4
drivers/gpu/nvgpu/common/vgpu/fifo/runlist_vgpu.c
View File

@@ -82,13 +82,13 @@ static bool vgpu_runlist_modify_active_locked(struct gk20a *g, u32 runlist_id,
runlist = f->runlist_info[runlist_id]; runlist = f->runlist_info[runlist_id];
if (add) { if (add) {
if (test_and_set_bit((int)ch->chid, if (nvgpu_test_and_set_bit(ch->chid,
runlist->active_channels)) { runlist->active_channels)) {
return false; return false;
/* was already there */ /* was already there */
} }
} else { } else {
if (!test_and_clear_bit((int)ch->chid, if (!nvgpu_test_and_clear_bit(ch->chid,
runlist->active_channels)) { runlist->active_channels)) {
/* wasn't there */ /* wasn't there */
return false; return false;

17
drivers/gpu/nvgpu/include/nvgpu/bitops.h
View File

@@ -35,8 +35,7 @@
#define BIT64(i) (U64(1) << U64(i)) #define BIT64(i) (U64(1) << U64(i))
#ifdef __KERNEL__ #ifdef __KERNEL__
#include <linux/bitops.h> #include <nvgpu/linux/bitops.h>
#include <linux/bitmap.h>
#else #else
#include <nvgpu/posix/bitops.h> #include <nvgpu/posix/bitops.h>
#endif #endif
@@ -48,18 +47,4 @@
*/ */
#define BITS_PER_BYTE_U32 8U #define BITS_PER_BYTE_U32 8U
static inline void nvgpu_bitmap_set(unsigned long *map, unsigned int start,
unsigned int len)
{
BUG_ON(len > U32(INT_MAX));
bitmap_set(map, start, (int)len);
}
static inline void nvgpu_bitmap_clear(unsigned long *map, unsigned int start,
unsigned int len)
{
BUG_ON(len > U32(INT_MAX));
bitmap_clear(map, start, (int)len);
}
#endif /* NVGPU_BITOPS_H */ #endif /* NVGPU_BITOPS_H */

70
drivers/gpu/nvgpu/include/nvgpu/linux/bitops.h Normal file
View File

@@ -0,0 +1,70 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef NVGPU_BITOPS_LINUX_H
#define NVGPU_BITOPS_LINUX_H
#include <linux/bitops.h>
#include <linux/bitmap.h>
static inline void nvgpu_bitmap_set(unsigned long *map, unsigned int start,
unsigned int len)
{
BUG_ON(len > U32(INT_MAX));
bitmap_set(map, start, (int)len);
}
static inline void nvgpu_bitmap_clear(unsigned long *map, unsigned int start,
unsigned int len)
{
BUG_ON(len > U32(INT_MAX));
bitmap_clear(map, start, (int)len);
}
static inline bool nvgpu_test_bit(unsigned int nr,
const volatile unsigned long *addr)
{
BUG_ON(nr > U32(INT_MAX));
return test_bit((int)nr, addr);
}
static inline bool nvgpu_test_and_set_bit(unsigned int nr,
volatile unsigned long *addr)
{
BUG_ON(nr > U32(INT_MAX));
return test_and_set_bit((int)nr, addr);
}
static inline bool nvgpu_test_and_clear_bit(unsigned int nr,
volatile unsigned long *addr)
{
BUG_ON(nr > U32(INT_MAX));
return test_and_clear_bit((int)nr, addr);
}
static inline void nvgpu_set_bit(unsigned int nr, volatile unsigned long *addr)
{
BUG_ON(nr > U32(INT_MAX));
set_bit((int)nr, addr);
}
static inline void nvgpu_clear_bit(unsigned int nr,
volatile unsigned long *addr)
{
BUG_ON(nr > U32(INT_MAX));
clear_bit((int)nr, addr);
}
#endif /* NVGPU_LOCK_LINUX_H */

14
drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h
View File

@@ -64,18 +64,18 @@ unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long find_first_zero_bit(const unsigned long *addr,
unsigned long size); unsigned long size);
bool test_bit(int nr, const volatile unsigned long *addr); bool nvgpu_test_bit(unsigned int nr, const volatile unsigned long *addr);
bool test_and_set_bit(int nr, volatile unsigned long *addr); bool nvgpu_test_and_set_bit(unsigned int nr, volatile unsigned long *addr);
bool test_and_clear_bit(int nr, volatile unsigned long *addr); bool nvgpu_test_and_clear_bit(unsigned int nr, volatile unsigned long *addr);
/* /*
* These two are atomic. * These two are atomic.
*/ */
void set_bit(int nr, volatile unsigned long *addr); void nvgpu_set_bit(unsigned int nr, volatile unsigned long *addr);
void clear_bit(int nr, volatile unsigned long *addr); void nvgpu_clear_bit(unsigned int nr, volatile unsigned long *addr);
void bitmap_set(unsigned long *map, unsigned int start, int len); void nvgpu_bitmap_set(unsigned long *map, unsigned int start, unsigned int len);
void bitmap_clear(unsigned long *map, unsigned int start, int len); void nvgpu_bitmap_clear(unsigned long *map, unsigned int start, unsigned int len);
unsigned long bitmap_find_next_zero_area_off(unsigned long *map, unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
unsigned long size, unsigned long size,
unsigned long start, unsigned long start,

14
drivers/gpu/nvgpu/libnvgpu-drv_safe.export
View File

@@ -1,11 +1,8 @@
# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. # Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
bitmap_clear
bitmap_find_next_zero_area_off bitmap_find_next_zero_area_off
bitmap_set
bug_handler_cancel bug_handler_cancel
bug_handler_register bug_handler_register
clear_bit
gv11b_fb_read_mmu_fault_buffer_size gv11b_fb_read_mmu_fault_buffer_size
gv11b_fb_read_mmu_fault_status gv11b_fb_read_mmu_fault_status
gv11b_fb_write_mmu_fault_buffer_lo_hi gv11b_fb_write_mmu_fault_buffer_lo_hi
@@ -62,6 +59,8 @@ nvgpu_allocator_init
nvgpu_aperture_mask nvgpu_aperture_mask
nvgpu_bar1_readl nvgpu_bar1_readl
nvgpu_bar1_writel nvgpu_bar1_writel
nvgpu_bitmap_clear
nvgpu_bitmap_set
nvgpu_bsearch nvgpu_bsearch
nvgpu_channel_alloc_inst nvgpu_channel_alloc_inst
nvgpu_channel_cleanup_sw nvgpu_channel_cleanup_sw
@@ -187,6 +186,7 @@ nvgpu_tsg_setup_sw
nvgpu_tsg_unbind_channel nvgpu_tsg_unbind_channel
nvgpu_tsg_unbind_channel_check_hw_state nvgpu_tsg_unbind_channel_check_hw_state
nvgpu_tsg_unbind_channel_check_ctx_reload nvgpu_tsg_unbind_channel_check_ctx_reload
nvgpu_set_bit
nvgpu_set_enabled nvgpu_set_enabled
nvgpu_set_pte nvgpu_set_pte
nvgpu_sgt_alignment nvgpu_sgt_alignment
@@ -215,8 +215,8 @@ nvgpu_vm_unmap
nvgpu_vzalloc_impl nvgpu_vzalloc_impl
nvgpu_writel nvgpu_writel
nvgpu_writel_check nvgpu_writel_check
set_bit nvgpu_clear_bit
test_and_clear_bit nvgpu_test_bit
test_and_set_bit nvgpu_test_and_clear_bit
test_bit nvgpu_test_and_set_bit
vm_aspace_id vm_aspace_id

51
drivers/gpu/nvgpu/os/posix/bitmap.c
View File

@@ -33,7 +33,7 @@
unsigned long nvgpu_posix_ffs(unsigned long word) unsigned long nvgpu_posix_ffs(unsigned long word)
{ {
return (unsigned long)__builtin_ffsl(word); return (unsigned long)__builtin_ffsl((signed long)word);
} }
unsigned long nvgpu_posix_fls(unsigned long word) unsigned long nvgpu_posix_fls(unsigned long word)
@@ -46,13 +46,14 @@ unsigned long nvgpu_posix_fls(unsigned long word)
*/ */
ret = 0UL; ret = 0UL;
} else { } else {
ret = (sizeof(unsigned long) * 8UL) - __builtin_clzl(word); ret = (sizeof(unsigned long) * 8UL) -
(unsigned long)__builtin_clzl(word);
} }
return ret; return ret;
} }
static unsigned long __find_next_bit(const unsigned long *addr, static unsigned long nvgpu_posix_find_next_bit(const unsigned long *addr,
unsigned long n, unsigned long n,
unsigned long start, unsigned long start,
bool invert) bool invert)
@@ -80,20 +81,20 @@ static unsigned long __find_next_bit(const unsigned long *addr,
return n; return n;
} }
start_mask = ~0UL << (start & (BITS_PER_LONG - 1)); start_mask = ~0UL << (start & (BITS_PER_LONG - 1UL));
idx = start / BITS_PER_LONG; idx = start / BITS_PER_LONG;
w = (addr[idx] ^ invert_mask) & start_mask; w = (addr[idx] ^ invert_mask) & start_mask;
start = round_up(start, BITS_PER_LONG); start = round_up(start, BITS_PER_LONG);
idx_max = (n - 1) / BITS_PER_LONG; idx_max = (n - 1UL) / BITS_PER_LONG;
/* /*
* Find the first non-zero word taking into account start and * Find the first non-zero word taking into account start and
* invert. * invert.
*/ */
while (!w) { while (w == 0UL) {
idx++; idx++;
if (idx > idx_max) { if (idx > idx_max) {
return n; return n;
@@ -109,28 +110,28 @@ static unsigned long __find_next_bit(const unsigned long *addr,
unsigned long find_first_bit(const unsigned long *addr, unsigned long size) unsigned long find_first_bit(const unsigned long *addr, unsigned long size)
{ {
return __find_next_bit(addr, size, 0, false); return nvgpu_posix_find_next_bit(addr, size, 0, false);
} }
unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size) unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size)
{ {
return __find_next_bit(addr, size, 0, true); return nvgpu_posix_find_next_bit(addr, size, 0, true);
} }
unsigned long find_next_bit(const unsigned long *addr, unsigned long size, unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
unsigned long offset) unsigned long offset)
{ {
return __find_next_bit(addr, size, offset, false); return nvgpu_posix_find_next_bit(addr, size, offset, false);
} }
static unsigned long find_next_zero_bit(const unsigned long *addr, static unsigned long find_next_zero_bit(const unsigned long *addr,
unsigned long size, unsigned long size,
unsigned long offset) unsigned long offset)
{ {
return __find_next_bit(addr, size, offset, true); return nvgpu_posix_find_next_bit(addr, size, offset, true);
} }
void bitmap_set(unsigned long *map, unsigned int start, int len) void nvgpu_bitmap_set(unsigned long *map, unsigned int start, unsigned int len)
{ {
unsigned int end = start + len; unsigned int end = start + len;
@@ -138,16 +139,16 @@ void bitmap_set(unsigned long *map, unsigned int start, int len)
* Super slow naive implementation. But speed isn't what matters here. * Super slow naive implementation. But speed isn't what matters here.
*/ */
while (start < end) { while (start < end) {
set_bit(start++, map); nvgpu_set_bit(start++, map);
} }
} }
void bitmap_clear(unsigned long *map, unsigned int start, int len) void nvgpu_bitmap_clear(unsigned long *map, unsigned int start, unsigned int len)
{ {
unsigned int end = start + len; unsigned int end = start + len;
while (start < end) { while (start < end) {
clear_bit(start++, map); nvgpu_clear_bit(start++, map);
} }
} }
@@ -185,7 +186,7 @@ unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
return start; return start;
} }
start = offs + 1; start = offs + 1UL;
} }
return size; return size;
@@ -201,12 +202,13 @@ unsigned long bitmap_find_next_zero_area(unsigned long *map,
align_mask, 0); align_mask, 0);
} }
bool test_bit(int nr, const volatile unsigned long *addr) bool nvgpu_test_bit(unsigned int nr, const volatile unsigned long *addr)
{ {
return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); return (1UL & (addr[BIT_WORD(nr)] >>
(nr & (BITS_PER_LONG-1UL)))) != 0UL;
} }
bool test_and_set_bit(int nr, volatile unsigned long *addr) bool nvgpu_test_and_set_bit(unsigned int nr, volatile unsigned long *addr)
{ {
unsigned long mask = BIT_MASK(nr); unsigned long mask = BIT_MASK(nr);
volatile unsigned long *p = addr + BIT_WORD(nr); volatile unsigned long *p = addr + BIT_WORD(nr);
@@ -214,27 +216,26 @@ bool test_and_set_bit(int nr, volatile unsigned long *addr)
return (atomic_fetch_or(p, mask) & mask) != 0ULL; return (atomic_fetch_or(p, mask) & mask) != 0ULL;
} }
bool test_and_clear_bit(int nr, volatile unsigned long *addr) bool nvgpu_test_and_clear_bit(unsigned int nr, volatile unsigned long *addr)
{ {
unsigned long mask = BIT_MASK(nr); unsigned long mask = BIT_MASK(nr);
volatile unsigned long *p = volatile unsigned long *p = addr + BIT_WORD(nr);
((volatile unsigned long *)addr) + BIT_WORD(nr);
return (atomic_fetch_and(p, ~mask) & mask) != 0ULL; return (atomic_fetch_and(p, ~mask) & mask) != 0ULL;
} }
void set_bit(int nr, volatile unsigned long *addr) void nvgpu_set_bit(unsigned int nr, volatile unsigned long *addr)
{ {
unsigned long mask = BIT_MASK(nr); unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); volatile unsigned long *p = addr + BIT_WORD(nr);
(void)atomic_fetch_or(p, mask); (void)atomic_fetch_or(p, mask);
} }
void clear_bit(int nr, volatile unsigned long *addr) void nvgpu_clear_bit(unsigned int nr, volatile unsigned long *addr)
{ {
unsigned long mask = BIT_MASK(nr); unsigned long mask = BIT_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); volatile unsigned long *p = addr + BIT_WORD(nr);
(void)atomic_fetch_and(p, ~mask); (void)atomic_fetch_and(p, ~mask);
} }

4
userspace/units/fifo/tsg/nvgpu-tsg.c
View File

@@ -327,9 +327,9 @@ static int test_tsg_bind_channel(struct unit_module *m,
/* ch already already active */ /* ch already already active */
runlist = &f->active_runlist_info[tsg->runlist_id]; runlist = &f->active_runlist_info[tsg->runlist_id];
if (branches & F_TSG_BIND_CHANNEL_ACTIVE) { if (branches & F_TSG_BIND_CHANNEL_ACTIVE) {
set_bit((int)ch->chid, runlist->active_channels); nvgpu_set_bit(ch->chid, runlist->active_channels);
} else { } else {
clear_bit((int)ch->chid, runlist->active_channels); nvgpu_clear_bit(ch->chid, runlist->active_channels);
} }
g->ops.tsg.bind_channel = g->ops.tsg.bind_channel =

24
userspace/units/posix/bitops/posix-bitops.c
View File

@@ -509,7 +509,7 @@ static int test_single_bitops(struct unit_module *m,
* First set all the bits and make sure the words are set. * First set all the bits and make sure the words are set.
*/ */
for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++) for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++)
set_bit(i, words); nvgpu_set_bit(i, words);
if (!verify_set_buf(words, NUM_WORDS * BITS_PER_LONG, if (!verify_set_buf(words, NUM_WORDS * BITS_PER_LONG,
0, NUM_WORDS * BITS_PER_LONG, false)) { 0, NUM_WORDS * BITS_PER_LONG, false)) {
@@ -521,11 +521,11 @@ static int test_single_bitops(struct unit_module *m,
* Now make sure the test_bit works for set bits. * Now make sure the test_bit works for set bits.
*/ */
for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++) for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++)
if (!test_bit(i, words)) if (!nvgpu_test_bit(i, words))
unit_return_fail(m, "test_bit: bit %d failed!\n", i); unit_return_fail(m, "test_bit: bit %d failed!\n", i);
for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++) for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++)
clear_bit(i, words); nvgpu_clear_bit(i, words);
if (!verify_set_buf(words, NUM_WORDS * BITS_PER_LONG, if (!verify_set_buf(words, NUM_WORDS * BITS_PER_LONG,
0, NUM_WORDS * BITS_PER_LONG, true)) { 0, NUM_WORDS * BITS_PER_LONG, true)) {
@@ -534,7 +534,7 @@ static int test_single_bitops(struct unit_module *m,
} }
for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++) for (i = 0; i < NUM_WORDS * BITS_PER_LONG; i++)
if (test_bit(i, words)) if (nvgpu_test_bit(i, words))
unit_return_fail(m, "test_bit: bit %d failed!\n", i); unit_return_fail(m, "test_bit: bit %d failed!\n", i);
return UNIT_SUCCESS; return UNIT_SUCCESS;
@@ -544,8 +544,8 @@ static int test_bit_setclear(struct unit_module *m,
struct gk20a *g, void *__args) struct gk20a *g, void *__args)
{ {
struct test_setclear_args *args = __args; struct test_setclear_args *args = __args;
void (*testfn)(int, volatile unsigned long *) = void (*testfn)(unsigned int, volatile unsigned long *) =
args->clear ? clear_bit : set_bit; args->clear ? nvgpu_clear_bit : nvgpu_set_bit;
unsigned long words[NUM_WORDS]; unsigned long words[NUM_WORDS];
unsigned int i; unsigned int i;
@@ -569,10 +569,10 @@ static int test_test_and_setclear_bit(struct unit_module *m,
struct gk20a *g, void *__args) struct gk20a *g, void *__args)
{ {
struct test_setclear_args *args = __args; struct test_setclear_args *args = __args;
bool (*testfn)(int, volatile unsigned long *) = bool (*testfn)(unsigned int, volatile unsigned long *) =
args->clear ? test_and_clear_bit : test_and_set_bit; args->clear ? nvgpu_test_and_clear_bit : nvgpu_test_and_set_bit;
bool (*testfn_reset)(int, volatile unsigned long *) = bool (*testfn_reset)(unsigned int, volatile unsigned long *) =
args->clear ? test_and_set_bit : test_and_clear_bit; args->clear ? nvgpu_test_and_set_bit : nvgpu_test_and_clear_bit;
unsigned long words[NUM_WORDS]; unsigned long words[NUM_WORDS];
unsigned int i; unsigned int i;
@@ -618,8 +618,8 @@ static int test_bitmap_setclear(struct unit_module *m,
struct gk20a *g, void *__args) struct gk20a *g, void *__args)
{ {
struct test_setclear_args *args = __args; struct test_setclear_args *args = __args;
void (*testfn)(unsigned long *, unsigned int, int) = void (*testfn)(unsigned long *, unsigned int, unsigned int) =
args->clear ? bitmap_clear : bitmap_set; args->clear ? nvgpu_bitmap_clear : nvgpu_bitmap_set;
unsigned long words[NUM_WORDS]; unsigned long words[NUM_WORDS];
unsigned long i, j; unsigned long i, j;
int set_char = args->clear ? 0xff : 0x0; int set_char = args->clear ? 0xff : 0x0;