nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: hal correction for class error handling

Browse Source 
Add new hal function
gp10b_gr_intr_handle_class_error.

Update handle_class_error hal function for
gp10b, gv11b and tu104 to
gp10b_gr_intr_handle_class_error from
gm20b_gr_intr_handle_class_error.
gr_trapped_data_mme_pc uses 12 bits from gp10b.

Move gm20b_gr_intr_handle_class_error hal function
to non-fusa section.

Jira NVGPU-4913

Signed-off-by: vinodg <vinodg@nvidia.com>
Change-Id: Ic93013ba43d4bf409527109f2f2d43db11c4238e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2314249
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vinodg
2020-03-17 11:13:07 -07:00
committed by Alex Waterman
parent ebb91f0b4d
commit a9d8fc96a7
8 changed files with 74 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
View File

@@ -39,6 +39,35 @@
#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE U32(0)
void gm20b_gr_intr_handle_class_error(struct gk20a *g, u32 chid,
struct nvgpu_gr_isr_data *isr_data)
{
u32 gr_class_error;
gr_class_error =
gr_class_error_code_v(nvgpu_readl(g, gr_class_error_r()));
nvgpu_err(g, "class error 0x%08x, offset 0x%08x,"
"sub channel 0x%08x mme generated %d,"
" mme pc 0x%08xdata high %d priv status %d"
" unhandled intr 0x%08x for channel %u",
isr_data->class_num, (isr_data->offset << 2),
gr_trapped_addr_subch_v(isr_data->addr),
gr_trapped_addr_mme_generated_v(isr_data->addr),
gr_trapped_data_mme_pc_v(
nvgpu_readl(g, gr_trapped_data_mme_r())),
gr_trapped_addr_datahigh_v(isr_data->addr),
gr_trapped_addr_priv_v(isr_data->addr),
gr_class_error, chid);
nvgpu_err(g, "trapped data low 0x%08x",
nvgpu_readl(g, gr_trapped_data_lo_r()));
if (gr_trapped_addr_datahigh_v(isr_data->addr) != 0U) {
nvgpu_err(g, "trapped data high 0x%08x",
nvgpu_readl(g, gr_trapped_data_hi_r()));
}
}
int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data)
{

4
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.h
View File

@@ -40,8 +40,6 @@ struct nvgpu_gr_intr_info;
#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE U32(0)
void gm20b_gr_intr_handle_class_error(struct gk20a *g, u32 chid,
struct nvgpu_gr_isr_data *isr_data);
void gm20b_gr_intr_clear_pending_interrupts(struct gk20a *g, u32 gr_intr);
u32 gm20b_gr_intr_read_pending_interrupts(struct gk20a *g,
struct nvgpu_gr_intr_info *intr_info);
@@ -56,6 +54,8 @@ u32 gm20b_gr_intr_get_tpc_exception(struct gk20a *g, u32 offset,
void gm20b_gr_intr_enable_interrupts(struct gk20a *g, bool enable);
u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gm20b_gr_intr_handle_class_error(struct gk20a *g, u32 chid,
struct nvgpu_gr_isr_data *isr_data);
void gm20b_gr_intr_tpc_exception_sm_enable(struct gk20a *g);
int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data);

29
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c
View File

@@ -40,35 +40,6 @@
#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE U32(0)
void gm20b_gr_intr_handle_class_error(struct gk20a *g, u32 chid,
struct nvgpu_gr_isr_data *isr_data)
{
u32 gr_class_error;
gr_class_error =
gr_class_error_code_v(nvgpu_readl(g, gr_class_error_r()));
nvgpu_err(g, "class error 0x%08x, offset 0x%08x,"
"sub channel 0x%08x mme generated %d,"
" mme pc 0x%08xdata high %d priv status %d"
" unhandled intr 0x%08x for channel %u",
isr_data->class_num, (isr_data->offset << 2),
gr_trapped_addr_subch_v(isr_data->addr),
gr_trapped_addr_mme_generated_v(isr_data->addr),
gr_trapped_data_mme_pc_v(
nvgpu_readl(g, gr_trapped_data_mme_r())),
gr_trapped_addr_datahigh_v(isr_data->addr),
gr_trapped_addr_priv_v(isr_data->addr),
gr_class_error, chid);
nvgpu_err(g, "trapped data low 0x%08x",
nvgpu_readl(g, gr_trapped_data_lo_r()));
if (gr_trapped_addr_datahigh_v(isr_data->addr) != 0U) {
nvgpu_err(g, "trapped data high 0x%08x",
nvgpu_readl(g, gr_trapped_data_hi_r()));
}
}
void gm20b_gr_intr_clear_pending_interrupts(struct gk20a *g, u32 gr_intr)
{
nvgpu_writel(g, gr_intr_r(), gr_intr);

4
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -43,6 +43,8 @@ struct nvgpu_gr_isr_data;
int gp10b_gr_intr_handle_fecs_error(struct gk20a *g,
struct nvgpu_channel *ch_ptr,
struct nvgpu_gr_isr_data *isr_data);
void gp10b_gr_intr_handle_class_error(struct gk20a *g, u32 chid,
struct nvgpu_gr_isr_data *isr_data);
#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)
void gp10b_gr_intr_set_coalesce_buffer_size(struct gk20a *g, u32 data);
void gp10b_gr_intr_set_go_idle_timeout(struct gk20a *g, u32 data);

36
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b_fusa.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -33,10 +33,44 @@
#include <nvgpu/gr/gr_intr.h>
#include <nvgpu/gr/gr_utils.h>
#include "common/gr/gr_intr_priv.h"
#include "gr_intr_gp10b.h"
#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
void gp10b_gr_intr_handle_class_error(struct gk20a *g, u32 chid,
struct nvgpu_gr_isr_data *isr_data)
{
u32 gr_class_error;
u32 offset_bit_shift = 2U;
u32 data_hi_set = 0U;
gr_class_error =
gr_class_error_code_v(nvgpu_readl(g, gr_class_error_r()));
nvgpu_err(g, "class error 0x%08x, offset 0x%08x,"
"sub channel 0x%08x mme generated %d,"
" mme pc 0x%08xdata high %d priv status %d"
" unhandled intr 0x%08x for channel %u",
isr_data->class_num, (isr_data->offset << offset_bit_shift),
gr_trapped_addr_subch_v(isr_data->addr),
gr_trapped_addr_mme_generated_v(isr_data->addr),
gr_trapped_data_mme_pc_v(
nvgpu_readl(g, gr_trapped_data_mme_r())),
gr_trapped_addr_datahigh_v(isr_data->addr),
gr_trapped_addr_priv_v(isr_data->addr),
gr_class_error, chid);
nvgpu_err(g, "trapped data low 0x%08x",
nvgpu_readl(g, gr_trapped_data_lo_r()));
data_hi_set = gr_trapped_addr_datahigh_v(isr_data->addr);
if (data_hi_set != 0U) {
nvgpu_err(g, "trapped data high 0x%08x",
nvgpu_readl(g, gr_trapped_data_hi_r()));
}
}
#ifdef CONFIG_NVGPU_CILP
static int gp10b_gr_intr_clear_cilp_preempt_pending(struct gk20a *g,
struct nvgpu_channel *fault_ch)

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -538,7 +538,7 @@ static const struct gpu_ops gp10b_ops = {
.set_shader_exceptions =
gm20b_gr_intr_set_shader_exceptions,
.handle_class_error =
gm20b_gr_intr_handle_class_error,
gp10b_gr_intr_handle_class_error,
.clear_pending_interrupts =
gm20b_gr_intr_clear_pending_interrupts,
.read_pending_interrupts =

3
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -137,6 +137,7 @@
#include "hal/gr/init/gr_init_gp10b.h"
#include "hal/gr/init/gr_init_gv11b.h"
#include "hal/gr/intr/gr_intr_gm20b.h"
#include "hal/gr/intr/gr_intr_gp10b.h"
#include "hal/gr/intr/gr_intr_gv11b.h"
#ifdef CONFIG_NVGPU_DEBUGGER
#include "hal/gr/hwpm_map/hwpm_map_gv100.h"
@@ -663,7 +664,7 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
.handle_fecs_error = gv11b_gr_intr_handle_fecs_error,
.handle_sw_method = gv11b_gr_intr_handle_sw_method,
.handle_class_error =
gm20b_gr_intr_handle_class_error,
gp10b_gr_intr_handle_class_error,
.clear_pending_interrupts =
gm20b_gr_intr_clear_pending_interrupts,
.read_pending_interrupts =

3
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -131,6 +131,7 @@
#include "hal/gr/init/gr_init_gv11b.h"
#include "hal/gr/init/gr_init_tu104.h"
#include "hal/gr/intr/gr_intr_gm20b.h"
#include "hal/gr/intr/gr_intr_gp10b.h"
#include "hal/gr/intr/gr_intr_gv11b.h"
#include "hal/gr/intr/gr_intr_tu104.h"
#include "hal/gr/hwpm_map/hwpm_map_gv100.h"
@@ -682,7 +683,7 @@ static const struct gpu_ops tu104_ops = {
.handle_fecs_error = gv11b_gr_intr_handle_fecs_error,
.handle_sw_method = tu104_gr_intr_handle_sw_method,
.handle_class_error =
gm20b_gr_intr_handle_class_error,
gp10b_gr_intr_handle_class_error,
.clear_pending_interrupts =
gm20b_gr_intr_clear_pending_interrupts,
.read_pending_interrupts =