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mc remove non-fusa HAL used only by PMU

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Compile out the MC HAL is_enabled() with the macro CONFIG_NVGPU_LS_PMU
since it is only used by the PMU unit.

JIRA NVGPU-2224

Change-Id: I242ba923bfce62674107089157a6103aee6a2f93
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258703
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-12-09 08:54:21 -05:00
committed by Alex Waterman
parent e515ba7098
commit ae4f219c65
7 changed files with 19 additions and 7 deletions
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2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
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@@ -979,7 +979,9 @@ static const struct gpu_ops gm20b_ops = {
.is_intr1_pending = gm20b_mc_is_intr1_pending,
.log_pending_intrs = gm20b_mc_log_pending_intrs,
.reset_mask = gm20b_mc_reset_mask,
#ifdef CONFIG_NVGPU_LS_PMU
.is_enabled = gm20b_mc_is_enabled,
#endif
.fb_reset = gm20b_mc_fb_reset,
.ltc_isr = gm20b_mc_ltc_isr,
.is_mmu_fault_pending = gm20b_mc_is_mmu_fault_pending,

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
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@@ -1077,7 +1077,9 @@ static const struct gpu_ops gp10b_ops = {
.is_intr1_pending = mc_gp10b_is_intr1_pending,
.log_pending_intrs = mc_gp10b_log_pending_intrs,
.reset_mask = gm20b_mc_reset_mask,
#ifdef CONFIG_NVGPU_LS_PMU
.is_enabled = gm20b_mc_is_enabled,
#endif
.fb_reset = gm20b_mc_fb_reset,
.ltc_isr = mc_gp10b_ltc_isr,
.is_mmu_fault_pending = gm20b_mc_is_mmu_fault_pending,

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
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@@ -1292,7 +1292,9 @@ static const struct gpu_ops gv11b_ops = {
.is_stall_and_eng_intr_pending =
gv11b_mc_is_stall_and_eng_intr_pending,
.reset_mask = gm20b_mc_reset_mask,
#ifdef CONFIG_NVGPU_LS_PMU
.is_enabled = gm20b_mc_is_enabled,
#endif
.fb_reset = NULL,
.ltc_isr = mc_gp10b_ltc_isr,
.is_mmu_fault_pending = gv11b_mc_is_mmu_fault_pending,

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
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@@ -1317,7 +1317,9 @@ static const struct gpu_ops tu104_ops = {
gv100_mc_is_stall_and_eng_intr_pending,
.fbpa_isr = mc_tu104_fbpa_isr,
.reset_mask = gv100_mc_reset_mask,
#ifdef CONFIG_NVGPU_LS_PMU
.is_enabled = gm20b_mc_is_enabled,
#endif
.fb_reset = NULL,
.ltc_isr = mc_tu104_ltc_isr,
.is_mmu_fault_pending = gv11b_mc_is_mmu_fault_pending,

9
drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
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@@ -299,3 +299,12 @@ bool gm20b_mc_is_mmu_fault_pending(struct gk20a *g)
{
return g->ops.fifo.is_mmu_fault_pending(g);
}
#ifdef CONFIG_NVGPU_LS_PMU
bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
{
u32 mask = g->ops.mc.reset_mask(g, unit);
return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
}
#endif

7
drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
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@@ -170,10 +170,3 @@ u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
return mask;
}
bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
{
u32 mask = g->ops.mc.reset_mask(g, unit);
return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
}

2
drivers/gpu/nvgpu/include/nvgpu/gops_mc.h
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@@ -284,7 +284,9 @@ struct gops_mc {
void (*disable)(struct gk20a *g, u32 units);
#ifdef CONFIG_NVGPU_LS_PMU
bool (*is_enabled)(struct gk20a *g, enum nvgpu_unit unit);
#endif
bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit,
u32 mc_intr_1);