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gpu: nvgpu: fix sim readl output configuration

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In nvgpu_sim_esc_readl() we prepare a message, issue RPC and then copy back
the response from offset "data_offset + 0xc"

But while configuring the message we incorrectly set the response offset as
just "data_offset"

Fix this by correctly configuring the response offset as "data_offset + 0xc"

Jira NVGPUT-41

Change-Id: I855e140b97e7128367446d0962eec283b069f514
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756844
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-06-21 03:18:05 -07:00
committed by mobile promotions
parent 790ba09554
commit af652f0bb7
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/nvgpu/common/sim_pci.c
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@@ -196,7 +196,7 @@ static void nvgpu_sim_esc_readl(struct gk20a *g,
*sim_msg_param(g, 0) = index;
*sim_msg_param(g, 4) = sizeof(u32);
data_offset = roundup(pathlen + 1, sizeof(u32));
*sim_msg_param(g, 8) = data_offset;
*sim_msg_param(g, 8) = data_offset + 0xc;
strcpy((char *)sim_msg_param(g, 0xc), path);
err = issue_rpc_and_wait(g);