nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 02:52:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Refactor Volt unit

Browse Source 
Current volt unit has multiple header files under pmuif folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within volt unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_volt_inf.h from pmuif which only
volt can access.
All public items are moved into include/volt.h which other units can
access
This will help in documentation of items for public items.

NVGPU-4492

Change-Id: Id40bf4922408a55f1e67d071be726839ac57718f
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289114
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2020-02-03 20:31:04 +05:30
committed by Alex Waterman
parent 7852d452ee
commit b21f300db7
21 changed files with 117 additions and 168 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/nvgpu-common.yaml
View File

@@ -646,7 +646,6 @@ pmu:
include/nvgpu/pmu/pmuif/ctrlclk.h,
include/nvgpu/pmu/pmuif/ctrlclkavfs.h,
include/nvgpu/pmu/pmuif/ctrlpmgr.h,
include/nvgpu/pmu/pmuif/ctrlvolt.h,
include/nvgpu/pmu/pmuif/acr.h,
include/nvgpu/pmu/pmuif/ap.h,
include/nvgpu/pmu/pmuif/cmn.h,
@@ -659,7 +658,6 @@ pmu:
include/nvgpu/pmu/pmuif/clk.h,
include/nvgpu/pmu/pmuif/pmgr.h,
include/nvgpu/pmu/pmuif/seq.h,
include/nvgpu/pmu/pmuif/volt.h,
include/nvgpu/pmu/pmuif/rpc.h,
include/nvgpu/pmu/pmuif/nvgpu_cmdif.h ]
boardobj:
@@ -914,6 +912,7 @@ pmu:
common/pmu/volt/volt_dev.h,
common/pmu/volt/volt_policy.h,
common/pmu/volt/volt_rail.h,
common/pmu/volt/ucode_volt_inf.h,
include/nvgpu/pmu/volt.h ]
sec2:

1
drivers/gpu/nvgpu/common/pmu/clk/clk.c
View File

@@ -24,7 +24,6 @@
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/pmu/pmuif/ctrlclk.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/bug.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/perf.h>

1
drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
View File

@@ -32,7 +32,6 @@
#include <nvgpu/pmu/clk/clk_vf_point.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/cmd.h>

1
drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
View File

@@ -28,7 +28,6 @@
#include <nvgpu/boardobjgrpmask.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlclk.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/clk/clk_fll.h>
#include <nvgpu/pmu/clk/clk_vin.h>

1
drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
View File

@@ -29,7 +29,6 @@
#include <nvgpu/pmu/boardobjgrp_classes.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlclk.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/clk/clk_vf_point.h>

1
drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
View File

@@ -27,7 +27,6 @@
#include <nvgpu/pmu/boardobjgrp_classes.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlclk.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/timers.h>
#include <nvgpu/clk_arb.h>
#include <nvgpu/pmu/volt.h>

1
drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
View File

@@ -29,7 +29,6 @@
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/boardobjgrp_classes.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/cmd.h>
#include <nvgpu/pmu/volt.h>

12
drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h
View File

@@ -25,7 +25,6 @@
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/pmu/pmuif/volt.h>
#include <nvgpu/pmu/pmuif/clk.h>
#include <nvgpu/pmu/pmuif/cmn.h>
#include <nvgpu/flcnif_cmn.h>
@@ -108,17 +107,6 @@ struct nv_pmu_super_surface {
* member present above to know the offset of
* required boardobj from super surface in nvgpu
*/
struct {
struct nv_pmu_volt_volt_device_boardobj_grp_set
volt_device_grp_set;
struct nv_pmu_volt_volt_policy_boardobj_grp_set
volt_policy_grp_set;
struct nv_pmu_volt_volt_rail_boardobj_grp_set
volt_rail_grp_set;
struct nv_pmu_volt_volt_rail_boardobj_grp_get_status
volt_rail_grp_get_status;
} volt;
struct {
struct nv_pmu_clk_clk_vin_device_boardobj_grp_set
clk_vin_device_grp_set;

94
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/volt.h → drivers/gpu/nvgpu/common/pmu/volt/ucode_volt_inf.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -24,10 +24,96 @@
#include <nvgpu/flcnif_cmn.h>
#include "boardobj.h"
#include "ctrlvolt.h"
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
#define NV_PMU_VOLT_VALUE_0V_IN_UV (0U)
#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \
CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES 0x8U
#define CTRL_VOLT_DOMAIN_INVALID 0x00U
#define CLK_PROG_VFE_ENTRY_SRAM 0x01U
#define NV_PMU_VOLT_VALUE_0V_IN_UV 0U
/*
* Macros for Voltage Domain HAL.
*/
#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U
/*!
* Special value corresponding to an invalid Voltage Rail Index.
*/
#define CTRL_VOLT_RAIL_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
/*!
* Special value corresponding to an invalid Voltage Device Index.
*/
#define CTRL_VOLT_DEVICE_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
/*!
* Special value corresponding to an invalid Voltage Policy Index.
*/
#define CTRL_VOLT_POLICY_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
enum nv_pmu_pmgr_pwm_source {
NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
NV_PMU_PMGR_PWM_SOURCE_THERM_IPC_VMIN_VID_PWM_0 = 13U,
};
/*!
* Macros for Voltage Device Types.
*/
#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00U
#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03U
/*
* Macros for Volt Device Operation types.
*/
#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00U
#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01U
#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04U
/*!
* Macros for Voltage Domains.
*/
#define CTRL_VOLT_DOMAIN_INVALID 0x00U
#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
#define CTRL_VOLT_DOMAIN_SRAM 0x02U
/*!
* Macros for Volt Policy types.
*
* Virtual VOLT_POLICY types are indexed starting from 0xFF.
*/
#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00U
#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01U
#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02U
#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03U
#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U
#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFEU
#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFFU
/*!
* Macros for Volt Policy Client types.
*/
#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00U
#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01U
struct ctrl_volt_volt_rail_list_item {
u8 rail_idx;
u32 voltage_uv;
};
struct ctrl_volt_volt_rail_list {
u8 num_rails;
struct ctrl_volt_volt_rail_list_item
rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
};
struct nv_pmu_volt_volt_rail_boardobjgrp_set_header {
struct nv_pmu_boardobjgrp_e32 super;

2
drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c
View File

@@ -29,10 +29,10 @@
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/boardobjgrp_classes.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/volt.h>
#include "ucode_volt_inf.h"
#include "volt_dev.h"
#include "volt_rail.h"

3
drivers/gpu/nvgpu/common/pmu/volt/volt_dev.h
View File

@@ -25,7 +25,8 @@
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include "ucode_volt_inf.h"
#define VOLTAGE_TABLE_MAX_ENTRIES_ONE 1U
#define VOLTAGE_TABLE_MAX_ENTRIES 256U

2
drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c
View File

@@ -26,9 +26,9 @@
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/boardobjgrp_classes.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/perf.h>
#include "ucode_volt_inf.h"
#include "volt_policy.h"
static int volt_policy_pmu_data_init_super(struct gk20a *g,

2
drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c
View File

@@ -26,10 +26,10 @@
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/boardobjgrp_classes.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/volt.h>
#include "ucode_volt_inf.h"
#include "volt_rail.h"
#define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16U

1
drivers/gpu/nvgpu/hal/clk/clk_tu104.c
View File

@@ -38,6 +38,7 @@
#include <nvgpu/clk_arb.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/clk/clk_domain.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/hw/tu104/hw_trim_tu104.h>
#include "clk_tu104.h"

1
drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h
View File

@@ -27,7 +27,6 @@
#include <nvgpu/pmu/pmuif/pg.h>
#include <nvgpu/pmu/pmuif/acr.h>
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/pmu/pmuif/volt.h>
#include <nvgpu/pmu/pmuif/clk.h>
#include <nvgpu/pmu/pmuif/pmgr.h>
#include <nvgpu/pmu/pmuif/rpc.h>

1
drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h
View File

@@ -31,7 +31,6 @@
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/pmu/pmuif/clk.h>
#include <nvgpu/pmu/pmuif/pmgr.h>
#include <nvgpu/pmu/pmuif/volt.h>
/* GPU ID */
#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2U

5
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -24,12 +24,11 @@
#define NVGPU_PMUIF_CLK_H
#include <nvgpu/flcnif_cmn.h>
#include <nvgpu/pmu/volt.h>
#include "ctrlboardobj.h"
#include "ctrlvolt.h"
#include "ctrlclk.h"
#include "boardobj.h"
#include "volt.h"
/*
* Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal

3
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlclk.h
View File

@@ -1,7 +1,7 @@
/*
* general p state infrastructure
*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -26,7 +26,6 @@
#include "ctrlboardobj.h"
#include "ctrlclkavfs.h"
#include "ctrlvolt.h"
#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4U

132
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlvolt.h
View File

@@ -1,132 +0,0 @@
/*
* general p state infrastructure
*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_PMUIF_CTRLVOLT_H
#define NVGPU_PMUIF_CTRLVOLT_H
#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \
CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
#include "ctrlboardobj.h"
#define CTRL_VOLT_VOLT_RAIL_CLIENT_MAX_RAILS 0x04U
#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8U)
#define CTRL_VOLT_DOMAIN_INVALID 0x00U
#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
#define CLK_PROG_VFE_ENTRY_LOGIC 0x00U
#define CLK_PROG_VFE_ENTRY_SRAM 0x01U
/*
* Macros for Voltage Domain HAL.
*/
#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U
/*!
* Special value corresponding to an invalid Voltage Rail Index.
*/
#define CTRL_VOLT_RAIL_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
/*!
* Special value corresponding to an invalid Voltage Device Index.
*/
#define CTRL_VOLT_DEVICE_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
/*!
* Special value corresponding to an invalid Voltage Policy Index.
*/
#define CTRL_VOLT_POLICY_INDEX_INVALID \
CTRL_BOARDOBJ_IDX_INVALID
enum nv_pmu_pmgr_pwm_source {
NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
NV_PMU_PMGR_PWM_SOURCE_THERM_IPC_VMIN_VID_PWM_0 = 13U,
};
/*!
* Macros for Voltage Device Types.
*/
#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00U
#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03U
/*
* Macros for Volt Device Operation types.
*/
#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00U
#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01U
#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04U
/*!
* Macros for Voltage Domains.
*/
#define CTRL_VOLT_DOMAIN_INVALID 0x00U
#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
#define CTRL_VOLT_DOMAIN_SRAM 0x02U
/*!
* Macros for Volt Policy types.
*
* Virtual VOLT_POLICY types are indexed starting from 0xFF.
*/
#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00U
#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01U
#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02U
#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03U
#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U
#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFEU
#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFFU
/*!
* Macros for Volt Policy Client types.
*/
#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00U
#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01U
struct ctrl_volt_volt_rail_list_item {
u8 rail_idx;
u32 voltage_uv;
};
struct ctrl_volt_volt_rail_list {
u8 num_rails;
struct ctrl_volt_volt_rail_list_item
rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
};
struct ctrl_volt_volt_rail_list_item_v1 {
u8 rail_idx;
u32 voltage_uv;
u32 voltage_min_noise_unaware_uv;
u32 voltage_offset_uV[2];
};
struct ctrl_volt_volt_rail_list_v1 {
u8 num_rails;
struct ctrl_volt_volt_rail_list_item_v1
rails[CTRL_VOLT_VOLT_RAIL_CLIENT_MAX_RAILS];
};
#endif /* NVGPU_PMUIF_CTRLVOLT_H */

15
drivers/gpu/nvgpu/include/nvgpu/pmu/volt.h
View File

@@ -28,6 +28,9 @@
struct gk20a;
#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
#define CLK_PROG_VFE_ENTRY_LOGIC 0x00U
#define CTRL_VOLT_VOLT_RAIL_CLIENT_MAX_RAILS 0x04U
#define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \
((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
@@ -66,6 +69,18 @@ struct nvgpu_pmu_volt {
struct voltage_device_metadata volt_dev_metadata;
struct voltage_policy_metadata volt_policy_metadata;
};
struct ctrl_volt_volt_rail_list_item_v1 {
u8 rail_idx;
u32 voltage_uv;
u32 voltage_min_noise_unaware_uv;
u32 voltage_offset_uV[2];
};
struct ctrl_volt_volt_rail_list_v1 {
u8 num_rails;
struct ctrl_volt_volt_rail_list_item_v1
rails[CTRL_VOLT_VOLT_RAIL_CLIENT_MAX_RAILS];
};
u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv);

3
drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2018-2020, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -26,6 +26,7 @@
#include <nvgpu/pmu/clk/clk_vf_point.h>
#include <nvgpu/pmu/clk/clk_fll.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/volt.h>
#include "hal/clk/clk_tu104.h"