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gpu: nvgpu: fixing unit tests for ga10b

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- Add support for unit tests to run on orin platform.

JIRA NVGPU-9909 

Change-Id: If4ca69b77d0d8483c0e9f6a6a5a64c3c3e050d65
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2737876
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
srajum
2022-06-30 19:23:04 +05:30
committed by mobile promotions
parent 63057907ee
commit b2345cd01a
9 changed files with 94 additions and 27 deletions
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4
drivers/gpu/nvgpu/include/nvgpu/posix/probe.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -26,6 +26,8 @@
/* /*
* In the unit test FW the POSIX code is expecting a gv11b at the moment. * In the unit test FW the POSIX code is expecting a gv11b at the moment.
*/ */
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 (0x00000017 << \
NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \ #define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \
NVGPU_GPU_ARCHITECTURE_SHIFT) NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB #define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB

22
drivers/gpu/nvgpu/os/posix/firmware.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -32,9 +32,11 @@
#define FW_MAX_PATH_SIZE 2048U #define FW_MAX_PATH_SIZE 2048U
#if defined(__QNX__) #if defined(__QNX__)
#define NVGPU_UNITTEST_UCODE_PATH "/gv11b/" #define NVGPU_UNITTEST_UCODE_PATH_GV11B "/gv11b/"
#define NVGPU_UNITTEST_UCODE_PATH_GA10B "/ga10b/"
#else #else
#define NVGPU_UNITTEST_UCODE_PATH "/firmware/gv11b/" #define NVGPU_UNITTEST_UCODE_PATH_GV11B "/firmware/gv11b/"
#define NVGPU_UNITTEST_UCODE_PATH_GA10B "/firmware/ga10b/"
#endif #endif
static int nvgpu_ucode_load(struct gk20a *g, const char *path, static int nvgpu_ucode_load(struct gk20a *g, const char *path,
@@ -130,14 +132,24 @@ struct nvgpu_firmware *nvgpu_request_firmware(struct gk20a *g,
full_path_len = strlen(full_path); full_path_len = strlen(full_path);
full_path_len += strlen(fw_name); full_path_len += strlen(fw_name);
full_path_len += strlen(NVGPU_UNITTEST_UCODE_PATH);
if (strcmp(g->name, "ga10b") == 0) {
full_path_len += strlen(NVGPU_UNITTEST_UCODE_PATH_GA10B);
} else {
full_path_len += strlen(NVGPU_UNITTEST_UCODE_PATH_GV11B);
}
if (full_path_len >= FW_MAX_PATH_SIZE) { if (full_path_len >= FW_MAX_PATH_SIZE) {
nvgpu_err(g, "Invalid MAX_PATH_SIZE %lu %u", full_path_len, nvgpu_err(g, "Invalid MAX_PATH_SIZE %lu %u", full_path_len,
FW_MAX_PATH_SIZE); FW_MAX_PATH_SIZE);
goto err; goto err;
} }
strcat(full_path, NVGPU_UNITTEST_UCODE_PATH); if (strcmp(g->name, "ga10b") == 0) {
strcat(full_path, NVGPU_UNITTEST_UCODE_PATH_GA10B);
} else {
strcat(full_path, NVGPU_UNITTEST_UCODE_PATH_GV11B);
}
strcat(full_path, fw_name); strcat(full_path, fw_name);
fw = nvgpu_kzalloc(g, sizeof(*fw)); fw = nvgpu_kzalloc(g, sizeof(*fw));

29
userspace/units/acr/nvgpu-acr.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -205,9 +205,14 @@ static int init_acr_falcon_test_env(struct unit_module *m, struct gk20a *g)
} }
/* /*
* HAL init parameters for gv11b * HAL init parameters for gv11b and ga10b
*/ */
if (strcmp(g->name, "ga10b") == 0) {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
} else {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
}
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
/* /*
@@ -653,7 +658,11 @@ int test_acr_construct_execute(struct unit_module *m,
* *
* HAL init parameters for gv11b: Correct chip id * HAL init parameters for gv11b: Correct chip id
*/ */
if (strcmp(g->name, "ga10b") == 0) {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
} else {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
}
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
nvgpu_posix_enable_fault_injection(kmem_fi, true, 0); nvgpu_posix_enable_fault_injection(kmem_fi, true, 0);
@@ -813,7 +822,11 @@ int test_acr_prepare_ucode_blob(struct unit_module *m,
* *
* HAL init parameters for gv11b: Correct chip id * HAL init parameters for gv11b: Correct chip id
*/ */
if (strcmp(g->name, "ga10b") == 0) {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
} else {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
}
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
nvgpu_posix_enable_fault_injection(kmem_fi, true, 0); nvgpu_posix_enable_fault_injection(kmem_fi, true, 0);
@@ -876,7 +889,11 @@ int test_acr_prepare_ucode_blob(struct unit_module *m,
/* /*
* set back the valid GPU version * set back the valid GPU version
*/ */
if (strcmp(g->name, "ga10b") == 0) {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
} else {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
}
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
/* /*
@@ -969,7 +986,11 @@ int test_acr_init(struct unit_module *m,
/* /*
* Case 3: enable debug mode for branch coverage * Case 3: enable debug mode for branch coverage
*/ */
if (strcmp(g->name, "ga10b") == 0) {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
} else {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
}
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
g->acr = NULL; g->acr = NULL;
debug_mode_enable = pwr_pmu_scpctl_stat_debug_mode_m(); debug_mode_enable = pwr_pmu_scpctl_stat_debug_mode_m();
@@ -986,7 +1007,11 @@ int test_acr_init(struct unit_module *m,
/* /*
* HAL init parameters for gv11b * HAL init parameters for gv11b
*/ */
if (strcmp(g->name, "ga10b") == 0) {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
} else {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
}
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
nvgpu_posix_io_writel_reg_space(g, pwr_pmu_scpctl_stat_r(), 0x0); nvgpu_posix_io_writel_reg_space(g, pwr_pmu_scpctl_stat_r(), 0x0);
g->acr = NULL; g->acr = NULL;

10
userspace/units/falcon/falcon_tests/falcon.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -49,6 +49,8 @@ static u32 *rand_test_data;
#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \ #define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \
NVGPU_GPU_ARCHITECTURE_SHIFT) NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 (0x00000017 << \
NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB #define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB
#define MAX_MEM_TYPE (MEM_IMEM + 1) #define MAX_MEM_TYPE (MEM_IMEM + 1)
@@ -149,8 +151,12 @@ static int init_falcon_test_env(struct unit_module *m, struct gk20a *g)
return -ENOMEM; return -ENOMEM;
} }
/* HAL init parameters for gv11b */ /* HAL init parameters for gv11b and ga10b */
if (strcmp(g->name, "ga10b") == 0) {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
} else {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
}
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
/* HAL init required for getting the falcon ops initialized. */ /* HAL init required for getting the falcon ops initialized. */

8
userspace/units/fuse/nvgpu-fuse.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -41,6 +41,8 @@
#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \ #define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \
NVGPU_GPU_ARCHITECTURE_SHIFT) NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 (0x00000017 << \
NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB #define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB
/* /*
@@ -119,7 +121,11 @@ int test_fuse_device_common_init(struct unit_module *m,
g->params.gpu_arch = args->gpu_arch << NVGPU_GPU_ARCHITECTURE_SHIFT; g->params.gpu_arch = args->gpu_arch << NVGPU_GPU_ARCHITECTURE_SHIFT;
g->params.gpu_impl = args->gpu_impl; g->params.gpu_impl = args->gpu_impl;
#else #else
if (strcmp(g->name, "ga10b") == 0) {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
} else {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
}
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
#endif #endif

10
userspace/units/ltc/nvgpu-ltc.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -46,6 +46,8 @@
#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \ #define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \
NVGPU_GPU_ARCHITECTURE_SHIFT) NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 (0x00000017 << \
NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB #define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB
/* /*
@@ -117,9 +119,13 @@ int test_ltc_init_support(struct unit_module *m,
(void)nvgpu_posix_register_io(g, &netlist_test_reg_callbacks); (void)nvgpu_posix_register_io(g, &netlist_test_reg_callbacks);
/* /*
* HAL init parameters for gv11b * HAL init parameters for gv11b and ga10b
*/ */
if (strcmp(g->name, "ga10b") == 0) {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
} else {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
}
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
/* /*

10
userspace/units/netlist/nvgpu-netlist.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -42,6 +42,8 @@
#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \ #define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \
NVGPU_GPU_ARCHITECTURE_SHIFT) NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 (0x00000017 << \
NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB #define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB
/* /*
@@ -100,9 +102,13 @@ int test_netlist_init_support(struct unit_module *m,
(void)nvgpu_posix_register_io(g, &netlist_test_reg_callbacks); (void)nvgpu_posix_register_io(g, &netlist_test_reg_callbacks);
/* /*
* HAL init parameters for gv11b * HAL init parameters for gv11b and ga10b
*/ */
if (strcmp(g->name, "ga10b") == 0) {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GA100;
} else {
g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
}
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
/* /*

4
userspace/units/rc/nvgpu-rc.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -47,6 +47,8 @@
#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \ #define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \
NVGPU_GPU_ARCHITECTURE_SHIFT) NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 (0x00000017 << \
NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB #define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB
#define assert(cond) unit_assert(cond, goto done) #define assert(cond) unit_assert(cond, goto done)

4
userspace/units/sync/nvgpu-sync.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -39,6 +39,8 @@
#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \ #define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \
NVGPU_GPU_ARCHITECTURE_SHIFT) NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 (0x00000017 << \
NVGPU_GPU_ARCHITECTURE_SHIFT)
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB #define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB
#define assert(cond) unit_assert(cond, goto done) #define assert(cond) unit_assert(cond, goto done)