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gpu: nvgpu: fix MISRA 16.x errors in gr falcon

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Fixed issues related to switch case formatting.

JIRA NVGPU-3226

Change-Id: I969ff3f56857ed0a523fb353ff07532ed50a114a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110734
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-05-02 16:26:33 -07:00
committed by mobile promotions
parent 8a57a9d8f1
commit b2c634d1bb
1 changed files with 19 additions and 1 deletions
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20
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c
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@@ -347,7 +347,24 @@ void gm20b_gr_falcon_load_ctxsw_ucode_header(struct gk20a *g,
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
/* fallthrough */
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 4);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
addr_code32);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
code_size);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
addr_data32);
nvgpu_writel(g, reg_offset + gr_fecs_dmemd_r(0),
data_size);
break;
case FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED:
case FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED:
case FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED:
@@ -395,6 +412,7 @@ void gm20b_gr_falcon_load_ctxsw_ucode_header(struct gk20a *g,
" with reg_offset 0x%08x",
boot_signature, reg_offset);
BUG();
break;
}
}