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gpu: nvgpu-next: Update pg pre and post init structs

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SECURITY_HARDENING feature in pmu ucode leads to failure
in pg pre and post init rpcs due to mismatch is interface
struct size. This change will update pg pre and post init
nvgpu-pmu interface structs as per pmu ucode.

NVGPU-6421

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: Ied9179b3a7ee1923dba56e792979115f3a19f7e5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551026
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Ramesh Mylavarapu
2021-02-09 16:41:02 +05:30
committed by mobile promotions
parent 27b3085c09
commit b38b8a794d
1 changed files with 18 additions and 4 deletions
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22
drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h
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@@ -23,6 +23,7 @@
#define NVGPU_PMU_PG_SW_GA10B_H
#include <nvgpu/types.h>
#include <nvgpu/pmu/pmuif/pg.h>
struct gk20a;
@@ -37,6 +38,7 @@ enum
{
NV_PMU_LPWR_GRP_CTRL_ID_GR = 0,
NV_PMU_LPWR_GRP_CTRL_ID_MS,
NV_PMU_LPWR_GRP_CTRL_ID_EI,
NV_PMU_LPWR_GRP_CTRL_ID__COUNT,
};
@@ -76,11 +78,23 @@ struct pmu_rpc_struct_lpwr_loading_pre_init
*/
struct pmu_rpc_struct_lpwr_loading_post_init
{
/* [IN/OUT] Must be first field in RPC structure */
/*
* [IN/OUT] Must be first field in RPC structure
*/
struct nv_pmu_rpc_header hdr;
/* Must be last field in RPC structure.*/
u32 scratch[5];
};
/*
* Voltage rail data in LPWR
*/
struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX];
/*
* [IN] Dummy array to match with pmu struct
*/
bool dummy;
/*
* Must be last field in RPC structure.
*/
u32 scratch[1];
};
struct pmu_rpc_struct_lpwr_loading_pg_ctrl_init
{