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gpu: nvgpu: vgpu: remove unused ivc commands

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TEGRA_VGPU_CMD_GET_ATTRIBUTE
TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX
TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX
TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY
TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE
TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE
TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX

The above commands which are not used by clients anymore are being
removed.

Jira GVSCI-5155

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: If5eef090308e6471a0e7aadf78878f1ad798ee9a
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2367556
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2020-06-25 17:59:21 -07:00
committed by Alex Waterman
parent 20235407ff
commit b3b968b423
1 changed files with 0 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
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@@ -46,7 +46,6 @@ enum {
TEGRA_VGPU_CMD_ABORT = 2,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX = 3,
TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX = 4,
TEGRA_VGPU_CMD_GET_ATTRIBUTE = 5,
TEGRA_VGPU_CMD_MAP_BAR1 = 6,
TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7,
TEGRA_VGPU_CMD_AS_BIND_SHARE = 8,
@@ -59,9 +58,7 @@ enum {
TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC = 17,
TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX = 20,
TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX = 21,
TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX = 22,
TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX = 23,
TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX = 24,
TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX = 25,
TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX = 26,
TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL = 27,
@@ -75,16 +72,12 @@ enum {
TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE = 35,
TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE = 36,
TEGRA_VGPU_CMD_REG_OPS = 37,
TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY = 38,
TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE = 39,
TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE = 40,
TEGRA_VGPU_CMD_FECS_TRACE_ENABLE = 41,
TEGRA_VGPU_CMD_FECS_TRACE_DISABLE = 42,
TEGRA_VGPU_CMD_FECS_TRACE_POLL = 43,
TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER = 44,
TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE = 45,
TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE = 46,
TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47,
TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48,
TEGRA_VGPU_CMD_GR_CTX_FREE = 49,
TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52,