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gpu: nvgpu: ga10b: update NVRISCV LSPMU

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- Set NVRISCV LSPMU app version to 0.
- Setting app version to 0 helps to load and boot
  multiple LSPMU ucode's without modifying the
  NVGPU driver.
- Add support for PMU NVRISCV prod and dbg bin's.
- This is corresponding change to LSPMU MPSK CL
  https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2576049

JIRA NVGPU-7061

Change-Id: I800953ca97af3badde1983aa99e09b4fe7453203
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2575341
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2021-08-12 12:09:27 +00:00
committed by mobile promotions
parent a743596697
commit b9696ee643
2 changed files with 19 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/nvgpu/common/pmu/fw/fw.c
View File

@@ -40,6 +40,9 @@
#define NVGPU_PMU_UCODE_NEXT_IMAGE "gpmu_ucode_next_image.bin"
#define NVGPU_PMU_UCODE_NEXT_DESC "gpmu_ucode_next_desc.bin"
#define NVGPU_PMU_UCODE_NEXT_SIG "pmu_pkc_sig.bin"
#define NVGPU_PMU_UCODE_NEXT_PROD_IMAGE "gpmu_ucode_next_prod_image.bin"
#define NVGPU_PMU_UCODE_NEXT_PROD_DESC "gpmu_ucode_next_prod_desc.bin"
#define NVGPU_PMU_UCODE_NEXT_PROD_SIG "pmu_pkc_prod_sig.bin"
void nvgpu_pmu_fw_get_cmd_line_args_offset(struct gk20a *g,
u32 *args_offset)
@@ -269,6 +272,8 @@ static int pmu_fw_init_ops(struct gk20a *g, struct nvgpu_pmu *pmu)
ncore_desc = (struct falcon_next_core_ucode_desc *)(void *)
rtos_fw->fw_desc->data;
app_version = ncore_desc->app_version;
nvgpu_pmu_dbg(g, "app version %d ", app_version);
app_version = 0;
} else {
desc = (struct pmu_ucode_desc *)(void *)rtos_fw->fw_desc->data;
app_version = desc->app_version;
@@ -304,10 +309,19 @@ int nvgpu_pmu_init_pmu_fw(struct gk20a *g, struct nvgpu_pmu *pmu,
*rtos_fw_p = rtos_fw;
if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
nvgpu_pmu_dbg(g, "FW read for RISCV/PKC\n");
err = pmu_fw_read(g, NVGPU_PMU_UCODE_NEXT_IMAGE,
NVGPU_PMU_UCODE_NEXT_DESC,
NVGPU_PMU_UCODE_NEXT_SIG);
if (g->ops.pmu.is_debug_mode_enabled(g)) {
nvgpu_pmu_dbg(g, "FW read for DBG RISCV/PKC");
err = pmu_fw_read(g,
NVGPU_PMU_UCODE_NEXT_IMAGE,
NVGPU_PMU_UCODE_NEXT_DESC,
NVGPU_PMU_UCODE_NEXT_SIG);
} else {
nvgpu_pmu_dbg(g, "FW read for PROD RISCV/PKC");
err = pmu_fw_read(g,
NVGPU_PMU_UCODE_NEXT_PROD_IMAGE,
NVGPU_PMU_UCODE_NEXT_PROD_DESC,
NVGPU_PMU_UCODE_NEXT_PROD_SIG);
}
} else {
nvgpu_pmu_dbg(g, "FW read for Falcon/AES\n");
err = pmu_fw_read(g, NVGPU_PMU_UCODE_IMAGE,

2
drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c
View File

@@ -40,7 +40,7 @@
#include <nvgpu/pmu/seq.h>
/* PMU F/W version */
#define APP_VERSION_NVGPU_NEXT_CORE 30187066U
#define APP_VERSION_NVGPU_NEXT_CORE 0U
#define APP_VERSION_NVGPU_NEXT 29323513U
#define APP_VERSION_TU10X 28084434U
#define APP_VERSION_GV11B 25005711U