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gpu: nvgpu: add check_warp_esr_error hal

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Set check_warp_esr_error hal pointer to
gv11b_gr_check_warp_esr_error hal function.

Jira NVGPU-4867

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: Ib014c5ff2456836af2fe89f849f37991fe52844e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331804
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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This commit is contained in:
Vinod G
2020-04-20 18:32:49 -07:00
committed by Alex Waterman
parent d013e42f60
commit bb93223a21
5 changed files with 6 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
View File

@@ -486,7 +486,7 @@ static int gr_gv11b_handle_warp_esr_error_mmu_nack(struct gk20a *g,
return err;
}
static bool gr_gv11b_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error)
bool gv11b_gr_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error)
{
u32 index = 0U;
bool esr_err = false;
@@ -559,7 +559,7 @@ static int gr_gv11b_handle_all_warp_esr_errors(struct gk20a *g,
/*
* Check for an esr error
*/
is_esr_error = gr_gv11b_check_warp_esr_error(g, warp_esr_error);
is_esr_error = g->ops.gr.check_warp_esr_error(g, warp_esr_error);
if (!is_esr_error) {
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
"No ESR error, Skip RC recovery and Trigger CILP");

1
drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h
View File

@@ -49,6 +49,7 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
int gv11b_gr_clear_sm_error_state(struct gk20a *g,
struct nvgpu_channel *ch, u32 sm_id);
bool gv11b_gr_sm_debugger_attached(struct gk20a *g);
bool gv11b_gr_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error);
void gv11b_gr_suspend_single_sm(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm,
u32 global_esr_mask, bool check_errors);

1
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -370,6 +370,7 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
.set_debug_mode = gm20b_gr_set_debug_mode,
.set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode,
.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
.check_warp_esr_error = gv11b_gr_check_warp_esr_error,
#endif /* CONFIG_NVGPU_DEBUGGER */
.ecc = {
.detect = gv11b_ecc_detect_enabled_units,

1
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -405,6 +405,7 @@ static const struct gpu_ops tu104_ops = {
.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
.set_debug_mode = gm20b_gr_set_debug_mode,
.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
.check_warp_esr_error = gv11b_gr_check_warp_esr_error,
#endif /* CONFIG_NVGPU_DEBUGGER */
.ecc = {
.detect = NULL,

1
drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
View File

@@ -1189,6 +1189,7 @@ struct gops_gr {
struct nvgpu_channel *ch, bool enable);
bool (*esr_bpt_pending_events)(u32 global_esr,
enum nvgpu_event_id_type bpt_event);
bool (*check_warp_esr_error)(struct gk20a *g, u32 warp_esr_error);
#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
int (*set_boosted_ctx)(struct nvgpu_channel *ch, bool boost);
#endif