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gpu: nvgpu: add gops.fifo.check_tsg_ctxsw_timeout/check_ch_ctxsw_timeout

Browse Source 
RM Server acts differently for ctxsw timeout check. It won't check
GP_GET or accumulated timeouts, but notify guest and go to recovery.

Jira VQRM-3058

Change-Id: I428aea34dc517311eb7e73feb556145e916309fb
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1679706
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2018-03-16 15:56:44 -07:00
committed by mobile promotions
parent c5f03db98a
commit bcab5c1486
9 changed files with 20 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -2216,10 +2216,10 @@ bool gk20a_fifo_handle_sched_error(struct gk20a *g)
bool verbose = false;
if (is_tsg) {
ret = gk20a_fifo_check_tsg_ctxsw_timeout(
ret = g->ops.fifo.check_tsg_ctxsw_timeout(
&f->tsg[id], &verbose, &ms);
} else {
ret = gk20a_fifo_check_ch_ctxsw_timeout(
ret = g->ops.fifo.check_ch_ctxsw_timeout(
&f->channel[id], &verbose, &ms);
}

4
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -629,6 +629,10 @@ struct gpu_ops {
u32 (*get_preempt_timeout)(struct gk20a *g);
void (*post_event_id)(struct tsg_gk20a *tsg, int event_id);
void (*ch_abort_clean_up)(struct channel_gk20a *ch);
bool (*check_tsg_ctxsw_timeout)(struct tsg_gk20a *tsg,
bool *verbose, u32 *ms);
bool (*check_ch_ctxsw_timeout)(struct channel_gk20a *ch,
bool *verbose, u32 *ms);
#ifdef CONFIG_TEGRA_GK20A_NVHOST
int (*alloc_syncpt_buf)(struct channel_gk20a *c,
u32 syncpt_id, struct nvgpu_mem *syncpt_buf);

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
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@@ -439,6 +439,8 @@ static const struct gpu_ops gm20b_ops = {
.tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
.post_event_id = gk20a_tsg_event_id_post_event,
.ch_abort_clean_up = gk20a_channel_abort_clean_up,
.check_tsg_ctxsw_timeout = gk20a_fifo_check_tsg_ctxsw_timeout,
.check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,

2
drivers/gpu/nvgpu/gp106/hal_gp106.c
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@@ -500,6 +500,8 @@ static const struct gpu_ops gp106_ops = {
.tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
.post_event_id = gk20a_tsg_event_id_post_event,
.ch_abort_clean_up = gk20a_channel_abort_clean_up,
.check_tsg_ctxsw_timeout = gk20a_fifo_check_tsg_ctxsw_timeout,
.check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
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@@ -471,6 +471,8 @@ static const struct gpu_ops gp10b_ops = {
.tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
.post_event_id = gk20a_tsg_event_id_post_event,
.ch_abort_clean_up = gk20a_channel_abort_clean_up,
.check_tsg_ctxsw_timeout = gk20a_fifo_check_tsg_ctxsw_timeout,
.check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -512,6 +512,8 @@ static const struct gpu_ops gv100_ops = {
.tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
.post_event_id = gk20a_tsg_event_id_post_event,
.ch_abort_clean_up = gk20a_channel_abort_clean_up,
.check_tsg_ctxsw_timeout = gk20a_fifo_check_tsg_ctxsw_timeout,
.check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gv11b_fifo_free_syncpt_buf,

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
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@@ -529,6 +529,8 @@ static const struct gpu_ops gv11b_ops = {
.tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
.post_event_id = gk20a_tsg_event_id_post_event,
.ch_abort_clean_up = gk20a_channel_abort_clean_up,
.check_tsg_ctxsw_timeout = gk20a_fifo_check_tsg_ctxsw_timeout,
.check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gv11b_fifo_free_syncpt_buf,

2
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -345,6 +345,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.tsg_unbind_channel = vgpu_tsg_unbind_channel,
.post_event_id = gk20a_tsg_event_id_post_event,
.ch_abort_clean_up = gk20a_channel_abort_clean_up,
.check_tsg_ctxsw_timeout = gk20a_fifo_check_tsg_ctxsw_timeout,
.check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,

2
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -388,6 +388,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.tsg_unbind_channel = vgpu_tsg_unbind_channel,
.post_event_id = gk20a_tsg_event_id_post_event,
.ch_abort_clean_up = gk20a_channel_abort_clean_up,
.check_tsg_ctxsw_timeout = gk20a_fifo_check_tsg_ctxsw_timeout,
.check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gv11b_fifo_free_syncpt_buf,